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[/] [edge/] [trunk/] [HW/] [Verilog/] [id_ex_pipereg.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////
//                                                              //
//  ID/EX pipeline register                                     //
//                                                              //
//  This file is part of the Edge project                       //
//  http://www.opencores.org/project,edge                       //
//                                                              //
//  Description                                                 //
//  Pipeline register lies between decode and execute stages    //
//                                                              //
//  Author(s):                                                  //
//      - Hesham AL-Matary, heshamelmatary@gmail.com            //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2014 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
module id_ex_pipereg
#
(
  parameter N=32,
  parameter M=5
)
(
  input clk,
  input reset,
  input en,
  input[N-1:0] read_value1_in,
  input[N-1:0] read_value2_in,
  input[M-1:0] Rs_in,
  input[M-1:0] Rt_in,
  input[M-1:0] Rd_in,
  input[N-1:0] SignImm_in,
  input[N-1:0] PCplus4_in,
 
  input[N-1:0] IR_in,
  input[5:0] opcode_in,
  input RegWrite_in,
  input[1:0] WBResultSelect_in,
  input MemWrite_in,
  input Branch_in,
  input Jump_in,
  input JumpR_in,
  input[3:0] ALUControl_in,
  input ALUSrcB_in,
  input RegDst_in,
  input UpperImm_in,
  input[2:0] BHW_in, /* byte or halfword or word ? */
  input ALUComp_in, /* Complement the ALU output */
  input[1:0] Shift_type_in,
  input ShiftAmtVar_in,
  input Shifter_or_ALU_in,
  input[1:0] MulDivRF_in,
  input hiEN_in,
  input loEN_in,
  input link_in,
 
  /* Coprocessor0 and exceptions signals */
  input undefinedEx_in,
  input breakEx_in,
  input divbyZero_in,
  input syscallEx_in,
 
  input[M-1:0] CP0_wa_in,
  input[M-1:0] CP0_ra_in,
  input[1:0] CP0_Inst_in,
  input[N-1:0] CP0_dout_in,
  input[N-1:0] CP0_din_in,
 
  /* Memory Reference size */
  input[1:0] MemRefSize_in,
 
  output[N-1:0] read_value1_out,
  output[N-1:0] read_value2_out,
  output[M-1:0] Rs_out,
  output[M-1:0] Rt_out,
  output[M-1:0] Rd_out,
  output[N-1:0] SignImm_out,
  output[N-1:0] PCplus4_out,
 
  output RegWrite_out,
  output[1:0] WBResultSelect_out,
  output MemWrite_out,
  output Branch_out,
  output Jump_out,
  output JumpR_out,
  output[3:0] ALUControl_out,
  output ALUSrcB_out,
  output RegDst_out,
  output UpperImm_out,
  output[2:0] BHW_out, /* byte or halfword or word ? */
  output ALUComp_out,
  output[1:0] Shift_type_out,
  output ShiftAmtVar_out,
  output Shifter_or_ALU_out,
  output[1:0] MulDivRF_out,
  output hiEN_out,
  output loEN_out,
  output [5:0] opcode_out,
  output[N-1:0] IR_out,
  output link_out,
 
  /* Coprocessor0 and exceptions signals */
  output undefinedEx_out,
  output breakEx_out,
  output divbyZero_out,
  output syscallEx_out,
 
  output[M-1:0] CP0_wa_out,
  output[M-1:0] CP0_ra_out,
  output[1:0] CP0_Inst_out,
  output[N-1:0] CP0_dout_out,
  output[N-1:0] CP0_din_out,
 
  output[1:0] MemRefSize_out
 
);
 
/* Instruction register */
register IR
(
  .clk(clk), .reset(reset), .en(en),
  .d(IR_in),
  .q(IR_out)
);
 
/* Opcode */
register #(6)
opcode
(
  .clk(clk), .reset(reset), .en(en),
  .d(opcode_in),
  .q(opcode_out)
);
 
/* data values registers */
register rd1
(
  .clk(clk), .reset(reset), .en(en),
  .d(read_value1_in),
  .q(read_value1_out)
);
 
register rd2
(
  .clk(clk), .reset(reset), .en(en),
  .d(read_value2_in),
  .q(read_value2_out)
);
 
/* Rs, Rt and Rd addresses */
register #(5) Rs
(
  .clk(clk), .reset(reset), .en(en),
  .d(Rs_in),
  .q(Rs_out)
);
 
register #(5)
Rt
(
  .clk(clk), .reset(reset), .en(en),
  .d(Rt_in),
  .q(Rt_out)
);
 
register #(5)
Rd
(
  .clk(clk), .reset(reset), .en(en),
  .d(Rd_in),
  .q(Rd_out)
);
 
/* Sign Immediate value */
register sign_imm
(
  .clk(clk), .reset(reset), .en(en),
  .d(SignImm_in),
  .q(SignImm_out)
);
 
/* PC + 4 register */
register PCplus4
(
  .clk(clk), .reset(reset), .en(en),
  .d(PCplus4_in),
  .q(PCplus4_out)
);
 
/* Control Signal */
register #(1)
RegWrite
(
  .clk(clk), .reset(reset), .en(en),
  .d(RegWrite_in),
  .q(RegWrite_out)
);
 
register #(2)
WBResultSelect
(
  .clk(clk), .reset(reset), .en(en),
  .d(WBResultSelect_in),
  .q(WBResultSelect_out)
);
 
register #(1)
MemWrite
(
  .clk(clk), .reset(reset), .en(en),
  .d(MemWrite_in),
  .q(MemWrite_out)
);
 
register #(1)
Branch
(
  .clk(clk), .reset(reset), .en(en),
  .d(Branch_in),
  .q(Branch_out)
);
 
register #(1)
Jump
(
  .clk(clk), .reset(reset), .en(en),
  .d(Jump_in),
  .q(Jump_out)
);
 
register #(1)
JumpR
(
  .clk(clk), .reset(reset), .en(en),
  .d(JumpR_in),
  .q(JumpR_out)
);
 
register #(1)
link
(
  .clk(clk), .reset(reset), .en(en),
  .d(link_in),
  .q(link_out)
);
 
register #(4)
ALUControl
(
  .clk(clk), .reset(reset), .en(en),
  .d(ALUControl_in),
  .q(ALUControl_out)
);
 
register #(1)
ALUSrcB
(
  .clk(clk), .reset(reset), .en(en),
  .d(ALUSrcB_in),
  .q(ALUSrcB_out)
);
 
register #(1)
RegDst
(
  .clk(clk), .reset(reset), .en(en),
  .d(RegDst_in),
  .q(RegDst_out)
);
 
register #(1)
UpperImm
(
  .clk(clk), .reset(reset), .en(en),
  .d(UpperImm_in),
  .q(UpperImm_out)
);
 
register #(3)
BHW
(
  .clk(clk), .reset(reset), .en(en),
  .d(BHW_in),
  .q(BHW_out)
);
 
register #(1)
ALUComp
(
  .clk(clk), .reset(reset), .en(en),
  .d(ALUComp_in),
  .q(ALUComp_out)
);
 
register #(2)
Shift_type
(
  .clk(clk), .reset(reset), .en(en),
  .d(Shift_type_in),
  .q(Shift_type_out)
);
 
register #(1)
ShiftAmtVar
(
  .clk(clk), .reset(reset), .en(en),
  .d(ShiftAmtVar_in),
  .q(ShiftAmtVar_out)
);
 
register #(1)
Shifter_or_ALU
(
  .clk(clk), .reset(reset), .en(en),
  .d(Shifter_or_ALU_in),
  .q(Shifter_or_ALU_out)
);
 
register #(2)
MulDivRF
(
  .clk(clk), .reset(reset), .en(en),
  .d(MulDivRF_in),
  .q(MulDivRF_out)
);
 
register #(1)
hiEN
(
  .clk(clk), .reset(reset), .en(en),
  .d(hiEN_in),
  .q(hiEN_out)
);
 
register #(1)
loEN
(
  .clk(clk), .reset(reset), .en(en),
  .d(loEN_in),
  .q(loEN_out)
);
 
 
/* Coprocessor zero related */
register #(1)
undefinedEx
(
  .clk(clk), .reset(reset), .en(en),
  .d(undefinedEx_in),
  .q(undefinedEx_out)
);
 
register #(1)
breakEx
(
  .clk(clk), .reset(reset), .en(en),
  .d(breakEx_in),
  .q(breakEx_out)
);
 
register #(1)
divbyZero
(
  .clk(clk), .reset(reset), .en(en),
  .d(divbyZero_in),
  .q(divbyZero_out)
);
 
register #(1)
syscallEx
(
  .clk(clk), .reset(reset), .en(en),
  .d(syscallEx_in),
  .q(syscallEx_out)
);
 
register #(5)
CP0_wa
(
  .clk(clk), .reset(reset), .en(en),
  .d(CP0_wa_in),
  .q(CP0_wa_out)
);
 
register #(5)
CP0_ra
(
  .clk(clk), .reset(reset), .en(en),
  .d(CP0_ra_in),
  .q(CP0_ra_out)
);
 
register #(2)
CP0_Inst
(
  .clk(clk), .reset(reset), .en(en),
  .d(CP0_Inst_in),
  .q(CP0_Inst_out)
);
 
register CP0_dout
(
  .clk(clk), .reset(reset), .en(en),
  .d(CP0_dout_in),
  .q(CP0_dout_out)
);
 
register CP0_din
(
  .clk(clk), .reset(reset), .en(en),
  .d(CP0_din_in),
  .q(CP0_din_out)
);
 
/* Memory referece sizes */
register #(2)
MemRefSize
(
  .clk(clk), .reset(reset), .en(en),
  .d(MemRefSize_in),
  .q(MemRefSize_out)
);
 
endmodule

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[/] [edge/] [trunk/] [HW/] [Verilog/] [id_ex_pipereg.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	heshamelma	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// ID/EX pipeline register //`
4			`// //`
5			`// This file is part of the Edge project //`
6			`// http://www.opencores.org/project,edge //`
7			`// //`
8			`// Description //`
9			`// Pipeline register lies between decode and execute stages //`
10			`// //`
11			`// Author(s): //`
12			`// - Hesham AL-Matary, heshamelmatary@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2014 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41			`module id_ex_pipereg`
42			`#`
43			`(`
44			`parameter N=32,`
45			`parameter M=5`
46			`)`
47			`(`
48			`input clk,`
49			`input reset,`
50			`input en,`
51			`input[N-1:0] read_value1_in,`
52			`input[N-1:0] read_value2_in,`
53			`input[M-1:0] Rs_in,`
54			`input[M-1:0] Rt_in,`
55			`input[M-1:0] Rd_in,`
56			`input[N-1:0] SignImm_in,`
57			`input[N-1:0] PCplus4_in,`
58
59			`input[N-1:0] IR_in,`
60			`input[5:0] opcode_in,`
61			`input RegWrite_in,`
62			`input[1:0] WBResultSelect_in,`
63			`input MemWrite_in,`
64			`input Branch_in,`
65			`input Jump_in,`
66			`input JumpR_in,`
67			`input[3:0] ALUControl_in,`
68			`input ALUSrcB_in,`
69			`input RegDst_in,`
70			`input UpperImm_in,`
71			`input[2:0] BHW_in, /* byte or halfword or word ? */`
72			`input ALUComp_in, /* Complement the ALU output */`
73			`input[1:0] Shift_type_in,`
74			`input ShiftAmtVar_in,`
75			`input Shifter_or_ALU_in,`
76			`input[1:0] MulDivRF_in,`
77			`input hiEN_in,`
78			`input loEN_in,`
79			`input link_in,`
80
81			`/* Coprocessor0 and exceptions signals */`
82			`input undefinedEx_in,`
83			`input breakEx_in,`
84			`input divbyZero_in,`
85			`input syscallEx_in,`
86
87			`input[M-1:0] CP0_wa_in,`
88			`input[M-1:0] CP0_ra_in,`
89			`input[1:0] CP0_Inst_in,`
90			`input[N-1:0] CP0_dout_in,`
91			`input[N-1:0] CP0_din_in,`
92
93			`/* Memory Reference size */`
94			`input[1:0] MemRefSize_in,`
95
96			`output[N-1:0] read_value1_out,`
97			`output[N-1:0] read_value2_out,`
98			`output[M-1:0] Rs_out,`
99			`output[M-1:0] Rt_out,`
100			`output[M-1:0] Rd_out,`
101			`output[N-1:0] SignImm_out,`
102			`output[N-1:0] PCplus4_out,`
103
104			`output RegWrite_out,`
105			`output[1:0] WBResultSelect_out,`
106			`output MemWrite_out,`
107			`output Branch_out,`
108			`output Jump_out,`
109			`output JumpR_out,`
110			`output[3:0] ALUControl_out,`
111			`output ALUSrcB_out,`
112			`output RegDst_out,`
113			`output UpperImm_out,`
114			`output[2:0] BHW_out, /* byte or halfword or word ? */`
115			`output ALUComp_out,`
116			`output[1:0] Shift_type_out,`
117			`output ShiftAmtVar_out,`
118			`output Shifter_or_ALU_out,`
119			`output[1:0] MulDivRF_out,`
120			`output hiEN_out,`
121			`output loEN_out,`
122			`output [5:0] opcode_out,`
123			`output[N-1:0] IR_out,`
124			`output link_out,`
125
126			`/* Coprocessor0 and exceptions signals */`
127			`output undefinedEx_out,`
128			`output breakEx_out,`
129			`output divbyZero_out,`
130			`output syscallEx_out,`
131
132			`output[M-1:0] CP0_wa_out,`
133			`output[M-1:0] CP0_ra_out,`
134			`output[1:0] CP0_Inst_out,`
135			`output[N-1:0] CP0_dout_out,`
136			`output[N-1:0] CP0_din_out,`
137
138			`output[1:0] MemRefSize_out`
139
140			`);`
141
142			`/* Instruction register */`
143			`register IR`
144			`(`
145			`.clk(clk), .reset(reset), .en(en),`
146			`.d(IR_in),`
147			`.q(IR_out)`
148			`);`
149
150			`/* Opcode */`
151			`register #(6)`
152			`opcode`
153			`(`
154			`.clk(clk), .reset(reset), .en(en),`
155			`.d(opcode_in),`
156			`.q(opcode_out)`
157			`);`
158
159			`/* data values registers */`
160			`register rd1`
161			`(`
162			`.clk(clk), .reset(reset), .en(en),`
163			`.d(read_value1_in),`
164			`.q(read_value1_out)`
165			`);`
166
167			`register rd2`
168			`(`
169			`.clk(clk), .reset(reset), .en(en),`
170			`.d(read_value2_in),`
171			`.q(read_value2_out)`
172			`);`
173
174			`/* Rs, Rt and Rd addresses */`
175			`register #(5) Rs`
176			`(`
177			`.clk(clk), .reset(reset), .en(en),`
178			`.d(Rs_in),`
179			`.q(Rs_out)`
180			`);`
181
182			`register #(5)`
183			`Rt`
184			`(`
185			`.clk(clk), .reset(reset), .en(en),`
186			`.d(Rt_in),`
187			`.q(Rt_out)`
188			`);`
189
190			`register #(5)`
191			`Rd`
192			`(`
193			`.clk(clk), .reset(reset), .en(en),`
194			`.d(Rd_in),`
195			`.q(Rd_out)`
196			`);`
197
198			`/* Sign Immediate value */`
199			`register sign_imm`
200			`(`
201			`.clk(clk), .reset(reset), .en(en),`
202			`.d(SignImm_in),`
203			`.q(SignImm_out)`
204			`);`
205
206			`/* PC + 4 register */`
207			`register PCplus4`
208			`(`
209			`.clk(clk), .reset(reset), .en(en),`
210			`.d(PCplus4_in),`
211			`.q(PCplus4_out)`
212			`);`
213
214			`/* Control Signal */`
215			`register #(1)`
216			`RegWrite`
217			`(`
218			`.clk(clk), .reset(reset), .en(en),`
219			`.d(RegWrite_in),`
220			`.q(RegWrite_out)`
221			`);`
222
223			`register #(2)`
224			`WBResultSelect`
225			`(`
226			`.clk(clk), .reset(reset), .en(en),`
227			`.d(WBResultSelect_in),`
228			`.q(WBResultSelect_out)`
229			`);`
230
231			`register #(1)`
232			`MemWrite`
233			`(`
234			`.clk(clk), .reset(reset), .en(en),`
235			`.d(MemWrite_in),`
236			`.q(MemWrite_out)`
237			`);`
238
239			`register #(1)`
240			`Branch`
241			`(`
242			`.clk(clk), .reset(reset), .en(en),`
243			`.d(Branch_in),`
244			`.q(Branch_out)`
245			`);`
246
247			`register #(1)`
248			`Jump`
249			`(`
250			`.clk(clk), .reset(reset), .en(en),`
251			`.d(Jump_in),`
252			`.q(Jump_out)`
253			`);`
254
255			`register #(1)`
256			`JumpR`
257			`(`
258			`.clk(clk), .reset(reset), .en(en),`
259			`.d(JumpR_in),`
260			`.q(JumpR_out)`
261			`);`
262
263			`register #(1)`
264			`link`
265			`(`
266			`.clk(clk), .reset(reset), .en(en),`
267			`.d(link_in),`
268			`.q(link_out)`
269			`);`
270
271			`register #(4)`
272			`ALUControl`
273			`(`
274			`.clk(clk), .reset(reset), .en(en),`
275			`.d(ALUControl_in),`
276			`.q(ALUControl_out)`
277			`);`
278
279			`register #(1)`
280			`ALUSrcB`
281			`(`
282			`.clk(clk), .reset(reset), .en(en),`
283			`.d(ALUSrcB_in),`
284			`.q(ALUSrcB_out)`
285			`);`
286
287			`register #(1)`
288			`RegDst`
289			`(`
290			`.clk(clk), .reset(reset), .en(en),`
291			`.d(RegDst_in),`
292			`.q(RegDst_out)`
293			`);`
294
295			`register #(1)`
296			`UpperImm`
297			`(`
298			`.clk(clk), .reset(reset), .en(en),`
299			`.d(UpperImm_in),`
300			`.q(UpperImm_out)`
301			`);`
302
303			`register #(3)`
304			`BHW`
305			`(`
306			`.clk(clk), .reset(reset), .en(en),`
307			`.d(BHW_in),`
308			`.q(BHW_out)`
309			`);`
310
311			`register #(1)`
312			`ALUComp`
313			`(`
314			`.clk(clk), .reset(reset), .en(en),`
315			`.d(ALUComp_in),`
316			`.q(ALUComp_out)`
317			`);`
318
319			`register #(2)`
320			`Shift_type`
321			`(`
322			`.clk(clk), .reset(reset), .en(en),`
323			`.d(Shift_type_in),`
324			`.q(Shift_type_out)`
325			`);`
326
327			`register #(1)`
328			`ShiftAmtVar`
329			`(`
330			`.clk(clk), .reset(reset), .en(en),`
331			`.d(ShiftAmtVar_in),`
332			`.q(ShiftAmtVar_out)`
333			`);`
334
335			`register #(1)`
336			`Shifter_or_ALU`
337			`(`
338			`.clk(clk), .reset(reset), .en(en),`
339			`.d(Shifter_or_ALU_in),`
340			`.q(Shifter_or_ALU_out)`
341			`);`
342
343			`register #(2)`
344			`MulDivRF`
345			`(`
346			`.clk(clk), .reset(reset), .en(en),`
347			`.d(MulDivRF_in),`
348			`.q(MulDivRF_out)`
349			`);`
350
351			`register #(1)`
352			`hiEN`
353			`(`
354			`.clk(clk), .reset(reset), .en(en),`
355			`.d(hiEN_in),`
356			`.q(hiEN_out)`
357			`);`
358
359			`register #(1)`
360			`loEN`
361			`(`
362			`.clk(clk), .reset(reset), .en(en),`
363			`.d(loEN_in),`
364			`.q(loEN_out)`
365			`);`
366
367
368			`/* Coprocessor zero related */`
369			`register #(1)`
370			`undefinedEx`
371			`(`
372			`.clk(clk), .reset(reset), .en(en),`
373			`.d(undefinedEx_in),`
374			`.q(undefinedEx_out)`
375			`);`
376
377			`register #(1)`
378			`breakEx`
379			`(`
380			`.clk(clk), .reset(reset), .en(en),`
381			`.d(breakEx_in),`
382			`.q(breakEx_out)`
383			`);`
384
385			`register #(1)`
386			`divbyZero`
387			`(`
388			`.clk(clk), .reset(reset), .en(en),`
389			`.d(divbyZero_in),`
390			`.q(divbyZero_out)`
391			`);`
392
393			`register #(1)`
394			`syscallEx`
395			`(`
396			`.clk(clk), .reset(reset), .en(en),`
397			`.d(syscallEx_in),`
398			`.q(syscallEx_out)`
399			`);`
400
401			`register #(5)`
402			`CP0_wa`
403			`(`
404			`.clk(clk), .reset(reset), .en(en),`
405			`.d(CP0_wa_in),`
406			`.q(CP0_wa_out)`
407			`);`
408
409			`register #(5)`
410			`CP0_ra`
411			`(`
412			`.clk(clk), .reset(reset), .en(en),`
413			`.d(CP0_ra_in),`
414			`.q(CP0_ra_out)`
415			`);`
416
417			`register #(2)`
418			`CP0_Inst`
419			`(`
420			`.clk(clk), .reset(reset), .en(en),`
421			`.d(CP0_Inst_in),`
422			`.q(CP0_Inst_out)`
423			`);`
424
425			`register CP0_dout`
426			`(`
427			`.clk(clk), .reset(reset), .en(en),`
428			`.d(CP0_dout_in),`
429			`.q(CP0_dout_out)`
430			`);`
431
432			`register CP0_din`
433			`(`
434			`.clk(clk), .reset(reset), .en(en),`
435			`.d(CP0_din_in),`
436			`.q(CP0_din_out)`
437			`);`
438
439			`/* Memory referece sizes */`
440			`register #(2)`
441			`MemRefSize`
442			`(`
443			`.clk(clk), .reset(reset), .en(en),`
444			`.d(MemRefSize_in),`
445			`.q(MemRefSize_out)`
446			`);`
447
448			`endmodule`