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[/] [edge/] [trunk/] [HW/] [Verilog/] [mux_WBResult.v] - Blame information for rev 2

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1 2 heshamelma
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Write back result select mux                                //
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//                                                              //
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//  This file is part of the Edge project                       //
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//  http://www.opencores.org/project,edge                       //
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//                                                              //
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//  Description                                                 //
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//  Multiplixer to choose from different result size            //               
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//                                                              //
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//  Author(s):                                                  //
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//      - Hesham AL-Matary, heshamelmatary@gmail.com            //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2014 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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`define loadWord                3'b000 /* LW (normal load word) */
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`define loadSByte               3'b001 /* LB (load signed byte) */
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`define loadSHWord      3'b010 /* LH (load signed half word) */
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`define loadUByte               3'b011 /* LBU (load unsigned byte) */
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`define loadUHWord      3'b100 /* LHU (load unsgined half word) */
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module mux_WBResult
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#
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(
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  parameter N=32
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)
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(
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  input[N-1:0] Word,
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  input[N-1:0] SByte,
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  input[N-1:0] SHWord,
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  input[N-1:0] UByte,
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  input[N-1:0] UHWord,
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  input[2:0] s,
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  output reg[N-1:0] WBResult
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);
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always @(*)
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  case (s)
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    `loadWord: WBResult = Word;
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    `loadSByte: WBResult = SByte;
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    `loadSHWord: WBResult = SHWord;
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    `loadUByte: WBResult = UByte;
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    `loadUHWord: WBResult = UHWord;
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    default: WBResult = Word;
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  endcase
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endmodule

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