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heshamelma |
//////////////////////////////////////////////////////////////////
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// //
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// Register file for Edge core. //
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// //
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// This file is part of the Edge project //
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// http://www.opencores.org/project,edge //
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// //
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// Description //
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// General purpose 32 x 32 bit register file //
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// //
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// Author(s): //
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// - Hesham AL-Matary, heshamelmatary@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2014 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module regfile
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(
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clk,
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reset,
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ra1,
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ra2,
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wa3,
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we3,
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wd3,
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rd1,
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rd2
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);
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/* Bus size in bits for data */
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parameter N = 32;
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/* Bus size in bits for Addresses, the register file size should be 2**addr_size */
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parameter addr_size = 5;
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/* Specify IO sizes */
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input wire clk;
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input wire reset;
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input wire[addr_size-1:0] ra1;
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input wire[addr_size-1:0]ra2;
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input wire[addr_size-1:0]wa3;
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input wire we3;
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input wire[N-1:0] wd3;
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output reg[N-1:0] rd1;
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output reg[N-1:0] rd2;
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integer i;
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/* Define register file*/
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reg[N-1:0] rf [(2**addr_size)-1:0];
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initial
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begin
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for(i=0; i<32; i=i+1)
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rf[i] = 0;
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end
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always @(posedge clk)
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if (we3)
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rf[wa3] = wd3;
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always @(negedge clk)
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begin
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rd1 = (ra1 != 0)? rf[ra1]:0;
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rd2 = (ra2 != 0)? rf[ra2]:0;
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end
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endmodule
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