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heshamelma |
//////////////////////////////////////////////////////////////////
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// //
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// Reset logic for Edge core //
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// //
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// This file is part of the Edge project //
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// http://www.opencores.org/project,edge //
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// //
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// Description //
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// Handling reset logic for Edge core jump to PC = 0 //
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// //
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// Author(s): //
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// - Hesham AL-Matary, heshamelmatary@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2014 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module reset_logic
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#
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(
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parameter RESET_AFTER = 1 // Produce 0 signal after #RESET_AFTER clock cycles
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)
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(
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input reset_interrupt,
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input clk,
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output reset
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);
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reg[1:0] counter = 0;
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reg res_buffer = 1;
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always @(posedge clk)
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begin
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/* Reset after specified clock cycles */
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/*counter = counter + 1;
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if(counter == RESET_AFTER + 1)
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res_buffer = 0;
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*/
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//res_buffer = 0;
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/* Only reset when reset button/signal pushed */
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if(reset_interrupt == 0)
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res_buffer = 0;
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else if(reset_interrupt == 1)
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res_buffer = 1;
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end
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assign reset = res_buffer;
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endmodule
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