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heshamelma |
//////////////////////////////////////////////////////////////////
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// //
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// Shift decoder for Edge Core //
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// //
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// This file is part of the Edge project //
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// http://www.opencores.org/project,edge //
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// //
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// Description //
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// Shift decoder is part of the main controller/decoder at //
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// decode stage. It decodes MIPS instruction and produces //
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// control signals for the shift unit.
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// //
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// Author(s): //
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// - Hesham AL-Matary, heshamelmatary@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2014 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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/* Shift unit control */
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`define SLL_CTRL 2'b00
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`define SRL_CTRL 2'b01
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`define SRA_CTRL 2'b10
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/* Shift Encoding */
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`define SLL_FUNCT 6'b000000 // 0
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`define SRL_FUNCT 6'b000010 // 2
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`define SRA_FUNCT 6'b000011 // 3
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`define SLLV_FUNCT 6'b000100 // 4
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`define SRLV_FUNCT 6'b000110 // 6
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`define SRAV_FUNCT 6'b000111 // 7
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module shifter_decoder
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(
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input[5:0] Funct,
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output reg ShiftAmtVar_out,
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output reg[1:0] Shift_type
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);
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always @*
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begin
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ShiftAmtVar_out = 1'b0;
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Shift_type <= 2'b00;
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case (Funct)
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`SLL_FUNCT : Shift_type <= `SLL_CTRL;
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`SLLV_FUNCT :
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begin
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Shift_type <= `SLL_CTRL;
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ShiftAmtVar_out = 1'b1;
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end
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`SRL_FUNCT : Shift_type <= `SRL_CTRL;
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`SRLV_FUNCT :
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begin
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Shift_type <= `SRL_CTRL;
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ShiftAmtVar_out = 1'b1;
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end
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`SRA_FUNCT : Shift_type <= `SRA_CTRL;
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`SRAV_FUNCT :
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begin
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Shift_type <= `SRA_CTRL;
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ShiftAmtVar_out = 1'b1;
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end
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endcase
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end
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endmodule
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