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/****************************************************************************************
 MODULE:                Sub Level Arithmatic Logic Unit Block
 
 FILE NAME:     alu.v
 VERSION:       1.0
 DATE:          September 28th, 2001
 AUTHOR:                Hossein Amidi
 COMPANY:       California Unique Electrical Co.
 CODE TYPE:     Register Transfer Level
 
 Instantiations:
 
 DESCRIPTION:
 Sub Level RTL Arithmatic Logic Unit block
 
 Hossein Amidi
 (C) September 2001
 California Unique Electric
 
***************************************************************************************/
 
`timescale 1ns / 1ps
 
module ALU (// Input
                                ALUSrcA,
                                ALUSrcB,
                                OpCode,
                                CurrentState,
                                // Output
                                ALUDataOut
                                );
 
// Parameter
parameter DataWidth = 32;
parameter OpcodeSize = 8;
parameter StateSize = 2;
parameter FunctionSize = 8;
 
// Instructions options
parameter  LDA = 8'h0;
parameter  STO = 8'h1;
parameter  ADD = 8'h2;
parameter  SUB = 8'h3;
parameter  JMP = 8'h4;
parameter  JGE = 8'h5;
parameter  JNE = 8'h6;
parameter  STP = 8'h7;
parameter  SHR = 8'h8;
parameter  SHL = 8'h9;
parameter  AND = 8'ha;
parameter  OR  = 8'hb;
parameter  XOR = 8'hc;
parameter  COM = 8'hd;
parameter  SWP = 8'he;
parameter  NOP = 8'hf;
 
// Instruction for Memory Map devices
parameter  MAP = 9'h64;
 
// Current State options
parameter Init                  = 2'b00;
parameter InstrFetch = 2'b01;
parameter InstrExec  = 2'b10;
 
// Function Select options
parameter FnAdd = 8'b0000_0000;
parameter FnSub = 8'b0000_0001;
parameter FnPassB = 8'b0000_0010;
parameter FnIncB        = 8'b0000_0011;
parameter FnShtR        = 8'b0000_0100;
parameter FnShtL        = 8'b0000_0101;
parameter FnAnd = 8'b0000_0110;
parameter FnOr  = 8'b0000_0111;
parameter FnXor = 8'b0000_1000;
parameter FnCom = 8'b0000_1001;
parameter FnSwp = 8'b0000_1010;
parameter FnNop   = 8'b0000_1011;
 
// Input
input [DataWidth - 1 : 0] ALUSrcA;
input [DataWidth - 1 : 0] ALUSrcB;
input [OpcodeSize - 1 : 0] OpCode;
input [StateSize - 1 : 0] CurrentState;
 
// Output
output [DataWidth - 1 : 0] ALUDataOut;
 
// Signal Assignments
reg [DataWidth - 1 : 0] ALUDataOut;
reg [FunctionSize - 1 : 0] FunctSel;
reg CIn;
 
wire [DataWidth - 1 : 0] AIn, BIn;
 
 
// Assignment
assign AIn = ALUSrcA;
assign BIn = ALUSrcB;
 
 
 
always @(OpCode or CurrentState)
begin
        if (CurrentState == InstrFetch)
        begin
                if (OpCode != STP) // In the Fetch cycle increment PC
                begin
                   FunctSel <= FnIncB;
                   CIn <= 1;
                end
        else
                begin
                   FunctSel <= FnPassB;
                   CIn <= 0;
                end
        end
        else
        if(CurrentState == InstrExec)
        begin
                case (OpCode)
                        LDA :
                        begin
                                FunctSel <= FnPassB;
                           CIn <= 0;
                        end
 
                        STO :
                        begin
                                FunctSel <= FnAdd;
                      CIn <= 0;
                   end
 
                        ADD :
                        begin
                FunctSel <= FnAdd;
                           CIn <= 0;
              end
 
                        SUB :
                        begin
                FunctSel <= FnSub;
                      CIn <= 0;
              end
 
                        JMP :
                        begin
                FunctSel <= FnPassB;
                CIn <= 0;
        end
 
                        JGE :
                        begin
                FunctSel <= FnPassB;
                CIn <= 0;
        end
 
                        JNE :
                        begin
                FunctSel <= FnPassB;
                      CIn <= 0;
        end
 
                        STP :
                        begin
                    FunctSel <= FnPassB;
                       CIn <= 0;
              end
 
                        SHR :
                        begin
                    FunctSel <= FnShtR;
                       CIn <= 0;
              end
 
                        SHL :
                        begin
                    FunctSel <= FnShtL;
                       CIn <= 0;
              end
 
                        AND :
                        begin
                    FunctSel <= FnAnd;
                       CIn <= 0;
              end
 
                        OR :
                        begin
                    FunctSel <= FnOr;
                       CIn <= 0;
              end
 
                        XOR :
                        begin
                    FunctSel <= FnXor;
                       CIn <= 0;
              end
 
                        COM :
                        begin
                    FunctSel <= FnCom;
                       CIn <= 0;
              end
 
                        SWP :
                        begin
                    FunctSel <= FnSwp;
                       CIn <= 0;
              end
 
                        NOP :
                        begin
                    FunctSel <= FnNop;
                       CIn <= 0;
              end
 
                        default :    ;
                endcase
        end
end
 
 
always @(AIn or BIn or CIn or FunctSel)
begin
        case (FunctSel)
                FnAdd           :    ALUDataOut <= AIn + BIn;
                FnSub           :    ALUDataOut <= AIn - BIn;
                FnPassB  :    ALUDataOut <= BIn;
                FnIncB   :    ALUDataOut <= BIn + CIn;
                FnShtR  :         ALUDataOut <= AIn >> 1;
                FnShtL  :         ALUDataOut <= AIn << 1;
                FnAnd   :         ALUDataOut <= AIn & BIn;
                FnOr    :         ALUDataOut <= AIn | BIn;
                FnXor   :         ALUDataOut <= AIn ^ BIn;
                FnCom   :         ALUDataOut <= ~BIn;
                FnSwp           :         ALUDataOut <= {BIn[15:0],BIn[31:16]};
                FnNop           :         ALUDataOut <= BIn;
                default         :    ALUDataOut <= AIn + BIn;
        endcase
end
 
 
endmodule

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[/] [embedded_risc/] [trunk/] [Verilog/] [ALU.V] - Blame information for rev 27

Line No.	Rev	Author	Line
1	26	hosseinami	`/****************************************************************************************`
2			`MODULE: Sub Level Arithmatic Logic Unit Block`
3
4			`FILE NAME: alu.v`
5			`VERSION: 1.0`
6			`DATE: September 28th, 2001`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY: California Unique Electrical Co.`
9			`CODE TYPE: Register Transfer Level`
10
11			`Instantiations:`
12
13			`DESCRIPTION:`
14			`Sub Level RTL Arithmatic Logic Unit block`
15
16			`Hossein Amidi`
17			`(C) September 2001`
18			`California Unique Electric`
19
20			`***************************************************************************************/`
21
22			`timescale 1ns / 1ps
23
24			`module ALU (// Input`
25			`ALUSrcA,`
26			`ALUSrcB,`
27			`OpCode,`
28			`CurrentState,`
29			`// Output`
30			`ALUDataOut`
31			`);`
32
33			`// Parameter`
34			`parameter DataWidth = 32;`
35			`parameter OpcodeSize = 8;`
36			`parameter StateSize = 2;`
37			`parameter FunctionSize = 8;`
38
39			`// Instructions options`
40			`parameter LDA = 8'h0;`
41			`parameter STO = 8'h1;`
42			`parameter ADD = 8'h2;`
43			`parameter SUB = 8'h3;`
44			`parameter JMP = 8'h4;`
45			`parameter JGE = 8'h5;`
46			`parameter JNE = 8'h6;`
47			`parameter STP = 8'h7;`
48			`parameter SHR = 8'h8;`
49			`parameter SHL = 8'h9;`
50			`parameter AND = 8'ha;`
51			`parameter OR = 8'hb;`
52			`parameter XOR = 8'hc;`
53			`parameter COM = 8'hd;`
54			`parameter SWP = 8'he;`
55			`parameter NOP = 8'hf;`
56
57			`// Instruction for Memory Map devices`
58			`parameter MAP = 9'h64;`
59
60			`// Current State options`
61			`parameter Init = 2'b00;`
62			`parameter InstrFetch = 2'b01;`
63			`parameter InstrExec = 2'b10;`
64
65			`// Function Select options`
66			`parameter FnAdd = 8'b0000_0000;`
67			`parameter FnSub = 8'b0000_0001;`
68			`parameter FnPassB = 8'b0000_0010;`
69			`parameter FnIncB = 8'b0000_0011;`
70			`parameter FnShtR = 8'b0000_0100;`
71			`parameter FnShtL = 8'b0000_0101;`
72			`parameter FnAnd = 8'b0000_0110;`
73			`parameter FnOr = 8'b0000_0111;`
74			`parameter FnXor = 8'b0000_1000;`
75			`parameter FnCom = 8'b0000_1001;`
76			`parameter FnSwp = 8'b0000_1010;`
77			`parameter FnNop = 8'b0000_1011;`
78
79			`// Input`
80			`input [DataWidth - 1 : 0] ALUSrcA;`
81			`input [DataWidth - 1 : 0] ALUSrcB;`
82			`input [OpcodeSize - 1 : 0] OpCode;`
83			`input [StateSize - 1 : 0] CurrentState;`
84
85			`// Output`
86			`output [DataWidth - 1 : 0] ALUDataOut;`
87
88			`// Signal Assignments`
89			`reg [DataWidth - 1 : 0] ALUDataOut;`
90			`reg [FunctionSize - 1 : 0] FunctSel;`
91			`reg CIn;`
92
93			`wire [DataWidth - 1 : 0] AIn, BIn;`
94
95
96			`// Assignment`
97			`assign AIn = ALUSrcA;`
98			`assign BIn = ALUSrcB;`
99
100
101
102			`always @(OpCode or CurrentState)`
103			`begin`
104			`if (CurrentState == InstrFetch)`
105			`begin`
106			`if (OpCode != STP) // In the Fetch cycle increment PC`
107			`begin`
108			`FunctSel <= FnIncB;`
109			`CIn <= 1;`
110			`end`
111			`else`
112			`begin`
113			`FunctSel <= FnPassB;`
114			`CIn <= 0;`
115			`end`
116			`end`
117			`else`
118			`if(CurrentState == InstrExec)`
119			`begin`
120			`case (OpCode)`
121			`LDA :`
122			`begin`
123			`FunctSel <= FnPassB;`
124			`CIn <= 0;`
125			`end`
126
127			`STO :`
128			`begin`
129			`FunctSel <= FnAdd;`
130			`CIn <= 0;`
131			`end`
132
133			`ADD :`
134			`begin`
135			`FunctSel <= FnAdd;`
136			`CIn <= 0;`
137			`end`
138
139			`SUB :`
140			`begin`
141			`FunctSel <= FnSub;`
142			`CIn <= 0;`
143			`end`
144
145			`JMP :`
146			`begin`
147			`FunctSel <= FnPassB;`
148			`CIn <= 0;`
149			`end`
150
151			`JGE :`
152			`begin`
153			`FunctSel <= FnPassB;`
154			`CIn <= 0;`
155			`end`
156
157			`JNE :`
158			`begin`
159			`FunctSel <= FnPassB;`
160			`CIn <= 0;`
161			`end`
162
163			`STP :`
164			`begin`
165			`FunctSel <= FnPassB;`
166			`CIn <= 0;`
167			`end`
168
169			`SHR :`
170			`begin`
171			`FunctSel <= FnShtR;`
172			`CIn <= 0;`
173			`end`
174
175			`SHL :`
176			`begin`
177			`FunctSel <= FnShtL;`
178			`CIn <= 0;`
179			`end`
180
181			`AND :`
182			`begin`
183			`FunctSel <= FnAnd;`
184			`CIn <= 0;`
185			`end`
186
187			`OR :`
188			`begin`
189			`FunctSel <= FnOr;`
190			`CIn <= 0;`
191			`end`
192
193			`XOR :`
194			`begin`
195			`FunctSel <= FnXor;`
196			`CIn <= 0;`
197			`end`
198
199			`COM :`
200			`begin`
201			`FunctSel <= FnCom;`
202			`CIn <= 0;`
203			`end`
204
205			`SWP :`
206			`begin`
207			`FunctSel <= FnSwp;`
208			`CIn <= 0;`
209			`end`
210
211			`NOP :`
212			`begin`
213			`FunctSel <= FnNop;`
214			`CIn <= 0;`
215			`end`
216
217			`default : ;`
218			`endcase`
219			`end`
220			`end`
221
222
223			`always @(AIn or BIn or CIn or FunctSel)`
224			`begin`
225			`case (FunctSel)`
226			`FnAdd : ALUDataOut <= AIn + BIn;`
227			`FnSub : ALUDataOut <= AIn - BIn;`
228			`FnPassB : ALUDataOut <= BIn;`
229			`FnIncB : ALUDataOut <= BIn + CIn;`
230			`FnShtR : ALUDataOut <= AIn >> 1;`
231			`FnShtL : ALUDataOut <= AIn << 1;`
232			`FnAnd : ALUDataOut <= AIn & BIn;`
233			`FnOr : ALUDataOut <= AIn \| BIn;`
234			`FnXor : ALUDataOut <= AIn ^ BIn;`
235			`FnCom : ALUDataOut <= ~BIn;`
236			`FnSwp : ALUDataOut <= {BIn[15:0],BIn[31:16]};`
237			`FnNop : ALUDataOut <= BIn;`
238			`default : ALUDataOut <= AIn + BIn;`
239			`endcase`
240			`end`
241
242
243			`endmodule`