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/****************************************************************************************
 MODULE:                Sub Level Controller Block
 
 FILE NAME:     control.v
 VERSION:       1.0
 DATE:          September 28th, 2001
 AUTHOR:                Hossein Amidi
 COMPANY:       California Unique Electrical Co.
 CODE TYPE:     Register Transfer Level
 
 Instantiations:
 
 DESCRIPTION:
 Sub Level RTL Controller block
 
 Hossein Amidi
 (C) September 2001
 California Unique Electric
 
***************************************************************************************/
 
`timescale 1ns / 1ps
 
module CNTRL (  // Input
                                                        clock,
                                                        reset,
                                                        OpCode,
                                                        ACCNeg,
                                                        ACCZero,
                                                        Grant,
                                                        // Ouptut
                                                        NextState,
                                                        PCInEn,
                                                        IRInEn,
                                                        ACCInEn,
                                                        ACCOutEn,
                                                        MemReq,
                                                        RdWrBar,
                                                        AddressSel,
                                                        ALUSrcBSel
                                                        );
 
 
// Parameter
parameter OpcodeSize = 8;
parameter StateSize = 2;
parameter Low   = 1'b0;
parameter High  = 1'b1;
parameter SelInstrAddr   = 1'b0;
parameter SelOperandAddr = 1'b1;
parameter SelAddress    = 1'b0;
parameter SelData       = 1'b1;
 
// Instructions options
parameter  LDA = 8'h0;
parameter  STO = 8'h1;
parameter  ADD = 8'h2;
parameter  SUB = 8'h3;
parameter  JMP = 8'h4;
parameter  JGE = 8'h5;
parameter  JNE = 8'h6;
parameter  STP = 8'h7;
parameter  SHR = 8'h8;
parameter  SHL = 8'h9;
parameter  AND = 8'ha;
parameter  OR  = 8'hb;
parameter  XOR = 8'hc;
parameter  COM = 8'hd;
parameter  SWP = 8'he;
parameter  NOP = 8'hf;
 
// Instruction for Memory Map devices
parameter  MAP = 8'h64;
 
 
// Current State options
parameter Init                  = 2'b00;
parameter InstrFetch = 2'b01;
parameter InstrExec  = 2'b10;
parameter InstrStop  = 2'b11;
 
 
// Input
input clock;
input reset;
input [OpcodeSize - 1 : 0] OpCode;
input ACCNeg;
input ACCZero;
input Grant;
 
// Output
output [StateSize - 1 : 0] NextState;
output PCInEn;
output IRInEn;
output ACCInEn;
output ACCOutEn;
output MemReq;
output RdWrBar;
output AddressSel;
output ALUSrcBSel;
 
// Signal Declerations
reg PCInEn;
reg IRInEn;
reg ACCInEn;
reg ACCOutEn;
reg MemReq;
reg RdWrBar;
reg AddressSel;
reg ALUSrcBSel;
wire [StateSize - 1 : 0] NextState;
 
 
reg [1:0]state;
// Assignments
assign NextState = state;
 
// Finite State Machine's Sequential Section
always @(posedge reset or negedge clock)
begin
        if(reset == 1'b1)
        begin
                state <= Init;
        end
        else
        begin // Grant = 1 -bit, opcode = 8-bit, state = 2-bit
                casex ({Grant,OpCode,state})
                   11'b0_xxxxxxxx_00:  state <= Init;
                        11'b1_00000000_00:  state <= InstrFetch;
                        11'b1_00000000_01:  state <= InstrExec;
                        11'b1_00000001_01:  state <= InstrExec;
                        11'b1_00000010_01:  state <= InstrExec;
                        11'b1_00000011_01:  state <= InstrExec;
                        11'b1_00000100_01:  state <= InstrExec;
                        11'b1_00000101_01:  state <= InstrExec;
                        11'b1_00000110_01:  state <= InstrExec;
                        11'b1_00000111_01:  state <= InstrExec;
                        11'b1_00001000_01:  state <= InstrExec;
                        11'b1_00001001_01:  state <= InstrExec;
                        11'b1_00001010_01:  state <= InstrExec;
                        11'b1_00001011_01:  state <= InstrExec;
                        11'b1_00001100_01:  state <= InstrExec;
                        11'b1_00001101_01:  state <= InstrExec;
                        11'b1_00001110_01:  state <= InstrExec;
                        11'b1_00001111_01:  state <= InstrExec;
                        11'b1_00010000_01:  state <= InstrExec;
                        11'b1_00010001_01:  state <= InstrExec;
                        11'b1_00010010_01:  state <= InstrExec;
                        11'b1_00010011_01:  state <= InstrExec;
                        11'b1_00010100_01:  state <= InstrExec;
                        11'b1_00010101_01:  state <= InstrExec;
                        11'b1_00010110_01:  state <= InstrExec;
                        11'b1_00010111_01:  state <= InstrExec;
                        11'b1_00011000_01:  state <= InstrExec;
                        11'b1_00011001_01:  state <= InstrExec;
                        11'b1_00011010_01:  state <= InstrExec;
                        11'b1_00011011_01:  state <= InstrExec;
                        11'b1_00011100_01:  state <= InstrExec;
                        11'b1_00011101_01:  state <= InstrExec;
                        11'b1_00011110_01:  state <= InstrExec;
                        11'b1_00011111_01:  state <= InstrExec;
                        11'b1_00100000_01:  state <= InstrExec;
                        11'b1_00100001_01:  state <= InstrExec;
                        11'b1_00100010_01:  state <= InstrExec;
                        11'b1_00100011_01:  state <= InstrExec;
                        11'b1_00100100_01:  state <= InstrExec;
                        11'b1_00100101_01:  state <= InstrExec;
                        11'b1_00100110_01:  state <= InstrExec;
                        11'b1_00100111_01:  state <= InstrExec;
                        11'b1_00101000_01:  state <= InstrExec;
                        11'b1_00101001_01:  state <= InstrExec;
                        11'b1_00101010_01:  state <= InstrExec;
                        11'b1_00101011_01:  state <= InstrExec;
                        11'b1_00101100_01:  state <= InstrExec;
                        11'b1_00101101_01:  state <= InstrExec;
                        11'b1_00101110_01:  state <= InstrExec;
                        11'b1_00101111_01:  state <= InstrExec;
                        11'b1_00110000_01:  state <= InstrExec;
                        11'b1_00110001_01:  state <= InstrExec;
                        11'b1_00110010_01:  state <= InstrExec;
                        11'b1_00110011_01:  state <= InstrExec;
                        11'b1_00110100_01:  state <= InstrExec;
                        11'b1_00110101_01:  state <= InstrExec;
                        11'b1_00110110_01:  state <= InstrExec;
                        11'b1_00110111_01:  state <= InstrExec;
                        11'b1_00111000_01:  state <= InstrExec;
                        11'b1_00111001_01:  state <= InstrExec;
                        11'b1_00111010_01:  state <= InstrExec;
                        11'b1_00111011_01:  state <= InstrExec;
                        11'b1_00111100_01:  state <= InstrExec;
                        11'b1_00111101_01:  state <= InstrExec;
                        11'b1_00111110_01:  state <= InstrExec;
                        11'b1_00111111_01:  state <= InstrExec;
                        11'b1_01000000_01:  state <= InstrExec;
                        11'b1_01000001_01:  state <= InstrExec;
                        11'b1_01000010_01:  state <= InstrExec;
                        11'b1_01000011_01:  state <= InstrExec;
                        11'b1_01000100_01:  state <= InstrExec;
                        11'b1_01000101_01:  state <= InstrExec;
                        11'b1_01000110_01:  state <= InstrExec;
                        11'b1_01000111_01:  state <= InstrExec;
                        11'b1_01001000_01:  state <= InstrExec;
                        11'b1_01001001_01:  state <= InstrExec;
                        11'b1_01001010_01:  state <= InstrExec;
                        11'b1_01001011_01:  state <= InstrExec;
                        11'b1_01001100_01:  state <= InstrExec;
                        11'b1_01001101_01:  state <= InstrExec;
                        11'b1_01001110_01:  state <= InstrExec;
                        11'b1_01001111_01:  state <= InstrExec;
                        11'b1_01010000_01:  state <= InstrExec;
                        11'b1_01010001_01:  state <= InstrExec;
                        11'b1_01010010_01:  state <= InstrExec;
                        11'b1_01010011_01:  state <= InstrExec;
                        11'b1_01010100_01:  state <= InstrExec;
                        11'b1_01010101_01:  state <= InstrExec;
                        11'b1_01010110_01:  state <= InstrExec;
                        11'b1_01010111_01:  state <= InstrExec;
                        11'b1_01011000_01:  state <= InstrExec;
                        11'b1_01011001_01:  state <= InstrExec;
                        11'b1_01011010_01:  state <= InstrExec;
                        11'b1_01011011_01:  state <= InstrExec;
                        11'b1_01011100_01:  state <= InstrExec;
                        11'b1_01011101_01:  state <= InstrExec;
                        11'b1_01011110_01:  state <= InstrExec;
                        11'b1_01011111_01:  state <= InstrExec;
                        11'b1_01100000_01:  state <= InstrExec;
                        11'b1_01100001_01:  state <= InstrExec;
                        11'b1_01100010_01:  state <= InstrExec;
                        11'b1_01100011_01:  state <= InstrExec;
                        11'b1_01100100_01:  state <= InstrExec;
                        11'b1_01100101_01:  state <= InstrExec;
                        11'b1_01100110_01:  state <= InstrExec;
                        11'b1_01100111_01:  state <= InstrExec;
                        11'b1_01101000_01:  state <= InstrExec;
                        11'b1_01101001_01:  state <= InstrExec;
                        11'b1_01101010_01:  state <= InstrExec;
                        11'b1_01101011_01:  state <= InstrExec;
                        11'b1_01101100_01:  state <= InstrExec;
                        11'b1_01101101_01:  state <= InstrExec;
                        11'b1_01101110_01:  state <= InstrExec;
                        11'b1_01101111_01:  state <= InstrExec;
                        11'b1_01110000_01:  state <= InstrExec;
                        11'b1_01110001_01:  state <= InstrExec;
                        11'b1_01110010_01:  state <= InstrExec;
                        11'b1_01110011_01:  state <= InstrExec;
                        11'b1_01110100_01:  state <= InstrExec;
                        11'b1_01110101_01:  state <= InstrExec;
                        11'b1_01110110_01:  state <= InstrExec;
                        11'b1_01110111_01:  state <= InstrExec;
                        11'b1_01111000_01:  state <= InstrExec;
                        11'b1_01111001_01:  state <= InstrExec;
                        11'b1_01111010_01:  state <= InstrExec;
                        11'b1_01111011_01:  state <= InstrExec;
                        11'b1_01111100_01:  state <= InstrExec;
                        11'b1_01111101_01:  state <= InstrExec;
                        11'b1_01111110_01:  state <= InstrExec;
                        11'b1_01111111_01:  state <= InstrExec;
                        11'b1_10000000_01:  state <= InstrExec;
                        11'b1_10000001_01:  state <= InstrExec;
                        11'b1_10000010_01:  state <= InstrExec;
                        11'b1_10000011_01:  state <= InstrExec;
                        11'b1_10000100_01:  state <= InstrExec;
                        11'b1_10000101_01:  state <= InstrExec;
                        11'b1_10000110_01:  state <= InstrExec;
                        11'b1_10000111_01:  state <= InstrExec;
                        11'b1_10001000_01:  state <= InstrExec;
                        11'b1_10001001_01:  state <= InstrExec;
                        11'b1_10001010_01:  state <= InstrExec;
                        11'b1_10001011_01:  state <= InstrExec;
                        11'b1_10001100_01:  state <= InstrExec;
                        11'b1_10001101_01:  state <= InstrExec;
                        11'b1_10001110_01:  state <= InstrExec;
                        11'b1_10001111_01:  state <= InstrExec;
                        11'b1_10010000_01:  state <= InstrExec;
                        11'b1_10010001_01:  state <= InstrExec;
                        11'b1_10010010_01:  state <= InstrExec;
                        11'b1_10010011_01:  state <= InstrExec;
                        11'b1_10010100_01:  state <= InstrExec;
                        11'b1_10010101_01:  state <= InstrExec;
                        11'b1_10010110_01:  state <= InstrExec;
                        11'b1_10010111_01:  state <= InstrExec;
                        11'b1_10011000_01:  state <= InstrExec;
                        11'b1_10011001_01:  state <= InstrExec;
                        11'b1_10011010_01:  state <= InstrExec;
                        11'b1_10011011_01:  state <= InstrExec;
                        11'b1_10011100_01:  state <= InstrExec;
                        11'b1_10011101_01:  state <= InstrExec;
                        11'b1_10011110_01:  state <= InstrExec;
                        11'b1_10011111_01:  state <= InstrExec;
                        11'b1_10100000_01:  state <= InstrExec;
                        11'b1_10100001_01:  state <= InstrExec;
                        11'b1_10100010_01:  state <= InstrExec;
                        11'b1_10100011_01:  state <= InstrExec;
                        11'b1_10100100_01:  state <= InstrExec;
                        11'b1_10100101_01:  state <= InstrExec;
                        11'b1_10100110_01:  state <= InstrExec;
                        11'b1_10100111_01:  state <= InstrExec;
                        11'b1_10101000_01:  state <= InstrExec;
                        11'b1_10101001_01:  state <= InstrExec;
                        11'b1_10101010_01:  state <= InstrExec;
                        11'b1_10101011_01:  state <= InstrExec;
                        11'b1_10101100_01:  state <= InstrExec;
                        11'b1_10101101_01:  state <= InstrExec;
                        11'b1_10101110_01:  state <= InstrExec;
                        11'b1_10101111_01:  state <= InstrExec;
                        11'b1_10110000_01:  state <= InstrExec;
                        11'b1_10110001_01:  state <= InstrExec;
                        11'b1_10110010_01:  state <= InstrExec;
                        11'b1_10110011_01:  state <= InstrExec;
                        11'b1_10110100_01:  state <= InstrExec;
                        11'b1_10110101_01:  state <= InstrExec;
                        11'b1_10110110_01:  state <= InstrExec;
                        11'b1_10110111_01:  state <= InstrExec;
                        11'b1_10111000_01:  state <= InstrExec;
                        11'b1_10111001_01:  state <= InstrExec;
                        11'b1_10111010_01:  state <= InstrExec;
                        11'b1_10111011_01:  state <= InstrExec;
                        11'b1_10111100_01:  state <= InstrExec;
                        11'b1_10111101_01:  state <= InstrExec;
                        11'b1_10111110_01:  state <= InstrExec;
                        11'b1_10111111_01:  state <= InstrExec;
                        11'b1_11000000_01:  state <= InstrExec;
                        11'b1_11000001_01:  state <= InstrExec;
                        11'b1_11000010_01:  state <= InstrExec;
                        11'b1_11000011_01:  state <= InstrExec;
                        11'b1_11000100_01:  state <= InstrExec;
                        11'b1_11000101_01:  state <= InstrExec;
                        11'b1_11000110_01:  state <= InstrExec;
                        11'b1_11000111_01:  state <= InstrExec;
                        11'b1_11001000_01:  state <= InstrExec;
                        11'b1_11001001_01:  state <= InstrExec;
                        11'b1_11001010_01:  state <= InstrExec;
                        11'b1_11001011_01:  state <= InstrExec;
                        11'b1_11001100_01:  state <= InstrExec;
                        11'b1_11001101_01:  state <= InstrExec;
                        11'b1_11001110_01:  state <= InstrExec;
                        11'b1_11001111_01:  state <= InstrExec;
                        11'b1_11010000_01:  state <= InstrExec;
                        11'b1_11010001_01:  state <= InstrExec;
                        11'b1_11010010_01:  state <= InstrExec;
                        11'b1_11010011_01:  state <= InstrExec;
                        11'b1_11010100_01:  state <= InstrExec;
                        11'b1_11010101_01:  state <= InstrExec;
                        11'b1_11010110_01:  state <= InstrExec;
                        11'b1_11010111_01:  state <= InstrExec;
                        11'b1_11011000_01:  state <= InstrExec;
                        11'b1_11011001_01:  state <= InstrExec;
                        11'b1_11011010_01:  state <= InstrExec;
                        11'b1_11011011_01:  state <= InstrExec;
                        11'b1_11011100_01:  state <= InstrExec;
                        11'b1_11011101_01:  state <= InstrExec;
                        11'b1_11011110_01:  state <= InstrExec;
                        11'b1_11011111_01:  state <= InstrExec;
                        11'b1_11100000_01:  state <= InstrExec;
                        11'b1_11100001_01:  state <= InstrExec;
                        11'b1_11100010_01:  state <= InstrExec;
                        11'b1_11100011_01:  state <= InstrExec;
                        11'b1_11100100_01:  state <= InstrExec;
                        11'b1_11100101_01:  state <= InstrExec;
                        11'b1_11100110_01:  state <= InstrExec;
                        11'b1_11100111_01:  state <= InstrExec;
                        11'b1_11101000_01:  state <= InstrExec;
                        11'b1_11101001_01:  state <= InstrExec;
                        11'b1_11101010_01:  state <= InstrExec;
                        11'b1_11101011_01:  state <= InstrExec;
                        11'b1_11101100_01:  state <= InstrExec;
                        11'b1_11101101_01:  state <= InstrExec;
                        11'b1_11101110_01:  state <= InstrExec;
                        11'b1_11101111_01:  state <= InstrExec;
                        11'b1_11110000_01:  state <= InstrExec;
                        11'b1_11110001_01:  state <= InstrExec;
                        11'b1_11110010_01:  state <= InstrExec;
                        11'b1_11110011_01:  state <= InstrExec;
                        11'b1_11110100_01:  state <= InstrExec;
                        11'b1_11110101_01:  state <= InstrExec;
                        11'b1_11110110_01:  state <= InstrExec;
                        11'b1_11110111_01:  state <= InstrExec;
                        11'b1_11111000_01:  state <= InstrExec;
                        11'b1_11111001_01:  state <= InstrExec;
                        11'b1_11111010_01:  state <= InstrExec;
                        11'b1_11111011_01:  state <= InstrExec;
                        11'b1_11111100_01:  state <= InstrExec;
                        11'b1_11111101_01:  state <= InstrExec;
                        11'b1_11111110_01:  state <= InstrExec;
                        11'b1_11111111_01:  state <= InstrExec;
                        11'b1_00000111_10:  state <= InstrStop;
                        11'b1_xxxxxxxx_10:  state <= InstrFetch;
                        11'b1_00000111_11:  state <= Init;
                        default:                             state <= Init;
                endcase
        end
end
 
 
// Finite State Machine's Combinatorial Section
always @(reset or state or ACCNeg or ACCZero or OpCode)
begin
        if (reset == 1'b1)
        begin
                PCInEn          <= Low;
                IRInEn          <= Low;
                ACCInEn                 <= Low;
                ACCOutEn        <= Low;
                MemReq          <= Low;
                RdWrBar                 <= Low;
                AddressSel      <= Low;
                ALUSrcBSel      <= Low;
        end
        else
        if (state == InstrFetch)
        begin
           PCInEn               <= High;
                IRInEn          <= High;
                ACCInEn                 <= Low;
                ACCOutEn        <= Low;
           MemReq               <= High;
                RdWrBar                 <= High;
                AddressSel      <= SelInstrAddr;
           ALUSrcBSel   <= SelAddress;
        end
        else
        if (state == InstrExec)
        begin
    case (OpCode)
 
         LDA:
                begin
        PCInEn          <= Low;
                  IRInEn                <= Low;
                  ACCInEn               <= High;
                  ACCOutEn              <= Low;
        MemReq          <= High;
                  RdWrBar               <= High;
                  AddressSel    <= SelOperandAddr;
        ALUSrcBSel      <= SelData;
      end
    STO:
        begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= High;
        MemReq <= High;
                  RdWrBar <= Low;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    ADD:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
       end
    SUB:
        begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
      end
    JMP:
        begin
        PCInEn <= High;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    JGE:
        begin
        PCInEn <= ~ACCNeg;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    JNE:
        begin
        PCInEn <= ~ACCZero;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    STP:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= High;
                  AddressSel <= SelAddress;
        ALUSrcBSel <= SelAddress;
           end
    SHR:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= Low;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
           end
    SHL:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= Low;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
        end
    AND:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
        end
    OR:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
        end
    XOR:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
        end
    COM:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
        end
    SWP:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= High;
                  ACCOutEn <= Low;
        MemReq <= High;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelData;
        end
    NOP:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
        end
    default:
                begin
        PCInEn <= Low;
                  IRInEn <= Low;
                  ACCInEn <= Low;
                  ACCOutEn <= Low;
        MemReq <= Low;
                  RdWrBar <= High;
                  AddressSel <= SelOperandAddr;
        ALUSrcBSel <= SelAddress;
      end
    endcase
         end
        else
        if (state == InstrStop)
   begin
       PCInEn <= Low;
                 IRInEn <= Low;
                 ACCInEn <= Low;
                 ACCOutEn <= Low;
       MemReq <= Low;
                 RdWrBar <= High;
                 AddressSel <= SelAddress;
       ALUSrcBSel <= SelAddress;
   end
end
endmodule

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Line No.	Rev	Author	Line
1	26	hosseinami	`/****************************************************************************************`
2			`MODULE: Sub Level Controller Block`
3
4			`FILE NAME: control.v`
5			`VERSION: 1.0`
6			`DATE: September 28th, 2001`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY: California Unique Electrical Co.`
9			`CODE TYPE: Register Transfer Level`
10
11			`Instantiations:`
12
13			`DESCRIPTION:`
14			`Sub Level RTL Controller block`
15
16			`Hossein Amidi`
17			`(C) September 2001`
18			`California Unique Electric`
19
20			`***************************************************************************************/`
21
22			`timescale 1ns / 1ps
23
24			`module CNTRL ( // Input`
25			`clock,`
26			`reset,`
27			`OpCode,`
28			`ACCNeg,`
29			`ACCZero,`
30			`Grant,`
31			`// Ouptut`
32			`NextState,`
33			`PCInEn,`
34			`IRInEn,`
35			`ACCInEn,`
36			`ACCOutEn,`
37			`MemReq,`
38			`RdWrBar,`
39			`AddressSel,`
40			`ALUSrcBSel`
41			`);`
42
43
44			`// Parameter`
45			`parameter OpcodeSize = 8;`
46			`parameter StateSize = 2;`
47			`parameter Low = 1'b0;`
48			`parameter High = 1'b1;`
49			`parameter SelInstrAddr = 1'b0;`
50			`parameter SelOperandAddr = 1'b1;`
51			`parameter SelAddress = 1'b0;`
52			`parameter SelData = 1'b1;`
53
54			`// Instructions options`
55			`parameter LDA = 8'h0;`
56			`parameter STO = 8'h1;`
57			`parameter ADD = 8'h2;`
58			`parameter SUB = 8'h3;`
59			`parameter JMP = 8'h4;`
60			`parameter JGE = 8'h5;`
61			`parameter JNE = 8'h6;`
62			`parameter STP = 8'h7;`
63			`parameter SHR = 8'h8;`
64			`parameter SHL = 8'h9;`
65			`parameter AND = 8'ha;`
66			`parameter OR = 8'hb;`
67			`parameter XOR = 8'hc;`
68			`parameter COM = 8'hd;`
69			`parameter SWP = 8'he;`
70			`parameter NOP = 8'hf;`
71
72			`// Instruction for Memory Map devices`
73			`parameter MAP = 8'h64;`
74
75
76			`// Current State options`
77			`parameter Init = 2'b00;`
78			`parameter InstrFetch = 2'b01;`
79			`parameter InstrExec = 2'b10;`
80			`parameter InstrStop = 2'b11;`
81
82
83			`// Input`
84			`input clock;`
85			`input reset;`
86			`input [OpcodeSize - 1 : 0] OpCode;`
87			`input ACCNeg;`
88			`input ACCZero;`
89			`input Grant;`
90
91			`// Output`
92			`output [StateSize - 1 : 0] NextState;`
93			`output PCInEn;`
94			`output IRInEn;`
95			`output ACCInEn;`
96			`output ACCOutEn;`
97			`output MemReq;`
98			`output RdWrBar;`
99			`output AddressSel;`
100			`output ALUSrcBSel;`
101
102			`// Signal Declerations`
103			`reg PCInEn;`
104			`reg IRInEn;`
105			`reg ACCInEn;`
106			`reg ACCOutEn;`
107			`reg MemReq;`
108			`reg RdWrBar;`
109			`reg AddressSel;`
110			`reg ALUSrcBSel;`
111			`wire [StateSize - 1 : 0] NextState;`
112
113
114			`reg [1:0]state;`
115			`// Assignments`
116			`assign NextState = state;`
117
118			`// Finite State Machine's Sequential Section`
119			`always @(posedge reset or negedge clock)`
120			`begin`
121			`if(reset == 1'b1)`
122			`begin`
123			`state <= Init;`
124			`end`
125			`else`
126			`begin // Grant = 1 -bit, opcode = 8-bit, state = 2-bit`
127			`casex ({Grant,OpCode,state})`
128			`11'b0_xxxxxxxx_00: state <= Init;`
129			`11'b1_00000000_00: state <= InstrFetch;`
130			`11'b1_00000000_01: state <= InstrExec;`
131			`11'b1_00000001_01: state <= InstrExec;`
132			`11'b1_00000010_01: state <= InstrExec;`
133			`11'b1_00000011_01: state <= InstrExec;`
134			`11'b1_00000100_01: state <= InstrExec;`
135			`11'b1_00000101_01: state <= InstrExec;`
136			`11'b1_00000110_01: state <= InstrExec;`
137			`11'b1_00000111_01: state <= InstrExec;`
138			`11'b1_00001000_01: state <= InstrExec;`
139			`11'b1_00001001_01: state <= InstrExec;`
140			`11'b1_00001010_01: state <= InstrExec;`
141			`11'b1_00001011_01: state <= InstrExec;`
142			`11'b1_00001100_01: state <= InstrExec;`
143			`11'b1_00001101_01: state <= InstrExec;`
144			`11'b1_00001110_01: state <= InstrExec;`
145			`11'b1_00001111_01: state <= InstrExec;`
146			`11'b1_00010000_01: state <= InstrExec;`
147			`11'b1_00010001_01: state <= InstrExec;`
148			`11'b1_00010010_01: state <= InstrExec;`
149			`11'b1_00010011_01: state <= InstrExec;`
150			`11'b1_00010100_01: state <= InstrExec;`
151			`11'b1_00010101_01: state <= InstrExec;`
152			`11'b1_00010110_01: state <= InstrExec;`
153			`11'b1_00010111_01: state <= InstrExec;`
154			`11'b1_00011000_01: state <= InstrExec;`
155			`11'b1_00011001_01: state <= InstrExec;`
156			`11'b1_00011010_01: state <= InstrExec;`
157			`11'b1_00011011_01: state <= InstrExec;`
158			`11'b1_00011100_01: state <= InstrExec;`
159			`11'b1_00011101_01: state <= InstrExec;`
160			`11'b1_00011110_01: state <= InstrExec;`
161			`11'b1_00011111_01: state <= InstrExec;`
162			`11'b1_00100000_01: state <= InstrExec;`
163			`11'b1_00100001_01: state <= InstrExec;`
164			`11'b1_00100010_01: state <= InstrExec;`
165			`11'b1_00100011_01: state <= InstrExec;`
166			`11'b1_00100100_01: state <= InstrExec;`
167			`11'b1_00100101_01: state <= InstrExec;`
168			`11'b1_00100110_01: state <= InstrExec;`
169			`11'b1_00100111_01: state <= InstrExec;`
170			`11'b1_00101000_01: state <= InstrExec;`
171			`11'b1_00101001_01: state <= InstrExec;`
172			`11'b1_00101010_01: state <= InstrExec;`
173			`11'b1_00101011_01: state <= InstrExec;`
174			`11'b1_00101100_01: state <= InstrExec;`
175			`11'b1_00101101_01: state <= InstrExec;`
176			`11'b1_00101110_01: state <= InstrExec;`
177			`11'b1_00101111_01: state <= InstrExec;`
178			`11'b1_00110000_01: state <= InstrExec;`
179			`11'b1_00110001_01: state <= InstrExec;`
180			`11'b1_00110010_01: state <= InstrExec;`
181			`11'b1_00110011_01: state <= InstrExec;`
182			`11'b1_00110100_01: state <= InstrExec;`
183			`11'b1_00110101_01: state <= InstrExec;`
184			`11'b1_00110110_01: state <= InstrExec;`
185			`11'b1_00110111_01: state <= InstrExec;`
186			`11'b1_00111000_01: state <= InstrExec;`
187			`11'b1_00111001_01: state <= InstrExec;`
188			`11'b1_00111010_01: state <= InstrExec;`
189			`11'b1_00111011_01: state <= InstrExec;`
190			`11'b1_00111100_01: state <= InstrExec;`
191			`11'b1_00111101_01: state <= InstrExec;`
192			`11'b1_00111110_01: state <= InstrExec;`
193			`11'b1_00111111_01: state <= InstrExec;`
194			`11'b1_01000000_01: state <= InstrExec;`
195			`11'b1_01000001_01: state <= InstrExec;`
196			`11'b1_01000010_01: state <= InstrExec;`
197			`11'b1_01000011_01: state <= InstrExec;`
198			`11'b1_01000100_01: state <= InstrExec;`
199			`11'b1_01000101_01: state <= InstrExec;`
200			`11'b1_01000110_01: state <= InstrExec;`
201			`11'b1_01000111_01: state <= InstrExec;`
202			`11'b1_01001000_01: state <= InstrExec;`
203			`11'b1_01001001_01: state <= InstrExec;`
204			`11'b1_01001010_01: state <= InstrExec;`
205			`11'b1_01001011_01: state <= InstrExec;`
206			`11'b1_01001100_01: state <= InstrExec;`
207			`11'b1_01001101_01: state <= InstrExec;`
208			`11'b1_01001110_01: state <= InstrExec;`
209			`11'b1_01001111_01: state <= InstrExec;`
210			`11'b1_01010000_01: state <= InstrExec;`
211			`11'b1_01010001_01: state <= InstrExec;`
212			`11'b1_01010010_01: state <= InstrExec;`
213			`11'b1_01010011_01: state <= InstrExec;`
214			`11'b1_01010100_01: state <= InstrExec;`
215			`11'b1_01010101_01: state <= InstrExec;`
216			`11'b1_01010110_01: state <= InstrExec;`
217			`11'b1_01010111_01: state <= InstrExec;`
218			`11'b1_01011000_01: state <= InstrExec;`
219			`11'b1_01011001_01: state <= InstrExec;`
220			`11'b1_01011010_01: state <= InstrExec;`
221			`11'b1_01011011_01: state <= InstrExec;`
222			`11'b1_01011100_01: state <= InstrExec;`
223			`11'b1_01011101_01: state <= InstrExec;`
224			`11'b1_01011110_01: state <= InstrExec;`
225			`11'b1_01011111_01: state <= InstrExec;`
226			`11'b1_01100000_01: state <= InstrExec;`
227			`11'b1_01100001_01: state <= InstrExec;`
228			`11'b1_01100010_01: state <= InstrExec;`
229			`11'b1_01100011_01: state <= InstrExec;`
230			`11'b1_01100100_01: state <= InstrExec;`
231			`11'b1_01100101_01: state <= InstrExec;`
232			`11'b1_01100110_01: state <= InstrExec;`
233			`11'b1_01100111_01: state <= InstrExec;`
234			`11'b1_01101000_01: state <= InstrExec;`
235			`11'b1_01101001_01: state <= InstrExec;`
236			`11'b1_01101010_01: state <= InstrExec;`
237			`11'b1_01101011_01: state <= InstrExec;`
238			`11'b1_01101100_01: state <= InstrExec;`
239			`11'b1_01101101_01: state <= InstrExec;`
240			`11'b1_01101110_01: state <= InstrExec;`
241			`11'b1_01101111_01: state <= InstrExec;`
242			`11'b1_01110000_01: state <= InstrExec;`
243			`11'b1_01110001_01: state <= InstrExec;`
244			`11'b1_01110010_01: state <= InstrExec;`
245			`11'b1_01110011_01: state <= InstrExec;`
246			`11'b1_01110100_01: state <= InstrExec;`
247			`11'b1_01110101_01: state <= InstrExec;`
248			`11'b1_01110110_01: state <= InstrExec;`
249			`11'b1_01110111_01: state <= InstrExec;`
250			`11'b1_01111000_01: state <= InstrExec;`
251			`11'b1_01111001_01: state <= InstrExec;`
252			`11'b1_01111010_01: state <= InstrExec;`
253			`11'b1_01111011_01: state <= InstrExec;`
254			`11'b1_01111100_01: state <= InstrExec;`
255			`11'b1_01111101_01: state <= InstrExec;`
256			`11'b1_01111110_01: state <= InstrExec;`
257			`11'b1_01111111_01: state <= InstrExec;`
258			`11'b1_10000000_01: state <= InstrExec;`
259			`11'b1_10000001_01: state <= InstrExec;`
260			`11'b1_10000010_01: state <= InstrExec;`
261			`11'b1_10000011_01: state <= InstrExec;`
262			`11'b1_10000100_01: state <= InstrExec;`
263			`11'b1_10000101_01: state <= InstrExec;`
264			`11'b1_10000110_01: state <= InstrExec;`
265			`11'b1_10000111_01: state <= InstrExec;`
266			`11'b1_10001000_01: state <= InstrExec;`
267			`11'b1_10001001_01: state <= InstrExec;`
268			`11'b1_10001010_01: state <= InstrExec;`
269			`11'b1_10001011_01: state <= InstrExec;`
270			`11'b1_10001100_01: state <= InstrExec;`
271			`11'b1_10001101_01: state <= InstrExec;`
272			`11'b1_10001110_01: state <= InstrExec;`
273			`11'b1_10001111_01: state <= InstrExec;`
274			`11'b1_10010000_01: state <= InstrExec;`
275			`11'b1_10010001_01: state <= InstrExec;`
276			`11'b1_10010010_01: state <= InstrExec;`
277			`11'b1_10010011_01: state <= InstrExec;`
278			`11'b1_10010100_01: state <= InstrExec;`
279			`11'b1_10010101_01: state <= InstrExec;`
280			`11'b1_10010110_01: state <= InstrExec;`
281			`11'b1_10010111_01: state <= InstrExec;`
282			`11'b1_10011000_01: state <= InstrExec;`
283			`11'b1_10011001_01: state <= InstrExec;`
284			`11'b1_10011010_01: state <= InstrExec;`
285			`11'b1_10011011_01: state <= InstrExec;`
286			`11'b1_10011100_01: state <= InstrExec;`
287			`11'b1_10011101_01: state <= InstrExec;`
288			`11'b1_10011110_01: state <= InstrExec;`
289			`11'b1_10011111_01: state <= InstrExec;`
290			`11'b1_10100000_01: state <= InstrExec;`
291			`11'b1_10100001_01: state <= InstrExec;`
292			`11'b1_10100010_01: state <= InstrExec;`
293			`11'b1_10100011_01: state <= InstrExec;`
294			`11'b1_10100100_01: state <= InstrExec;`
295			`11'b1_10100101_01: state <= InstrExec;`
296			`11'b1_10100110_01: state <= InstrExec;`
297			`11'b1_10100111_01: state <= InstrExec;`
298			`11'b1_10101000_01: state <= InstrExec;`
299			`11'b1_10101001_01: state <= InstrExec;`
300			`11'b1_10101010_01: state <= InstrExec;`
301			`11'b1_10101011_01: state <= InstrExec;`
302			`11'b1_10101100_01: state <= InstrExec;`
303			`11'b1_10101101_01: state <= InstrExec;`
304			`11'b1_10101110_01: state <= InstrExec;`
305			`11'b1_10101111_01: state <= InstrExec;`
306			`11'b1_10110000_01: state <= InstrExec;`
307			`11'b1_10110001_01: state <= InstrExec;`
308			`11'b1_10110010_01: state <= InstrExec;`
309			`11'b1_10110011_01: state <= InstrExec;`
310			`11'b1_10110100_01: state <= InstrExec;`
311			`11'b1_10110101_01: state <= InstrExec;`
312			`11'b1_10110110_01: state <= InstrExec;`
313			`11'b1_10110111_01: state <= InstrExec;`
314			`11'b1_10111000_01: state <= InstrExec;`
315			`11'b1_10111001_01: state <= InstrExec;`
316			`11'b1_10111010_01: state <= InstrExec;`
317			`11'b1_10111011_01: state <= InstrExec;`
318			`11'b1_10111100_01: state <= InstrExec;`
319			`11'b1_10111101_01: state <= InstrExec;`
320			`11'b1_10111110_01: state <= InstrExec;`
321			`11'b1_10111111_01: state <= InstrExec;`
322			`11'b1_11000000_01: state <= InstrExec;`
323			`11'b1_11000001_01: state <= InstrExec;`
324			`11'b1_11000010_01: state <= InstrExec;`
325			`11'b1_11000011_01: state <= InstrExec;`
326			`11'b1_11000100_01: state <= InstrExec;`
327			`11'b1_11000101_01: state <= InstrExec;`
328			`11'b1_11000110_01: state <= InstrExec;`
329			`11'b1_11000111_01: state <= InstrExec;`
330			`11'b1_11001000_01: state <= InstrExec;`
331			`11'b1_11001001_01: state <= InstrExec;`
332			`11'b1_11001010_01: state <= InstrExec;`
333			`11'b1_11001011_01: state <= InstrExec;`
334			`11'b1_11001100_01: state <= InstrExec;`
335			`11'b1_11001101_01: state <= InstrExec;`
336			`11'b1_11001110_01: state <= InstrExec;`
337			`11'b1_11001111_01: state <= InstrExec;`
338			`11'b1_11010000_01: state <= InstrExec;`
339			`11'b1_11010001_01: state <= InstrExec;`
340			`11'b1_11010010_01: state <= InstrExec;`
341			`11'b1_11010011_01: state <= InstrExec;`
342			`11'b1_11010100_01: state <= InstrExec;`
343			`11'b1_11010101_01: state <= InstrExec;`
344			`11'b1_11010110_01: state <= InstrExec;`
345			`11'b1_11010111_01: state <= InstrExec;`
346			`11'b1_11011000_01: state <= InstrExec;`
347			`11'b1_11011001_01: state <= InstrExec;`
348			`11'b1_11011010_01: state <= InstrExec;`
349			`11'b1_11011011_01: state <= InstrExec;`
350			`11'b1_11011100_01: state <= InstrExec;`
351			`11'b1_11011101_01: state <= InstrExec;`
352			`11'b1_11011110_01: state <= InstrExec;`
353			`11'b1_11011111_01: state <= InstrExec;`
354			`11'b1_11100000_01: state <= InstrExec;`
355			`11'b1_11100001_01: state <= InstrExec;`
356			`11'b1_11100010_01: state <= InstrExec;`
357			`11'b1_11100011_01: state <= InstrExec;`
358			`11'b1_11100100_01: state <= InstrExec;`
359			`11'b1_11100101_01: state <= InstrExec;`
360			`11'b1_11100110_01: state <= InstrExec;`
361			`11'b1_11100111_01: state <= InstrExec;`
362			`11'b1_11101000_01: state <= InstrExec;`
363			`11'b1_11101001_01: state <= InstrExec;`
364			`11'b1_11101010_01: state <= InstrExec;`
365			`11'b1_11101011_01: state <= InstrExec;`
366			`11'b1_11101100_01: state <= InstrExec;`
367			`11'b1_11101101_01: state <= InstrExec;`
368			`11'b1_11101110_01: state <= InstrExec;`
369			`11'b1_11101111_01: state <= InstrExec;`
370			`11'b1_11110000_01: state <= InstrExec;`
371			`11'b1_11110001_01: state <= InstrExec;`
372			`11'b1_11110010_01: state <= InstrExec;`
373			`11'b1_11110011_01: state <= InstrExec;`
374			`11'b1_11110100_01: state <= InstrExec;`
375			`11'b1_11110101_01: state <= InstrExec;`
376			`11'b1_11110110_01: state <= InstrExec;`
377			`11'b1_11110111_01: state <= InstrExec;`
378			`11'b1_11111000_01: state <= InstrExec;`
379			`11'b1_11111001_01: state <= InstrExec;`
380			`11'b1_11111010_01: state <= InstrExec;`
381			`11'b1_11111011_01: state <= InstrExec;`
382			`11'b1_11111100_01: state <= InstrExec;`
383			`11'b1_11111101_01: state <= InstrExec;`
384			`11'b1_11111110_01: state <= InstrExec;`
385			`11'b1_11111111_01: state <= InstrExec;`
386			`11'b1_00000111_10: state <= InstrStop;`
387			`11'b1_xxxxxxxx_10: state <= InstrFetch;`
388			`11'b1_00000111_11: state <= Init;`
389			`default: state <= Init;`
390			`endcase`
391			`end`
392			`end`
393
394
395			`// Finite State Machine's Combinatorial Section`
396			`always @(reset or state or ACCNeg or ACCZero or OpCode)`
397			`begin`
398			`if (reset == 1'b1)`
399			`begin`
400			`PCInEn <= Low;`
401			`IRInEn <= Low;`
402			`ACCInEn <= Low;`
403			`ACCOutEn <= Low;`
404			`MemReq <= Low;`
405			`RdWrBar <= Low;`
406			`AddressSel <= Low;`
407			`ALUSrcBSel <= Low;`
408			`end`
409			`else`
410			`if (state == InstrFetch)`
411			`begin`
412			`PCInEn <= High;`
413			`IRInEn <= High;`
414			`ACCInEn <= Low;`
415			`ACCOutEn <= Low;`
416			`MemReq <= High;`
417			`RdWrBar <= High;`
418			`AddressSel <= SelInstrAddr;`
419			`ALUSrcBSel <= SelAddress;`
420			`end`
421			`else`
422			`if (state == InstrExec)`
423			`begin`
424			`case (OpCode)`
425
426			`LDA:`
427			`begin`
428			`PCInEn <= Low;`
429			`IRInEn <= Low;`
430			`ACCInEn <= High;`
431			`ACCOutEn <= Low;`
432			`MemReq <= High;`
433			`RdWrBar <= High;`
434			`AddressSel <= SelOperandAddr;`
435			`ALUSrcBSel <= SelData;`
436			`end`
437			`STO:`
438			`begin`
439			`PCInEn <= Low;`
440			`IRInEn <= Low;`
441			`ACCInEn <= Low;`
442			`ACCOutEn <= High;`
443			`MemReq <= High;`
444			`RdWrBar <= Low;`
445			`AddressSel <= SelOperandAddr;`
446			`ALUSrcBSel <= SelAddress;`
447			`end`
448			`ADD:`
449			`begin`
450			`PCInEn <= Low;`
451			`IRInEn <= Low;`
452			`ACCInEn <= High;`
453			`ACCOutEn <= Low;`
454			`MemReq <= High;`
455			`RdWrBar <= High;`
456			`AddressSel <= SelOperandAddr;`
457			`ALUSrcBSel <= SelData;`
458			`end`
459			`SUB:`
460			`begin`
461			`PCInEn <= Low;`
462			`IRInEn <= Low;`
463			`ACCInEn <= High;`
464			`ACCOutEn <= Low;`
465			`MemReq <= High;`
466			`RdWrBar <= High;`
467			`AddressSel <= SelOperandAddr;`
468			`ALUSrcBSel <= SelData;`
469			`end`
470			`JMP:`
471			`begin`
472			`PCInEn <= High;`
473			`IRInEn <= Low;`
474			`ACCInEn <= Low;`
475			`ACCOutEn <= Low;`
476			`MemReq <= Low;`
477			`RdWrBar <= High;`
478			`AddressSel <= SelOperandAddr;`
479			`ALUSrcBSel <= SelAddress;`
480			`end`
481			`JGE:`
482			`begin`
483			`PCInEn <= ~ACCNeg;`
484			`IRInEn <= Low;`
485			`ACCInEn <= Low;`
486			`ACCOutEn <= Low;`
487			`MemReq <= Low;`
488			`RdWrBar <= High;`
489			`AddressSel <= SelOperandAddr;`
490			`ALUSrcBSel <= SelAddress;`
491			`end`
492			`JNE:`
493			`begin`
494			`PCInEn <= ~ACCZero;`
495			`IRInEn <= Low;`
496			`ACCInEn <= Low;`
497			`ACCOutEn <= Low;`
498			`MemReq <= Low;`
499			`RdWrBar <= High;`
500			`AddressSel <= SelOperandAddr;`
501			`ALUSrcBSel <= SelAddress;`
502			`end`
503			`STP:`
504			`begin`
505			`PCInEn <= Low;`
506			`IRInEn <= Low;`
507			`ACCInEn <= Low;`
508			`ACCOutEn <= Low;`
509			`MemReq <= Low;`
510			`RdWrBar <= High;`
511			`AddressSel <= SelAddress;`
512			`ALUSrcBSel <= SelAddress;`
513			`end`
514			`SHR:`
515			`begin`
516			`PCInEn <= Low;`
517			`IRInEn <= Low;`
518			`ACCInEn <= High;`
519			`ACCOutEn <= Low;`
520			`MemReq <= Low;`
521			`RdWrBar <= Low;`
522			`AddressSel <= SelOperandAddr;`
523			`ALUSrcBSel <= SelAddress;`
524			`end`
525			`SHL:`
526			`begin`
527			`PCInEn <= Low;`
528			`IRInEn <= Low;`
529			`ACCInEn <= High;`
530			`ACCOutEn <= Low;`
531			`MemReq <= Low;`
532			`RdWrBar <= Low;`
533			`AddressSel <= SelOperandAddr;`
534			`ALUSrcBSel <= SelAddress;`
535			`end`
536			`AND:`
537			`begin`
538			`PCInEn <= Low;`
539			`IRInEn <= Low;`
540			`ACCInEn <= High;`
541			`ACCOutEn <= Low;`
542			`MemReq <= High;`
543			`RdWrBar <= High;`
544			`AddressSel <= SelOperandAddr;`
545			`ALUSrcBSel <= SelData;`
546			`end`
547			`OR:`
548			`begin`
549			`PCInEn <= Low;`
550			`IRInEn <= Low;`
551			`ACCInEn <= High;`
552			`ACCOutEn <= Low;`
553			`MemReq <= High;`
554			`RdWrBar <= High;`
555			`AddressSel <= SelOperandAddr;`
556			`ALUSrcBSel <= SelData;`
557			`end`
558			`XOR:`
559			`begin`
560			`PCInEn <= Low;`
561			`IRInEn <= Low;`
562			`ACCInEn <= High;`
563			`ACCOutEn <= Low;`
564			`MemReq <= High;`
565			`RdWrBar <= High;`
566			`AddressSel <= SelOperandAddr;`
567			`ALUSrcBSel <= SelData;`
568			`end`
569			`COM:`
570			`begin`
571			`PCInEn <= Low;`
572			`IRInEn <= Low;`
573			`ACCInEn <= High;`
574			`ACCOutEn <= Low;`
575			`MemReq <= High;`
576			`RdWrBar <= High;`
577			`AddressSel <= SelOperandAddr;`
578			`ALUSrcBSel <= SelData;`
579			`end`
580			`SWP:`
581			`begin`
582			`PCInEn <= Low;`
583			`IRInEn <= Low;`
584			`ACCInEn <= High;`
585			`ACCOutEn <= Low;`
586			`MemReq <= High;`
587			`RdWrBar <= High;`
588			`AddressSel <= SelOperandAddr;`
589			`ALUSrcBSel <= SelData;`
590			`end`
591			`NOP:`
592			`begin`
593			`PCInEn <= Low;`
594			`IRInEn <= Low;`
595			`ACCInEn <= Low;`
596			`ACCOutEn <= Low;`
597			`MemReq <= Low;`
598			`RdWrBar <= High;`
599			`AddressSel <= SelOperandAddr;`
600			`ALUSrcBSel <= SelAddress;`
601			`end`
602			`default:`
603			`begin`
604			`PCInEn <= Low;`
605			`IRInEn <= Low;`
606			`ACCInEn <= Low;`
607			`ACCOutEn <= Low;`
608			`MemReq <= Low;`
609			`RdWrBar <= High;`
610			`AddressSel <= SelOperandAddr;`
611			`ALUSrcBSel <= SelAddress;`
612			`end`
613			`endcase`
614			`end`
615			`else`
616			`if (state == InstrStop)`
617			`begin`
618			`PCInEn <= Low;`
619			`IRInEn <= Low;`
620			`ACCInEn <= Low;`
621			`ACCOutEn <= Low;`
622			`MemReq <= Low;`
623			`RdWrBar <= High;`
624			`AddressSel <= SelAddress;`
625			`ALUSrcBSel <= SelAddress;`
626			`end`
627			`end`
628			`endmodule`