OpenCores
URL https://opencores.org/ocsvn/embedded_risc/embedded_risc/trunk

Subversion Repositories embedded_risc

[/] [embedded_risc/] [trunk/] [Verilog/] [MUX16.V] - Blame information for rev 26

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 hosseinami
/****************************************************************************************
2
 MODULE:                Sub Level Multiplexer Block
3
 
4
 FILE NAME:     mux16.v
5
 VERSION:       1.0
6
 DATE:          September 28th, 2001
7
 AUTHOR:                Hossein Amidi
8
 COMPANY:       California Unique Electrical Co.
9
 CODE TYPE:     Register Transfer Level
10
 
11
 Instantiations:
12
 
13
 DESCRIPTION:
14
 Sub Level RTL Multiplexer block
15
 
16
 Hossein Amidi
17
 (C) September 2001
18
 California Unique Electric
19
 
20
***************************************************************************************/
21
 
22
`timescale 1ns / 1ps
23
 
24
module MUX16 (  // Input
25
                                        A_in,
26
                                        B_in,
27
                                        A_Select,
28
                                        // Output
29
                                        Out
30
                                        );
31
 
32
// Parameter
33
parameter DataWidth = 32;
34
parameter AddrWidth = 24;
35
 
36
// Input
37
input  [AddrWidth - 1 : 0]  A_in;
38
input  [DataWidth - 1 : 0]  B_in;
39
input  A_Select;
40
 
41
// Output
42
output [DataWidth - 1 : 0]  Out;
43
 
44
//Dataflow description of MUX16
45
 
46
assign Out = A_Select ? B_in : {8'b0, A_in};
47
 
48
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.