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/*********************************************************
 MODULE:                Sub Level Bus Arbiter Block
 
 FILE NAME:     bus_arbiter.v
 VERSION:       1.0
 DATE:          May 7th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the top level RTL code of Bus Arbiter verilog code.
 
 It will instantiate the following blocks in the ASIC:
 
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
// TOP MODULE
module bus_arbiter(// Inputs
                                                reset,
                                                clk0,
                                                bus_request,
                                                dma_dataout,
                                                dma_addr,
                                                dma_cmd,
                                                dcache_dataout,
                                                dcache_addr,
                                                dcache_cmd,
                                                icache_dataout,
                                                icache_addr,
                                                icache_cmd,
                                                sdram_dataout,
                                                // Outputs
                                                bus_grant,
                                                dma_datain,
                                                dcache_datain,
                                                icache_datain,
                                                sdram_addr,
                                                sdram_cmd,
                                                sdram_datain
                                                );
 
 
// Parameter
`include        "parameter.v"
 
// FSM States
parameter       s_idle  = 8'b0000_0001,
                                s_tap1  = 8'b0000_0010,
                                s_tap2  = 8'b0000_0100,
                                s_tap3  = 8'b0000_1000,
                                s_tap4  = 8'b0001_0000,
                                s_tap5  = 8'b0010_0000,
                                s_tap6  = 8'b0100_0000,
                                s_tap7  = 8'b1000_0000;
 
 
// Inputs
input reset;
input clk0;
input [arbiter_bus_size - 1 : 0]bus_request;
input [fifo_size - 1 : 0]dma_dataout;
input [padd_size - 1 : 0]dma_addr;
input [cmd_size  - 1 : 0]dma_cmd;
input [data_size - 1 : 0]dcache_dataout;
input [padd_size - 1 : 0]dcache_addr;
input [cmd_size  - 1 : 0]dcache_cmd;
input [data_size - 1 : 0]icache_dataout;
input [padd_size - 1 : 0]icache_addr;
input [cmd_size  - 1 : 0]icache_cmd;
input [data_size - 1 : 0]sdram_dataout;
 
// Outputs
output [arbiter_bus_size - 1 : 0]bus_grant;
output [fifo_size - 1 : 0]dma_datain;
output [data_size - 1 : 0]dcache_datain;
output [data_size - 1 : 0]icache_datain;
output [padd_size - 1 : 0]sdram_addr;
output [cmd_size - 1 : 0]sdram_cmd;
output [data_size - 1 : 0]sdram_datain;
 
// Signal Declarations
wire reset;
wire clk0;
wire [arbiter_bus_size - 1 : 0]bus_request;
wire [fifo_size - 1 : 0]dma_dataout;
wire [padd_size - 1 : 0]dma_addr;
wire [cmd_size  - 1 : 0]dma_cmd;
wire [data_size - 1 : 0]dcache_dataout;
wire [padd_size - 1 : 0]dcache_addr;
wire [cmd_size  - 1 : 0]dcache_cmd;
wire [data_size - 1 : 0]icache_dataout;
wire [padd_size - 1 : 0]icache_addr;
wire [cmd_size  - 1 : 0]icache_cmd;
wire [data_size - 1 : 0]sdram_dataout;
 
wire [arbiter_bus_size - 1 : 0]bus_grant;
wire [fifo_size - 1 : 0]dma_datain;
wire [data_size - 1 : 0]dcache_datain;
wire [data_size - 1 : 0]icache_datain;
wire [padd_size - 1 : 0]sdram_addr;
wire [cmd_size - 1 : 0]sdram_cmd;
wire [data_size - 1 : 0]sdram_datain;
 
reg [arbiter_bus_size - 1 : 0]rbus_grant;
reg [fifo_size - 1 : 0]rdma_datain;
reg [data_size - 1 : 0]rdcache_datain;
reg [data_size - 1 : 0]ricache_datain;
reg [padd_size - 1 : 0]rsdram_addr;
reg [cmd_size - 1 : 0]rsdram_cmd;
reg [data_size - 1 : 0]rsdram_datain;
 
 
// State Registers
reg [7:0]state;
 
 
// Assignment statments
 
 
assign bus_grant = rbus_grant;
assign dma_datain = rdma_datain;
assign dcache_datain = rdcache_datain;
assign icache_datain = ricache_datain;
assign sdram_addr = rsdram_addr;
assign sdram_cmd = rsdram_cmd;
assign sdram_datain = rsdram_datain;
 
 
 
// FSM Sequential Section ( One-Hot encoding )
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
                state = s_idle;
        else
        begin
                casex({bus_request,state})
 
                        11'b000_0000_0001:
                                        state = s_idle;
                        11'b001_0000_0001:
                                        state = s_tap1;
                        11'b010_0000_0001:
                                        state = s_tap2;
                        11'b011_0000_0001:
                                        state = s_tap3;
                        11'b100_0000_0001:
                                        state = s_tap4;
                        11'b101_0000_0001:
                                        state = s_tap5;
                        11'b110_0000_0001:
                                        state = s_tap6;
                        11'b111_0000_0001:
                                        state = s_tap7;
                        11'b000_0000_0010:
                                        state = s_idle;
                        11'b001_0000_0010:
                                        state = s_tap1;
                        11'b000_0000_0100:
                                        state = s_idle;
                        11'b010_0000_0100:
                                        state = s_tap2;
                        11'b001_0000_1000:
                                        state = s_tap1;
                        11'b011_0000_1000:
                                        state = s_tap3;
                        11'b000_0001_0000:
                                        state = s_idle;
                        11'b100_0001_0000:
                                        state = s_tap4;
                        11'b101_0010_0000:
                                        state = s_tap5;
                        11'b001_0010_0000:
                                        state = s_tap1;
                        11'b110_0100_0000:
                                        state = s_tap6;
                        11'b010_0100_0000:
                                        state = s_tap2;
                        11'b111_1000_0000:
                                        state = s_tap7;
                        11'b011_1000_0000:
                                        state = s_tap3;
                        default:
                                        state = s_idle;
                endcase
        end
end
 
 
// FSM Presets State Task Call
always @(reset or state)
        state_task(     // Input
                                        state,
                                        reset,
                                        // Outuput
                                        rbus_grant,
                                        rdma_datain,
                                        rdcache_datain,
                                        ricache_datain,
                                        rsdram_addr,
                                        rsdram_cmd,
                                        rsdram_datain
                                        );
 
 
// FSM Task ( Combinatorial Section )
task state_task;
 
//INPUTS
input [7:0]state;
input reset;
 
//OUTPUTS
output [arbiter_bus_size - 1 : 0]rbus_grant;
output [fifo_size - 1 : 0]rdma_datain;
output [data_size - 1 : 0]rdcache_datain;
output [data_size - 1 : 0]ricache_datain;
output [padd_size - 1 : 0]rsdram_addr;
output [cmd_size - 1 : 0]rsdram_cmd;
output [data_size - 1 : 0]rsdram_datain;
 
// Signal Declaration
reg [arbiter_bus_size - 1 : 0]rbus_grant;
reg [fifo_size - 1 : 0]rdma_datain;
reg [data_size - 1 : 0]rdcache_datain;
reg [data_size - 1 : 0]ricache_datain;
reg [padd_size - 1 : 0]rsdram_addr;
reg [cmd_size - 1 : 0]rsdram_cmd;
reg [data_size - 1 : 0]rsdram_datain;
 
 
// Parameter
parameter       s_idle  = 8'b0000_0001,
                                s_tap1  = 8'b0000_0010,
                                s_tap2  = 8'b0000_0100,
                                s_tap3  = 8'b0000_1000,
                                s_tap4  = 8'b0001_0000,
                                s_tap5  = 8'b0010_0000,
                                s_tap6  = 8'b0100_0000,
                                s_tap7  = 8'b1000_0000;
 
begin
 
        if(reset == 1'b1)
        begin
                rbus_grant <= 3'h0;
                rdma_datain <= 8'h0;
                rdcache_datain <= 32'h0;
                ricache_datain <= 32'h0;
                rsdram_addr <= 24'h0;
                rsdram_cmd <= 3'h0;
                rsdram_datain <= 32'h0;
        end
        else
        begin
                case(state)
 
                        s_idle:
                        begin
                                rbus_grant    <= 3'b000;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= 32'h0;
                        end
 
                        s_tap1:
                        begin
                                rbus_grant    <= 3'b001;
                                rdma_datain   <= sdram_dataout;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= dma_addr;
                                rsdram_cmd    <= dma_cmd;
                                rsdram_datain <= dma_dataout;
                        end
 
                        s_tap2:
                        begin
                                rbus_grant    <= 3'b010;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= sdram_dataout;
                                ricache_datain <= sdram_dataout;
                                rsdram_addr   <= dcache_addr | icache_addr;
                                rsdram_cmd    <= dcache_cmd | icache_cmd;
                                rsdram_datain <= dcache_dataout;
                        end
 
                        s_tap3:
                        begin
                                rbus_grant    <= 3'b100;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= dcache_dataout;
                        end
 
                        s_tap4:
                        begin
                                rbus_grant    <= 3'b100;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= icache_dataout;
                        end
 
                        s_tap5:
                        begin
                                rbus_grant    <= 3'b100;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= dcache_dataout;
                        end
 
                        s_tap6:
                        begin
                                rbus_grant    <= 3'b100;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= icache_dataout;
                        end
 
                        s_tap7:
                        begin
                                rbus_grant    <= 3'b100;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= dma_dataout;
                        end
 
                        default:
                        begin
                                rbus_grant    <= 3'b100;
                                rdma_datain   <= 8'h0;
                                rdcache_datain <= 32'h0;
                                ricache_datain <= 32'h0;
                                rsdram_addr   <= 24'h0;
                                rsdram_cmd    <= 3'h0;
                                rsdram_datain <= dcache_dataout;
                        end
                 endcase
        end
end
endtask
 
 
endmodule

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[/] [embedded_risc/] [trunk/] [Verilog/] [bus_arbiter.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level Bus Arbiter Block`
3
4			`FILE NAME: bus_arbiter.v`
5			`VERSION: 1.0`
6			`DATE: May 7th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the top level RTL code of Bus Arbiter verilog code.`
12
13			`It will instantiate the following blocks in the ASIC:`
14
15
16			`Hossein Amidi`
17			`(C) April 2002`
18
19			`*********************************************************/`
20
21			`// DEFINES`
22			`timescale 1ns / 10ps
23
24			`// TOP MODULE`
25			`module bus_arbiter(// Inputs`
26			`reset,`
27			`clk0,`
28			`bus_request,`
29			`dma_dataout,`
30			`dma_addr,`
31			`dma_cmd,`
32			`dcache_dataout,`
33			`dcache_addr,`
34			`dcache_cmd,`
35			`icache_dataout,`
36			`icache_addr,`
37			`icache_cmd,`
38			`sdram_dataout,`
39			`// Outputs`
40			`bus_grant,`
41			`dma_datain,`
42			`dcache_datain,`
43			`icache_datain,`
44			`sdram_addr,`
45			`sdram_cmd,`
46			`sdram_datain`
47			`);`
48
49
50			`// Parameter`
51			`include "parameter.v"
52
53			`// FSM States`
54			`parameter s_idle = 8'b0000_0001,`
55			`s_tap1 = 8'b0000_0010,`
56			`s_tap2 = 8'b0000_0100,`
57			`s_tap3 = 8'b0000_1000,`
58			`s_tap4 = 8'b0001_0000,`
59			`s_tap5 = 8'b0010_0000,`
60			`s_tap6 = 8'b0100_0000,`
61			`s_tap7 = 8'b1000_0000;`
62
63
64			`// Inputs`
65			`input reset;`
66			`input clk0;`
67			`input [arbiter_bus_size - 1 : 0]bus_request;`
68			`input [fifo_size - 1 : 0]dma_dataout;`
69			`input [padd_size - 1 : 0]dma_addr;`
70			`input [cmd_size - 1 : 0]dma_cmd;`
71			`input [data_size - 1 : 0]dcache_dataout;`
72			`input [padd_size - 1 : 0]dcache_addr;`
73			`input [cmd_size - 1 : 0]dcache_cmd;`
74			`input [data_size - 1 : 0]icache_dataout;`
75			`input [padd_size - 1 : 0]icache_addr;`
76			`input [cmd_size - 1 : 0]icache_cmd;`
77			`input [data_size - 1 : 0]sdram_dataout;`
78
79			`// Outputs`
80			`output [arbiter_bus_size - 1 : 0]bus_grant;`
81			`output [fifo_size - 1 : 0]dma_datain;`
82			`output [data_size - 1 : 0]dcache_datain;`
83			`output [data_size - 1 : 0]icache_datain;`
84			`output [padd_size - 1 : 0]sdram_addr;`
85			`output [cmd_size - 1 : 0]sdram_cmd;`
86			`output [data_size - 1 : 0]sdram_datain;`
87
88			`// Signal Declarations`
89			`wire reset;`
90			`wire clk0;`
91			`wire [arbiter_bus_size - 1 : 0]bus_request;`
92			`wire [fifo_size - 1 : 0]dma_dataout;`
93			`wire [padd_size - 1 : 0]dma_addr;`
94			`wire [cmd_size - 1 : 0]dma_cmd;`
95			`wire [data_size - 1 : 0]dcache_dataout;`
96			`wire [padd_size - 1 : 0]dcache_addr;`
97			`wire [cmd_size - 1 : 0]dcache_cmd;`
98			`wire [data_size - 1 : 0]icache_dataout;`
99			`wire [padd_size - 1 : 0]icache_addr;`
100			`wire [cmd_size - 1 : 0]icache_cmd;`
101			`wire [data_size - 1 : 0]sdram_dataout;`
102
103			`wire [arbiter_bus_size - 1 : 0]bus_grant;`
104			`wire [fifo_size - 1 : 0]dma_datain;`
105			`wire [data_size - 1 : 0]dcache_datain;`
106			`wire [data_size - 1 : 0]icache_datain;`
107			`wire [padd_size - 1 : 0]sdram_addr;`
108			`wire [cmd_size - 1 : 0]sdram_cmd;`
109			`wire [data_size - 1 : 0]sdram_datain;`
110
111			`reg [arbiter_bus_size - 1 : 0]rbus_grant;`
112			`reg [fifo_size - 1 : 0]rdma_datain;`
113			`reg [data_size - 1 : 0]rdcache_datain;`
114			`reg [data_size - 1 : 0]ricache_datain;`
115			`reg [padd_size - 1 : 0]rsdram_addr;`
116			`reg [cmd_size - 1 : 0]rsdram_cmd;`
117			`reg [data_size - 1 : 0]rsdram_datain;`
118
119
120			`// State Registers`
121			`reg [7:0]state;`
122
123
124			`// Assignment statments`
125
126
127			`assign bus_grant = rbus_grant;`
128			`assign dma_datain = rdma_datain;`
129			`assign dcache_datain = rdcache_datain;`
130			`assign icache_datain = ricache_datain;`
131			`assign sdram_addr = rsdram_addr;`
132			`assign sdram_cmd = rsdram_cmd;`
133			`assign sdram_datain = rsdram_datain;`
134
135
136
137			`// FSM Sequential Section ( One-Hot encoding )`
138			`always @(posedge reset or posedge clk0)`
139			`begin`
140			`if(reset == 1'b1)`
141			`state = s_idle;`
142			`else`
143			`begin`
144			`casex({bus_request,state})`
145
146			`11'b000_0000_0001:`
147			`state = s_idle;`
148			`11'b001_0000_0001:`
149			`state = s_tap1;`
150			`11'b010_0000_0001:`
151			`state = s_tap2;`
152			`11'b011_0000_0001:`
153			`state = s_tap3;`
154			`11'b100_0000_0001:`
155			`state = s_tap4;`
156			`11'b101_0000_0001:`
157			`state = s_tap5;`
158			`11'b110_0000_0001:`
159			`state = s_tap6;`
160			`11'b111_0000_0001:`
161			`state = s_tap7;`
162			`11'b000_0000_0010:`
163			`state = s_idle;`
164			`11'b001_0000_0010:`
165			`state = s_tap1;`
166			`11'b000_0000_0100:`
167			`state = s_idle;`
168			`11'b010_0000_0100:`
169			`state = s_tap2;`
170			`11'b001_0000_1000:`
171			`state = s_tap1;`
172			`11'b011_0000_1000:`
173			`state = s_tap3;`
174			`11'b000_0001_0000:`
175			`state = s_idle;`
176			`11'b100_0001_0000:`
177			`state = s_tap4;`
178			`11'b101_0010_0000:`
179			`state = s_tap5;`
180			`11'b001_0010_0000:`
181			`state = s_tap1;`
182			`11'b110_0100_0000:`
183			`state = s_tap6;`
184			`11'b010_0100_0000:`
185			`state = s_tap2;`
186			`11'b111_1000_0000:`
187			`state = s_tap7;`
188			`11'b011_1000_0000:`
189			`state = s_tap3;`
190			`default:`
191			`state = s_idle;`
192			`endcase`
193			`end`
194			`end`
195
196
197			`// FSM Presets State Task Call`
198			`always @(reset or state)`
199			`state_task( // Input`
200			`state,`
201			`reset,`
202			`// Outuput`
203			`rbus_grant,`
204			`rdma_datain,`
205			`rdcache_datain,`
206			`ricache_datain,`
207			`rsdram_addr,`
208			`rsdram_cmd,`
209			`rsdram_datain`
210			`);`
211
212
213			`// FSM Task ( Combinatorial Section )`
214			`task state_task;`
215
216			`//INPUTS`
217			`input [7:0]state;`
218			`input reset;`
219
220			`//OUTPUTS`
221			`output [arbiter_bus_size - 1 : 0]rbus_grant;`
222			`output [fifo_size - 1 : 0]rdma_datain;`
223			`output [data_size - 1 : 0]rdcache_datain;`
224			`output [data_size - 1 : 0]ricache_datain;`
225			`output [padd_size - 1 : 0]rsdram_addr;`
226			`output [cmd_size - 1 : 0]rsdram_cmd;`
227			`output [data_size - 1 : 0]rsdram_datain;`
228
229			`// Signal Declaration`
230			`reg [arbiter_bus_size - 1 : 0]rbus_grant;`
231			`reg [fifo_size - 1 : 0]rdma_datain;`
232			`reg [data_size - 1 : 0]rdcache_datain;`
233			`reg [data_size - 1 : 0]ricache_datain;`
234			`reg [padd_size - 1 : 0]rsdram_addr;`
235			`reg [cmd_size - 1 : 0]rsdram_cmd;`
236			`reg [data_size - 1 : 0]rsdram_datain;`
237
238
239			`// Parameter`
240			`parameter s_idle = 8'b0000_0001,`
241			`s_tap1 = 8'b0000_0010,`
242			`s_tap2 = 8'b0000_0100,`
243			`s_tap3 = 8'b0000_1000,`
244			`s_tap4 = 8'b0001_0000,`
245			`s_tap5 = 8'b0010_0000,`
246			`s_tap6 = 8'b0100_0000,`
247			`s_tap7 = 8'b1000_0000;`
248
249			`begin`
250
251			`if(reset == 1'b1)`
252			`begin`
253			`rbus_grant <= 3'h0;`
254			`rdma_datain <= 8'h0;`
255			`rdcache_datain <= 32'h0;`
256			`ricache_datain <= 32'h0;`
257			`rsdram_addr <= 24'h0;`
258			`rsdram_cmd <= 3'h0;`
259			`rsdram_datain <= 32'h0;`
260			`end`
261			`else`
262			`begin`
263			`case(state)`
264
265			`s_idle:`
266			`begin`
267			`rbus_grant <= 3'b000;`
268			`rdma_datain <= 8'h0;`
269			`rdcache_datain <= 32'h0;`
270			`ricache_datain <= 32'h0;`
271			`rsdram_addr <= 24'h0;`
272			`rsdram_cmd <= 3'h0;`
273			`rsdram_datain <= 32'h0;`
274			`end`
275
276			`s_tap1:`
277			`begin`
278			`rbus_grant <= 3'b001;`
279			`rdma_datain <= sdram_dataout;`
280			`rdcache_datain <= 32'h0;`
281			`ricache_datain <= 32'h0;`
282			`rsdram_addr <= dma_addr;`
283			`rsdram_cmd <= dma_cmd;`
284			`rsdram_datain <= dma_dataout;`
285			`end`
286
287			`s_tap2:`
288			`begin`
289			`rbus_grant <= 3'b010;`
290			`rdma_datain <= 8'h0;`
291			`rdcache_datain <= sdram_dataout;`
292			`ricache_datain <= sdram_dataout;`
293			`rsdram_addr <= dcache_addr \| icache_addr;`
294			`rsdram_cmd <= dcache_cmd \| icache_cmd;`
295			`rsdram_datain <= dcache_dataout;`
296			`end`
297
298			`s_tap3:`
299			`begin`
300			`rbus_grant <= 3'b100;`
301			`rdma_datain <= 8'h0;`
302			`rdcache_datain <= 32'h0;`
303			`ricache_datain <= 32'h0;`
304			`rsdram_addr <= 24'h0;`
305			`rsdram_cmd <= 3'h0;`
306			`rsdram_datain <= dcache_dataout;`
307			`end`
308
309			`s_tap4:`
310			`begin`
311			`rbus_grant <= 3'b100;`
312			`rdma_datain <= 8'h0;`
313			`rdcache_datain <= 32'h0;`
314			`ricache_datain <= 32'h0;`
315			`rsdram_addr <= 24'h0;`
316			`rsdram_cmd <= 3'h0;`
317			`rsdram_datain <= icache_dataout;`
318			`end`
319
320			`s_tap5:`
321			`begin`
322			`rbus_grant <= 3'b100;`
323			`rdma_datain <= 8'h0;`
324			`rdcache_datain <= 32'h0;`
325			`ricache_datain <= 32'h0;`
326			`rsdram_addr <= 24'h0;`
327			`rsdram_cmd <= 3'h0;`
328			`rsdram_datain <= dcache_dataout;`
329			`end`
330
331			`s_tap6:`
332			`begin`
333			`rbus_grant <= 3'b100;`
334			`rdma_datain <= 8'h0;`
335			`rdcache_datain <= 32'h0;`
336			`ricache_datain <= 32'h0;`
337			`rsdram_addr <= 24'h0;`
338			`rsdram_cmd <= 3'h0;`
339			`rsdram_datain <= icache_dataout;`
340			`end`
341
342			`s_tap7:`
343			`begin`
344			`rbus_grant <= 3'b100;`
345			`rdma_datain <= 8'h0;`
346			`rdcache_datain <= 32'h0;`
347			`ricache_datain <= 32'h0;`
348			`rsdram_addr <= 24'h0;`
349			`rsdram_cmd <= 3'h0;`
350			`rsdram_datain <= dma_dataout;`
351			`end`
352
353			`default:`
354			`begin`
355			`rbus_grant <= 3'b100;`
356			`rdma_datain <= 8'h0;`
357			`rdcache_datain <= 32'h0;`
358			`ricache_datain <= 32'h0;`
359			`rsdram_addr <= 24'h0;`
360			`rsdram_cmd <= 3'h0;`
361			`rsdram_datain <= dcache_dataout;`
362			`end`
363			`endcase`
364			`end`
365			`end`
366			`endtask`
367
368
369			`endmodule`