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[/] [embedded_risc/] [trunk/] [Verilog/] [cmd_decoder.v] - Blame information for rev 26

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/*********************************************************
 MODULE:                Sub Level Command Interface Decoder
 
 FILE NAME:     cmd_decoder.v
 VERSION:       1.0
 DATE:          April 28th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the sub level RTL code of SDRAM Controller ASIC verilog
 code. It will Decode the incoming uProcessor command for internal State Machines.
 
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
 
module cmd_decoder(// Input
                                                        reset,
                                                        clk0,
                                                        paddr,
                                                        cmd,
                                                        cmdack,
                                                        // Output
                                                        nop,
                                                        reada,
                                                        writea,
                                                        refresh,
                                                        preacharge,
                                                        load_mod,
                                                        load_time,
                                                        load_rfcnt,
                                                        caddr
                                                        );
 
// Parameter
`include        "parameter.v"
 
// Input
input reset;
input clk0;
input [padd_size - 1 : 0]paddr;
input [cmd_size  - 1 : 0]cmd;
input cmdack;
 
// Output
output nop;
output reada;
output writea;
output refresh;
output preacharge;
output load_mod;
output load_time;
output load_rfcnt;
output [padd_size - 1 : 0]caddr;
 
 
// Internal wire and reg signals
reg nop;
reg reada;
reg writea;
reg refresh;
reg preacharge;
reg load_mod;
reg load_time;
reg load_rfcnt;
reg [padd_size - 1 : 0]caddr;
 
 
// Assignment
 
 
 
//Command Decoder and Address Register
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                nop             <= 1'b0;
                reada           <= 1'b0;
                writea          <= 1'b0;
                refresh         <= 1'b0;
                preacharge      <= 1'b0;
                load_mod                <= 1'b0;
                load_time   <= 1'b0;
                load_rfcnt  <= 1'b0;
                caddr           <= 24'h00_0000;
        end
        else
        begin
                // Register the Address Buss to match the timing
                caddr <= paddr;
 
                if(cmd == 3'b000)
                        nop <= 1'b1;
                else
                        nop <= 1'b0;
 
                if(cmd == 3'b001)
                        reada <= 1'b1;
                else
                        reada <= 1'b0;
 
                if(cmd == 3'b010)
                        writea <= 1'b1;
                else
                        writea <= 1'b0;
 
                if(cmd == 3'b011)
                        refresh <= 1'b1;
                else
                        refresh <= 1'b0;
 
                if(cmd == 3'b100)
                        preacharge <= 1'b1;
                else
                        preacharge <= 1'b0;
 
                if(cmd == 3'b101)
                        load_mod <= 1'b1;
                else
                        load_mod <= 1'b0;
 
                if((cmd == 3'b110) & (load_time == 1'b0) & (cmdack == 1'b0))
                        load_time <= 1'b1;
                else
                        load_time <= 1'b0;
 
                if((cmd == 3'b111) & (load_rfcnt == 1'b0) & (cmdack == 1'b0))
                        load_rfcnt <= 1'b1;
                else
                        load_rfcnt <= 1'b0;
        end
end
 
/*
                casex({cmdack,load_rfcnt,load_time,cmd})
 
                        6'bx_x_x_000: nop                       <= 1'b1;
                        6'bx_x_x_001: reada                     <= 1'b1;
                        6'bx_x_x_010: writea                    <= 1'b1;
                        6'bx_x_x_011: refresh           <= 1'b1;
                        6'bx_x_x_100: preacharge        <= 1'b1;
                        6'bx_x_x_101: load_mod          <= 1'b1;
                        6'b0_x_0_110: load_time         <= 1'b1;
                        6'b0_0_x_111: load_rfcnt        <= 1'b1;
                        default:
                        begin
                                nop                     <= 1'b0;
                                reada           <= 1'b0;
                                writea          <= 1'b0;
                                refresh                 <= 1'b0;
                                preacharge      <= 1'b0;
                                load_mod        <= 1'b0;
                                load_time       <= 1'b0;
                                load_rfcnt      <= 1'b0;
                        end
                endcase
*/
 
endmodule

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level Command Interface Decoder`
3
4			`FILE NAME: cmd_decoder.v`
5			`VERSION: 1.0`
6			`DATE: April 28th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog`
12			`code. It will Decode the incoming uProcessor command for internal State Machines.`
13
14
15			`Hossein Amidi`
16			`(C) April 2002`
17
18			`*********************************************************/`
19
20			`// DEFINES`
21			`timescale 1ns / 10ps
22
23
24			`module cmd_decoder(// Input`
25			`reset,`
26			`clk0,`
27			`paddr,`
28			`cmd,`
29			`cmdack,`
30			`// Output`
31			`nop,`
32			`reada,`
33			`writea,`
34			`refresh,`
35			`preacharge,`
36			`load_mod,`
37			`load_time,`
38			`load_rfcnt,`
39			`caddr`
40			`);`
41
42			`// Parameter`
43			`include "parameter.v"
44
45			`// Input`
46			`input reset;`
47			`input clk0;`
48			`input [padd_size - 1 : 0]paddr;`
49			`input [cmd_size - 1 : 0]cmd;`
50			`input cmdack;`
51
52			`// Output`
53			`output nop;`
54			`output reada;`
55			`output writea;`
56			`output refresh;`
57			`output preacharge;`
58			`output load_mod;`
59			`output load_time;`
60			`output load_rfcnt;`
61			`output [padd_size - 1 : 0]caddr;`
62
63
64			`// Internal wire and reg signals`
65			`reg nop;`
66			`reg reada;`
67			`reg writea;`
68			`reg refresh;`
69			`reg preacharge;`
70			`reg load_mod;`
71			`reg load_time;`
72			`reg load_rfcnt;`
73			`reg [padd_size - 1 : 0]caddr;`
74
75
76			`// Assignment`
77
78
79
80			`//Command Decoder and Address Register`
81			`always @(posedge reset or posedge clk0)`
82			`begin`
83			`if(reset == 1'b1)`
84			`begin`
85			`nop <= 1'b0;`
86			`reada <= 1'b0;`
87			`writea <= 1'b0;`
88			`refresh <= 1'b0;`
89			`preacharge <= 1'b0;`
90			`load_mod <= 1'b0;`
91			`load_time <= 1'b0;`
92			`load_rfcnt <= 1'b0;`
93			`caddr <= 24'h00_0000;`
94			`end`
95			`else`
96			`begin`
97			`// Register the Address Buss to match the timing`
98			`caddr <= paddr;`
99
100			`if(cmd == 3'b000)`
101			`nop <= 1'b1;`
102			`else`
103			`nop <= 1'b0;`
104
105			`if(cmd == 3'b001)`
106			`reada <= 1'b1;`
107			`else`
108			`reada <= 1'b0;`
109
110			`if(cmd == 3'b010)`
111			`writea <= 1'b1;`
112			`else`
113			`writea <= 1'b0;`
114
115			`if(cmd == 3'b011)`
116			`refresh <= 1'b1;`
117			`else`
118			`refresh <= 1'b0;`
119
120			`if(cmd == 3'b100)`
121			`preacharge <= 1'b1;`
122			`else`
123			`preacharge <= 1'b0;`
124
125			`if(cmd == 3'b101)`
126			`load_mod <= 1'b1;`
127			`else`
128			`load_mod <= 1'b0;`
129
130			`if((cmd == 3'b110) & (load_time == 1'b0) & (cmdack == 1'b0))`
131			`load_time <= 1'b1;`
132			`else`
133			`load_time <= 1'b0;`
134
135			`if((cmd == 3'b111) & (load_rfcnt == 1'b0) & (cmdack == 1'b0))`
136			`load_rfcnt <= 1'b1;`
137			`else`
138			`load_rfcnt <= 1'b0;`
139			`end`
140			`end`
141
142			`/*`
143			`casex({cmdack,load_rfcnt,load_time,cmd})`
144
145			`6'bx_x_x_000: nop <= 1'b1;`
146			`6'bx_x_x_001: reada <= 1'b1;`
147			`6'bx_x_x_010: writea <= 1'b1;`
148			`6'bx_x_x_011: refresh <= 1'b1;`
149			`6'bx_x_x_100: preacharge <= 1'b1;`
150			`6'bx_x_x_101: load_mod <= 1'b1;`
151			`6'b0_x_0_110: load_time <= 1'b1;`
152			`6'b0_0_x_111: load_rfcnt <= 1'b1;`
153			`default:`
154			`begin`
155			`nop <= 1'b0;`
156			`reada <= 1'b0;`
157			`writea <= 1'b0;`
158			`refresh <= 1'b0;`
159			`preacharge <= 1'b0;`
160			`load_mod <= 1'b0;`
161			`load_time <= 1'b0;`
162			`load_rfcnt <= 1'b0;`
163			`end`
164			`endcase`
165			`*/`
166
167			`endmodule`

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[/] [embedded_risc/] [trunk/] [Verilog/] [cmd_decoder.v] - Blame information for rev 26