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/*********************************************************
 MODULE:                Sub Level SDRAM Command Detector
 
 FILE NAME:     cmd_detector.v
 VERSION:       1.0
 DATE:          May 2nd, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the sub level RTL code of SDRAM Controller ASIC verilog
 code. It will detect the uProcessor command and create appropriate internal signal
 for SDRAM Controller FSM.
 
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
module cmd_detector(// Input
                                                        reset,
                                                        clk0,
                                                        nop,
                                                        ref_req,
                                                        refresh,
                                                        reada,
                                                        writea,
                                                        preacharge,
                                                        load_mod,
                                                        ref_dur,
                                                        // Output
                                                        do_nop,
                                                        do_reada,
                                                        do_writea,
                                                        do_writea1,
                                                        do_refresh,
                                                        do_preacharge,
                                                        do_load_mod,
                                                        rw_flag
                                                        );
 
 
// Parameter
`include        "parameter.v"
 
// Input
input reset;
input clk0;
input nop;
input ref_req;
input refresh;
input reada;
input writea;
input preacharge;
input load_mod;
input [ref_dur_size - 1 : 0]ref_dur;
 
// Output
output do_nop;
output do_reada;
output do_writea;
output do_writea1;
output do_refresh;
output do_preacharge;
output do_load_mod;
output rw_flag;
 
// Internal wire and reg signals
wire reset;
wire clk0;
wire nop;
wire ref_req;
wire refresh;
wire reada;
wire writea;
wire preacharge;
wire load_mod;
wire [ref_dur_size - 1 : 0]ref_dur;
 
reg do_nop;
reg do_reada;
reg do_writea;
reg do_writea1;
reg do_refresh;
reg do_preacharge;
reg do_load_mod;
reg command_done;
reg [7:0]command_delay;
reg rw_flag;
reg [3:0]rp_shift;
reg rp_done;
 
// Assignment
 
 
// This always block monitors the individual command lines and issues a command
// to the next stage if there currently another command already running.
//
always @(posedge reset or posedge clk0)
begin
        if (reset == 1'b1)
        begin
                do_nop          <= 0;
                do_reada        <= 0;
                do_writea       <= 0;
                do_refresh      <= 0;
                do_preacharge   <= 0;
                do_load_mod     <= 0;
                command_done    <= 0;
                command_delay   <= 8'b0000_0000;
                rw_flag         <= 0;
                rp_shift        <= 0;
                rp_done         <= 0;
        end
 
        else
        begin
 
//  Issue the appropriate command if the sdram is not currently busy     
                if ((nop == 1)  & (command_done == 0) & (do_nop == 0))                                                                                            // refresh
                        do_nop <= 1;
                else
                        do_nop <= 0;
 
                                        if ((ref_req == 1 | refresh == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // refresh
                        & do_reada == 0 & do_writea == 0)
                        do_refresh <= 1;
                else
                        do_refresh <= 0;
 
                if ((reada == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (ref_req == 0))    // reada
                        do_reada <= 1;
                else
                        do_reada <= 0;
 
                if ((writea == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (ref_req == 0))  // writea
                begin
                        do_writea <= 1;
                        do_writea1 <= 1;
                end
                else
                begin
                        do_writea <= 0;
                        do_writea1 <= 0;
                end
                if ((preacharge == 1) & (command_done == 0) & (do_preacharge == 0))                              // preacharge
                        do_preacharge <= 1;
                else
                        do_preacharge <= 0;
 
                if ((load_mod == 1) & (command_done == 0) & (do_load_mod == 0))                              // LOADMODE
                        do_load_mod <= 1;
                else
                        do_load_mod <= 0;
 
// set command_delay shift register and command_done flag
// The command delay shift register is a timer that is used to ensure that
// the SDRAM devices have had sufficient time to finish the last command.
 
                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_preacharge == 1)
                     | (do_load_mod))
                begin
                        command_delay <= 8'b11111111;
                        command_done  <= 1;
                        rw_flag <= do_reada;
 
                end
 
                else
                begin
                        command_done        <= command_delay[0];                // the command_delay shift operation
                        command_delay[6:0]  <= command_delay[7:1];
                        command_delay[7]    <= 0;
                end
 
 
 // start additional timer that is used for the refresh, writea, reada commands               
                if (command_delay[0] == 0 & command_done == 1)
                begin
//                        rp_shift <= 4'b1111;
                        rp_shift <= ref_dur;
                        rp_done <= 1;
                end
                else
                begin
                        rp_done         <= rp_shift[0];
                        rp_shift[2:0]   <= rp_shift[3:1];
                        rp_shift[3]     <= 0;
                end
        end
end
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level SDRAM Command Detector`
3
4			`FILE NAME: cmd_detector.v`
5			`VERSION: 1.0`
6			`DATE: May 2nd, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog`
12			`code. It will detect the uProcessor command and create appropriate internal signal`
13			`for SDRAM Controller FSM.`
14
15
16			`Hossein Amidi`
17			`(C) April 2002`
18
19			`*********************************************************/`
20
21			`// DEFINES`
22			`timescale 1ns / 10ps
23
24			`module cmd_detector(// Input`
25			`reset,`
26			`clk0,`
27			`nop,`
28			`ref_req,`
29			`refresh,`
30			`reada,`
31			`writea,`
32			`preacharge,`
33			`load_mod,`
34			`ref_dur,`
35			`// Output`
36			`do_nop,`
37			`do_reada,`
38			`do_writea,`
39			`do_writea1,`
40			`do_refresh,`
41			`do_preacharge,`
42			`do_load_mod,`
43			`rw_flag`
44			`);`
45
46
47			`// Parameter`
48			`include "parameter.v"
49
50			`// Input`
51			`input reset;`
52			`input clk0;`
53			`input nop;`
54			`input ref_req;`
55			`input refresh;`
56			`input reada;`
57			`input writea;`
58			`input preacharge;`
59			`input load_mod;`
60			`input [ref_dur_size - 1 : 0]ref_dur;`
61
62			`// Output`
63			`output do_nop;`
64			`output do_reada;`
65			`output do_writea;`
66			`output do_writea1;`
67			`output do_refresh;`
68			`output do_preacharge;`
69			`output do_load_mod;`
70			`output rw_flag;`
71
72			`// Internal wire and reg signals`
73			`wire reset;`
74			`wire clk0;`
75			`wire nop;`
76			`wire ref_req;`
77			`wire refresh;`
78			`wire reada;`
79			`wire writea;`
80			`wire preacharge;`
81			`wire load_mod;`
82			`wire [ref_dur_size - 1 : 0]ref_dur;`
83
84			`reg do_nop;`
85			`reg do_reada;`
86			`reg do_writea;`
87			`reg do_writea1;`
88			`reg do_refresh;`
89			`reg do_preacharge;`
90			`reg do_load_mod;`
91			`reg command_done;`
92			`reg [7:0]command_delay;`
93			`reg rw_flag;`
94			`reg [3:0]rp_shift;`
95			`reg rp_done;`
96
97			`// Assignment`
98
99
100			`// This always block monitors the individual command lines and issues a command`
101			`// to the next stage if there currently another command already running.`
102			`//`
103			`always @(posedge reset or posedge clk0)`
104			`begin`
105			`if (reset == 1'b1)`
106			`begin`
107			`do_nop <= 0;`
108			`do_reada <= 0;`
109			`do_writea <= 0;`
110			`do_refresh <= 0;`
111			`do_preacharge <= 0;`
112			`do_load_mod <= 0;`
113			`command_done <= 0;`
114			`command_delay <= 8'b0000_0000;`
115			`rw_flag <= 0;`
116			`rp_shift <= 0;`
117			`rp_done <= 0;`
118			`end`
119
120			`else`
121			`begin`
122
123			`// Issue the appropriate command if the sdram is not currently busy`
124			`if ((nop == 1) & (command_done == 0) & (do_nop == 0)) // refresh`
125			`do_nop <= 1;`
126			`else`
127			`do_nop <= 0;`
128
129			`if ((ref_req == 1 \| refresh == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0 // refresh`
130			`& do_reada == 0 & do_writea == 0)`
131			`do_refresh <= 1;`
132			`else`
133			`do_refresh <= 0;`
134
135			`if ((reada == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (ref_req == 0)) // reada`
136			`do_reada <= 1;`
137			`else`
138			`do_reada <= 0;`
139
140			`if ((writea == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (ref_req == 0)) // writea`
141			`begin`
142			`do_writea <= 1;`
143			`do_writea1 <= 1;`
144			`end`
145			`else`
146			`begin`
147			`do_writea <= 0;`
148			`do_writea1 <= 0;`
149			`end`
150			`if ((preacharge == 1) & (command_done == 0) & (do_preacharge == 0)) // preacharge`
151			`do_preacharge <= 1;`
152			`else`
153			`do_preacharge <= 0;`
154
155			`if ((load_mod == 1) & (command_done == 0) & (do_load_mod == 0)) // LOADMODE`
156			`do_load_mod <= 1;`
157			`else`
158			`do_load_mod <= 0;`
159
160			`// set command_delay shift register and command_done flag`
161			`// The command delay shift register is a timer that is used to ensure that`
162			`// the SDRAM devices have had sufficient time to finish the last command.`
163
164			`if ((do_refresh == 1) \| (do_reada == 1) \| (do_writea == 1) \| (do_preacharge == 1)`
165			`\| (do_load_mod))`
166			`begin`
167			`command_delay <= 8'b11111111;`
168			`command_done <= 1;`
169			`rw_flag <= do_reada;`
170
171			`end`
172
173			`else`
174			`begin`
175			`command_done <= command_delay[0]; // the command_delay shift operation`
176			`command_delay[6:0] <= command_delay[7:1];`
177			`command_delay[7] <= 0;`
178			`end`
179
180
181			`// start additional timer that is used for the refresh, writea, reada commands`
182			`if (command_delay[0] == 0 & command_done == 1)`
183			`begin`
184			`// rp_shift <= 4'b1111;`
185			`rp_shift <= ref_dur;`
186			`rp_done <= 1;`
187			`end`
188			`else`
189			`begin`
190			`rp_done <= rp_shift[0];`
191			`rp_shift[2:0] <= rp_shift[3:1];`
192			`rp_shift[3] <= 0;`
193			`end`
194			`end`
195			`end`
196
197
198
199
200			`endmodule`

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[/] [embedded_risc/] [trunk/] [Verilog/] [cmd_detector.v] - Blame information for rev 27