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[/] [embedded_risc/] [trunk/] [Verilog/] [cmd_generator.v] - Blame information for rev 27

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1 26 hosseinami
/*********************************************************
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 MODULE:                Sub Level SDRAM Command Genrator
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 FILE NAME:     cmd_generator.v
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 VERSION:       1.0
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 DATE:          April 28th, 2002
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 AUTHOR:                Hossein Amidi
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 COMPANY:
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 CODE TYPE:     Register Transfer Level
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 DESCRIPTION:   This module is the sub level RTL code of SDRAM Controller ASIC verilog
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 code. It will generate the SDRAM control signals.
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 Hossein Amidi
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 (C) April 2002
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*********************************************************/
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// DEFINES
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`timescale 1ns / 10ps
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module cmd_generator(// Input
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                                                        reset,
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                                                        clk0,
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                                                        do_reada,
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                                                        do_writea,
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                                                        do_preacharge,
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                                                        do_rw,
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                                                        rowaddr,
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                                                        coladdr,
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                                                        bankaddr,
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                                                        page_mod,
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                                                        do_load_mod,
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                                                        do_refresh,
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                                                        caddr,
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                                                        do_nop,
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                                                        rw_flag,
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                                                        oe4,
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                                                        // Output
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                                                        sadd,
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                                                        ba,
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                                                        cs,
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                                                        ras,
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                                                        cas,
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                                                        we,
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                                                        cke
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                                                        );
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// Parameter
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`include        "parameter.v"
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// Input
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input reset;
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input clk0;
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input do_reada;
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input do_writea;
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input do_preacharge;
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input do_rw;
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input [row_size - 1:0]        rowaddr;
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input [col_size - 1:0]        coladdr;
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input [bank_size - 1:0]       bankaddr;
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input page_mod;
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input do_load_mod;
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input do_refresh;
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input [padd_size - 1 : 0]caddr;
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input do_nop;
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input rw_flag;
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input oe4;
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// Output
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output [add_size - 1 : 0]sadd;
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output [ba_size - 1 : 0]ba;
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output [cs_size - 1 : 0]cs;
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output ras;
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output cas;
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output we;
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output cke;
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// Internal wire and reg signals
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wire reset;
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wire clk0;
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wire do_reada;
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wire do_writea;
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wire do_preacharge;
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wire do_rw;
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wire [row_size - 1:0]        rowaddr;
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wire [col_size - 1:0]        coladdr;
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wire [bank_size - 1:0]       bankaddr;
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wire page_mod;
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wire do_load_mod;
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wire do_refresh;
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wire [padd_size - 1 : 0]caddr;
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wire do_nop;
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wire rw_flag;
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wire oe4;
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reg [add_size - 1 : 0]sadd;
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reg [ba_size - 1 : 0]ba;
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reg [cs_size - 1 : 0]cs;
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reg ras;
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reg cas;
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reg we;
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reg cke;
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// Assignment
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// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
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// 
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always @(posedge reset or posedge clk0)
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begin
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        if (reset == 1'b1) begin
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                sadd <= 0;
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                ba   <= 0;
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                cs   <= 1;
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                ras  <= 1;
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                cas  <= 1;
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                we   <= 1;
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                cke  <= 0;
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        end
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        else begin
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                cke  <= 1;
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// Generate sadd        
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                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
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                        sadd <= rowaddr;
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                else if ((do_rw == 1) | (do_preacharge == 1))
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                        sadd[10] <= !page_mod;              // set sadd[10] for autopreacharge read/write or for a preacharge all command
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                else                                        // don't set it if the controller is in page mode.           
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                        sadd <= coladdr;                 // else alway present column address
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                if (do_preacharge == 1 | do_load_mod == 1)
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                        ba <= 0;                       // Set ba=0 if performing a preacharge or load_mod command
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                else
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                        ba <= bankaddr[1:0];           // else set it with the appropriate address bits
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                if (do_refresh == 1 | do_preacharge == 1 | do_load_mod == 1)
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                        cs <= 0;                                    // Select both chip selects if performing
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                else                                                  // refresh, preacharge(all) or load_mod
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                begin
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                        cs[0] <= caddr[padd_size - 1];                   // else set the chip selects based off of the
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                        cs[1] <= ~caddr[padd_size - 1];                  // msb address bit
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                end
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//Generate the appropriate logic levels on ras, cas, and we
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//depending on the issued command.
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//              
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                if (do_nop == 1) begin                                          // No Operation: RAS=1, CAS=1, WE=1
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                        ras <= 1;
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                        cas <= 1;
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                        we  <= 1;
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                end
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                     else if (do_refresh == 1) begin                        // refresh: S=00, RAS=0, CAS=0, WE=1
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                        ras <= 0;
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                        cas <= 0;
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                        we  <= 1;
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                end
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                else if ((do_preacharge == 1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
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                        ras <= 1;
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                        cas <= 1;
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                        we  <= 0;
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                end
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                else if (do_preacharge == 1) begin                 // preacharge All: S=00, RAS=0, CAS=1, WE=0
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                        ras <= 0;
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                        cas <= 1;
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                        we  <= 0;
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                end
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                else if (do_load_mod == 1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
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                        ras <= 0;
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                        cas <= 0;
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                        we  <= 0;
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                end
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                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
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                        ras <= 0;
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                        cas <= 1;
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                        we  <= 1;
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                end
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                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
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                        ras <= 1;
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                        cas <= 0;
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                        we  <= rw_flag;
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                end
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                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
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                        ras <= 1;
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                        cas <= 1;
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                        we  <= 1;
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                end
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        end
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end
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endmodule

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