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[/] [embedded_risc/] [trunk/] [Verilog/] [flash_ctrl.v] - Blame information for rev 26

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/*********************************************************
 MODULE:                Sub Level UART Device
 
 FILE NAME:     uart.v
 VERSION:       1.0
 DATE:          May 14th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the top level RTL code of UART verilog code.
 
 It will instantiate the following blocks in the ASIC:
 
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
// TOP MODULE
module flash_ctrl(// Inputs
                                                reset,
                                                clk0,
                                                flash_host_addr,
                                                flash_host_cmd,
                                                flash_host_dataout,
                                                flash_datain,
                                                // Outputs
                                                flash_host_datain,
                                                flash_cle,
                                                flash_ale,
                                                flash_ce,
                                                flash_re,
                                                flash_we,
                                                flash_wp,
                                                flash_rb,
                                                flash_irq,
                                                flash_dataout
                                                );
 
 
// Parameter
`include        "parameter.v"
 
// Inputs
input reset;
input clk0;
input [padd_size - 1 : 0]flash_host_addr;
input [cmd_size - 1 : 0]flash_host_cmd;
input [data_size - 1 : 0]flash_host_dataout;
input [flash_size - 1 : 0]flash_datain;
 
// Outputs
output [data_size - 1 : 0]flash_host_datain;
output flash_cle;
output flash_ale;
output flash_ce;
output flash_re;
output flash_we;
output flash_wp;
output flash_rb;
output flash_irq;
output [flash_size - 1 : 0]flash_dataout;
 
 
// Signal Declarations
wire reset;
wire clk0;
wire [padd_size - 1 : 0]flash_host_addr;
wire [cmd_size - 1 : 0]flash_host_cmd;
wire [data_size - 1 : 0]flash_host_dataout;
wire [flash_size - 1 : 0]flash_datain;
 
wire [data_size - 1 : 0]flash_host_datain;
reg flash_cle;
reg flash_ale;
reg flash_ce;
reg flash_re;
reg flash_we;
reg flash_wp;
reg flash_rb;
reg flash_irq;
reg [flash_size - 1 : 0]flash_dataout;
 
 
// Internal Registers
reg [Byte_size - 1 : 0]flash_reg_dataout;
 
// Assignment statments
assign flash_host_datain = flash_reg_dataout;
 
/***************** Internal Register of Uart configuration *******************/
reg [flash_reg_width - 1 : 0] flash_register [flash_reg_depth - 1 : 0];
 
 
// Circuit for internal Register
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                flash_reg_dataout <= 8'h0;
                flash_register[0] <= 8'h0;
                flash_register[1] <= 8'h0;
                flash_register[2] <= 8'h0;
                flash_register[3] <= 8'h0;
                flash_register[4] <= 8'h0;
                flash_register[5] <= 8'h0;
                flash_register[6] <= 8'h0;
                flash_register[7] <= 8'h0;
        end
        else
        begin
                if(flash_host_cmd == 3'b010)
                begin
                        case(flash_host_addr)
                                24'h080008: flash_register[0] <= flash_host_dataout;
                                24'h080009: flash_register[1] <= flash_host_dataout;
                                24'h08000A: flash_register[2] <= flash_host_dataout;
                                24'h08000B: flash_register[3] <= flash_host_dataout;
                                24'h08000C: flash_register[4] <= flash_host_dataout;
                                24'h08000D: flash_register[5] <= flash_host_dataout;
                                24'h08000E: flash_register[6] <= flash_host_dataout;
                                24'h08000F: flash_register[7] <= flash_host_dataout;
                        endcase
                end
                else
                if(flash_host_cmd == 3'b001)
                begin
                        case(flash_host_addr)
                                24'h080008: flash_reg_dataout <= flash_register[0];
                                24'h080009: flash_reg_dataout <= flash_register[1];
                                24'h08000A: flash_reg_dataout <= flash_register[2];
                                24'h08000B: flash_reg_dataout <= flash_register[3];
                                24'h08000C: flash_reg_dataout <= flash_register[4];
                                24'h08000D: flash_reg_dataout <= flash_register[5];
                                24'h08000E: flash_reg_dataout <= flash_register[6];
                                24'h08000F: flash_reg_dataout <= flash_register[7];
                        endcase
                end
        end
 
end
 
 
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                flash_cle <= 1'b0;
                flash_ale <= 1'b0;
                flash_ce <= 1'b0;
                flash_re <= 1'b0;
                flash_we <= 1'b0;
                flash_wp <= 1'b0;
                flash_rb <= 1'b0;
                flash_irq <= 1'b0;
                flash_dataout <= 8'h0;
        end
        else
        begin
                flash_cle <= flash_host_addr[7];
                flash_ale <= flash_host_addr[0] & flash_host_cmd[0];
                flash_ce <= flash_host_addr[1] & flash_host_cmd[1];
                flash_re <= flash_host_addr[2] & flash_host_cmd[2];
                flash_we <= flash_host_addr[3];
                flash_wp <= flash_host_addr[4];
                flash_rb <= flash_host_addr[5];
                flash_irq <= flash_host_addr[6];
                flash_dataout <= flash_datain;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level UART Device`
3
4			`FILE NAME: uart.v`
5			`VERSION: 1.0`
6			`DATE: May 14th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the top level RTL code of UART verilog code.`
12
13			`It will instantiate the following blocks in the ASIC:`
14
15
16			`Hossein Amidi`
17			`(C) April 2002`
18
19			`*********************************************************/`
20
21			`// DEFINES`
22			`timescale 1ns / 10ps
23
24			`// TOP MODULE`
25			`module flash_ctrl(// Inputs`
26			`reset,`
27			`clk0,`
28			`flash_host_addr,`
29			`flash_host_cmd,`
30			`flash_host_dataout,`
31			`flash_datain,`
32			`// Outputs`
33			`flash_host_datain,`
34			`flash_cle,`
35			`flash_ale,`
36			`flash_ce,`
37			`flash_re,`
38			`flash_we,`
39			`flash_wp,`
40			`flash_rb,`
41			`flash_irq,`
42			`flash_dataout`
43			`);`
44
45
46			`// Parameter`
47			`include "parameter.v"
48
49			`// Inputs`
50			`input reset;`
51			`input clk0;`
52			`input [padd_size - 1 : 0]flash_host_addr;`
53			`input [cmd_size - 1 : 0]flash_host_cmd;`
54			`input [data_size - 1 : 0]flash_host_dataout;`
55			`input [flash_size - 1 : 0]flash_datain;`
56
57			`// Outputs`
58			`output [data_size - 1 : 0]flash_host_datain;`
59			`output flash_cle;`
60			`output flash_ale;`
61			`output flash_ce;`
62			`output flash_re;`
63			`output flash_we;`
64			`output flash_wp;`
65			`output flash_rb;`
66			`output flash_irq;`
67			`output [flash_size - 1 : 0]flash_dataout;`
68
69
70			`// Signal Declarations`
71			`wire reset;`
72			`wire clk0;`
73			`wire [padd_size - 1 : 0]flash_host_addr;`
74			`wire [cmd_size - 1 : 0]flash_host_cmd;`
75			`wire [data_size - 1 : 0]flash_host_dataout;`
76			`wire [flash_size - 1 : 0]flash_datain;`
77
78			`wire [data_size - 1 : 0]flash_host_datain;`
79			`reg flash_cle;`
80			`reg flash_ale;`
81			`reg flash_ce;`
82			`reg flash_re;`
83			`reg flash_we;`
84			`reg flash_wp;`
85			`reg flash_rb;`
86			`reg flash_irq;`
87			`reg [flash_size - 1 : 0]flash_dataout;`
88
89
90			`// Internal Registers`
91			`reg [Byte_size - 1 : 0]flash_reg_dataout;`
92
93			`// Assignment statments`
94			`assign flash_host_datain = flash_reg_dataout;`
95
96			`/*************** Internal Register of Uart configuration *****************/`
97			`reg [flash_reg_width - 1 : 0] flash_register [flash_reg_depth - 1 : 0];`
98
99
100			`// Circuit for internal Register`
101			`always @(posedge reset or posedge clk0)`
102			`begin`
103			`if(reset == 1'b1)`
104			`begin`
105			`flash_reg_dataout <= 8'h0;`
106			`flash_register[0] <= 8'h0;`
107			`flash_register[1] <= 8'h0;`
108			`flash_register[2] <= 8'h0;`
109			`flash_register[3] <= 8'h0;`
110			`flash_register[4] <= 8'h0;`
111			`flash_register[5] <= 8'h0;`
112			`flash_register[6] <= 8'h0;`
113			`flash_register[7] <= 8'h0;`
114			`end`
115			`else`
116			`begin`
117			`if(flash_host_cmd == 3'b010)`
118			`begin`
119			`case(flash_host_addr)`
120			`24'h080008: flash_register[0] <= flash_host_dataout;`
121			`24'h080009: flash_register[1] <= flash_host_dataout;`
122			`24'h08000A: flash_register[2] <= flash_host_dataout;`
123			`24'h08000B: flash_register[3] <= flash_host_dataout;`
124			`24'h08000C: flash_register[4] <= flash_host_dataout;`
125			`24'h08000D: flash_register[5] <= flash_host_dataout;`
126			`24'h08000E: flash_register[6] <= flash_host_dataout;`
127			`24'h08000F: flash_register[7] <= flash_host_dataout;`
128			`endcase`
129			`end`
130			`else`
131			`if(flash_host_cmd == 3'b001)`
132			`begin`
133			`case(flash_host_addr)`
134			`24'h080008: flash_reg_dataout <= flash_register[0];`
135			`24'h080009: flash_reg_dataout <= flash_register[1];`
136			`24'h08000A: flash_reg_dataout <= flash_register[2];`
137			`24'h08000B: flash_reg_dataout <= flash_register[3];`
138			`24'h08000C: flash_reg_dataout <= flash_register[4];`
139			`24'h08000D: flash_reg_dataout <= flash_register[5];`
140			`24'h08000E: flash_reg_dataout <= flash_register[6];`
141			`24'h08000F: flash_reg_dataout <= flash_register[7];`
142			`endcase`
143			`end`
144			`end`
145
146			`end`
147
148
149			`always @(posedge reset or posedge clk0)`
150			`begin`
151			`if(reset == 1'b1)`
152			`begin`
153			`flash_cle <= 1'b0;`
154			`flash_ale <= 1'b0;`
155			`flash_ce <= 1'b0;`
156			`flash_re <= 1'b0;`
157			`flash_we <= 1'b0;`
158			`flash_wp <= 1'b0;`
159			`flash_rb <= 1'b0;`
160			`flash_irq <= 1'b0;`
161			`flash_dataout <= 8'h0;`
162			`end`
163			`else`
164			`begin`
165			`flash_cle <= flash_host_addr[7];`
166			`flash_ale <= flash_host_addr[0] & flash_host_cmd[0];`
167			`flash_ce <= flash_host_addr[1] & flash_host_cmd[1];`
168			`flash_re <= flash_host_addr[2] & flash_host_cmd[2];`
169			`flash_we <= flash_host_addr[3];`
170			`flash_wp <= flash_host_addr[4];`
171			`flash_rb <= flash_host_addr[5];`
172			`flash_irq <= flash_host_addr[6];`
173			`flash_dataout <= flash_datain;`
174			`end`
175			`end`
176
177			`endmodule`

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[/] [embedded_risc/] [trunk/] [Verilog/] [flash_ctrl.v] - Blame information for rev 26