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hosseinami |
/**********************************************************
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MODULE: Sub Level Least Recently Used Data Cache
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FILE NAME: lru_data_cache.v
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VERSION: 1.0
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DATE: May 7th, 2002
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AUTHOR: Hossein Amidi
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COMPANY:
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CODE TYPE: Register Transfer Level
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DESCRIPTION: This module is the top level RTL code of LRU
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Data Cache verilog code.
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It will instantiate the following blocks in the ASIC:
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1) Data Cache Way 0
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2) Data Cache Way 1
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3) Data Cache Way 2
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4) Data Cache Way 3
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Hossein Amidi
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(C) April 2002
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*********************************************************/
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// DEFINES
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`timescale 1ns / 10ps
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// TOP MODULE
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module lru_data_cache(// Inputs
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reset,
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clk0,
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cache_host_addr,
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cache_host_cmd,
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cache_request,
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cache_host_datain,
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cache_bus_grant,
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cache_datain,
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// Outputs
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cache_host_dataout,
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cache_hit,
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cache_miss,
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cache_bus_request,
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cache_addr,
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cache_cmd,
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cache_dataout
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);
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// Parameter
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`include "parameter.v"
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// Inputs
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input reset;
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input clk0;
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input [padd_size - 1 : 0]cache_host_addr;
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input [cmd_size - 1 : 0]cache_host_cmd;
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input cache_request;
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input [data_size - 1 : 0]cache_host_datain;
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input cache_bus_grant;
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input [data_size - 1 : 0]cache_datain;
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// Outputs
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output [data_size - 1 : 0]cache_host_dataout;
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output cache_hit;
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output cache_miss;
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output cache_bus_request;
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output [padd_size - 1 : 0]cache_addr;
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output [cmd_size - 1 : 0]cache_cmd;
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output [data_size - 1 : 0]cache_dataout;
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// Signal Declarations
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wire reset;
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wire clk0;
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wire [padd_size - 1 : 0]cache_host_addr;
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wire [cmd_size - 1 : 0]cache_host_cmd;
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wire cache_request;
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wire [data_size - 1 : 0]cache_host_datain;
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wire cache_bus_grant;
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wire [data_size - 1 : 0]cache_datain;
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reg [data_size - 1 : 0]cache_host_dataout;
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reg cache_hit;
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reg cache_miss;
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wire cache_bus_request;
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reg [padd_size - 1 : 0]cache_addr;
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reg [cmd_size - 1 : 0]cache_cmd;
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reg [data_size - 1 : 0]cache_dataout;
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wire [cache_line_size - 1 : 0]data_cache_datain_way0;
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wire [cache_line_size - 1 : 0]data_cache_datain_way1;
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wire [cache_line_size - 1 : 0]data_cache_datain_way2;
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wire [cache_line_size - 1 : 0]data_cache_datain_way3;
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wire [cache_line_size - 1 : 0]data_cache_dataout_way0;
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wire [cache_line_size - 1 : 0]data_cache_dataout_way1;
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wire [cache_line_size - 1 : 0]data_cache_dataout_way2;
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wire [cache_line_size - 1 : 0]data_cache_dataout_way3;
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wire cache_wr;
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reg [cache_valid - 1 : 0]valid0;
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reg [cache_valid - 1 : 0]valid1;
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reg [cache_valid - 1 : 0]valid2;
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reg [cache_valid - 1 : 0]valid3;
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wire [cache_tag - 1 : 0]tag;
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wire [cache_tag - 1 : 0]read_tag0;
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wire [cache_tag - 1 : 0]read_tag1;
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wire [cache_tag - 1 : 0]read_tag2;
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wire [cache_tag - 1 : 0]read_tag3;
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/********* Internal Register of Data cache configuration *********/
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reg [cache_reg_width - 1 : 0] cache_register [cache_reg_depth - 1 : 0];
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// Assignment statments
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assign cache_bus_request = cache_miss;
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assign cache_wr = (cache_host_cmd == 010) ? 1'b1 : 1'b0;
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assign tag = cache_host_addr[23:5];
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assign read_tag0 = data_cache_dataout_way0[50:32];
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assign read_tag1 = data_cache_dataout_way1[50:32];
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assign read_tag2 = data_cache_dataout_way2[50:32];
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assign read_tag3 = data_cache_dataout_way3[50:32];
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assign data_cache_datain_way0 = ({valid0,tag,cache_datain});
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assign data_cache_datain_way1 = ({valid1,tag,cache_datain});
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assign data_cache_datain_way2 = ({valid2,tag,cache_datain});
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assign data_cache_datain_way3 = ({valid3,tag,cache_datain});
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/********************************** Sub Level Instantiation *********************************/
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data_cache_way0 data_cache_way0_0 (// Input
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.A(cache_host_addr[4:0]),
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.CLK(clk0),
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.D(data_cache_datain_way0),
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.WE(cache_wr),
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.SPO(data_cache_dataout_way0));
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data_cache_way1 data_cache_way1_0 (// Input
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.A(cache_host_addr[4:0]),
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.CLK(clk0),
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.D(data_cache_datain_way1),
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.WE(cache_wr),
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.SPO(data_cache_dataout_way1));
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data_cache_way2 data_cache_way2_0 (// Input
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.A(cache_host_addr[4:0]),
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.CLK(clk0),
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.D(data_cache_datain_way2),
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.WE(cache_wr),
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.SPO(data_cache_dataout_way2));
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data_cache_way3 data_cache_way3_0 (// Input
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.A(cache_host_addr[4:0]),
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.CLK(clk0),
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.D(data_cache_datain_way3),
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.WE(cache_wr),
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.SPO(data_cache_dataout_way3));
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// Generate the LRU talbe
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always @(posedge reset or posedge clk0)
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begin
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if(reset == 1'b1)
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begin
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valid0 <= 2'b00;
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valid1 <= 2'b00;
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valid2 <= 2'b10;
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valid3 <= 2'b10;
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end
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else
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if((cache_wr == 1'b1) && (valid0 == 2'b00))
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valid0 <= 2'b01;
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else
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if((cache_wr == 1'b1) && (valid0 == 2'b01))
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valid0 <= 2'b00;
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else
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if((cache_wr == 1'b1) && (valid1 == 2'b00))
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valid1 <= 2'b01;
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else
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if((cache_wr == 1'b1) && (valid1 == 2'b01))
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valid1 <= 2'b00;
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else
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if((cache_wr == 1'b1) && (valid2 == 2'b10))
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valid2 <= 2'b11;
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else
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if((cache_wr == 1'b1) && (valid2 == 2'b11))
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valid2 <= 2'b10;
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else
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if((cache_wr == 1'b1) && (valid3 == 2'b10))
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valid3 <= 2'b11;
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else
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if((cache_wr == 1'b1) && (valid3 == 2'b11))
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valid3 <= 2'b10;
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end
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// Check for cache way validity, if matches generate the cache hit signal
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// else generate cache miss signal
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always @(posedge reset or posedge clk0)
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begin
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if(reset == 1'b1)
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cache_dataout <= 32'h0;
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else
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if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag0 == cache_host_addr[23:5]))
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begin
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cache_hit <= 1'b1;
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cache_dataout <= data_cache_dataout_way0[31:0];
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end
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else
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if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag1 == cache_host_addr[23:5]))
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begin
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cache_hit <= 1'b1;
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cache_dataout <= data_cache_dataout_way1[31:0];
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end
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else
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if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag2 == cache_host_addr[23:5]))
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begin
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cache_hit <= 1'b1;
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cache_dataout <= data_cache_dataout_way2[31:0];
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end
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else
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if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag3 == cache_host_addr[23:5]))
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begin
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cache_hit <= 1'b1;
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cache_dataout <= data_cache_dataout_way3[31:0];
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end
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else
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if((cache_request == 1'b1) && (cache_host_cmd == 001))
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begin
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cache_miss <= 1'b1;
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cache_hit <= 1'b0;
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cache_dataout <= 32'h0;
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end
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else
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begin
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cache_miss <= 1'b0;
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cache_hit <= 1'b0;
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cache_dataout <= 32'h0;
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end
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end
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// Access to internal register by CPU address and command signals (write/read)
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always @(posedge reset or posedge clk0)
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begin
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if(reset == 1'b1)
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begin
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cache_host_dataout <= 32'h0;
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cache_register[0] <= 32'h0;
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cache_register[1] <= 32'h0;
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cache_register[2] <= 32'h0;
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cache_register[3] <= 32'h0;
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cache_register[4] <= 32'h0;
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cache_register[5] <= 32'h0;
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cache_register[6] <= 32'h0;
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cache_register[7] <= 32'h0;
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end
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else
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begin
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if(cache_host_cmd == 3'b010) // Write from Host to Cache internal Registers
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begin
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case (cache_host_addr)
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24'h080010: cache_register[0] <= cache_host_datain; // Status Register
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24'h080011: cache_register[1] <= cache_host_datain; // Read Master Start Address
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24'h080012: cache_register[2] <= cache_host_datain; // Write Master Start Address
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24'h080013: cache_register[3] <= cache_host_datain; // Length in Bytes
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24'h080014: cache_register[4] <= cache_host_datain; // Reserved
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24'h080015: cache_register[5] <= cache_host_datain; // Reserved
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24'h080016: cache_register[6] <= cache_host_datain; // Control
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24'h080017: cache_register[7] <= cache_host_datain; // Reserved
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endcase
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end
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else
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if(cache_host_cmd == 3'b001) // Read from Cache internal Registers to Host
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begin
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case (cache_host_addr)
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24'h080010: cache_host_dataout <= cache_register[0];
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24'h080011: cache_host_dataout <= cache_register[1];
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24'h080012: cache_host_dataout <= cache_register[2];
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24'h080013: cache_host_dataout <= cache_register[3];
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24'h080014: cache_host_dataout <= cache_register[4];
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24'h080015: cache_host_dataout <= cache_register[5];
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24'h080016: cache_host_dataout <= cache_register[6];
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24'h080017: cache_host_dataout <= cache_register[7];
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endcase
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end
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end
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end
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always @(posedge reset or posedge clk0)
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begin
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if(reset == 1'b1)
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begin
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cache_addr <= 24'h0;
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cache_cmd <= 3'h0;
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end
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else
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begin
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cache_addr <= cache_bus_grant & cache_host_addr;
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cache_cmd <= cache_bus_grant & cache_host_cmd;
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end
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end
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endmodule
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