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/**********************************************************
 MODULE:                Sub Level Least Recently Used Instruction Cache
 
 FILE NAME:     lru_instruction_cache.v
 VERSION:       1.0
 DATE:          May 7th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the top level RTL code of LRU
 instruction Cache verilog code.
 
 It will instantiate the following blocks in the ASIC:
 
 1)     Instruction Cache Way 0
 2)     Instruction Cache Way 1
 3)     Instruction Cache Way 2
 4)     Instruction Cache Way 3
 
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
// TOP MODULE
module lru_instruction_cache(// Inputs
                                                reset,
                                                clk0,
                                                cache_host_addr,
                                                cache_host_cmd,
                                                cache_request,
                                                cache_host_datain,
                                                cache_bus_grant,
                                                cache_datain,
                                                // Outputs
                                                cache_host_dataout,
                                                cache_hit,
                                                cache_miss,
                                                cache_bus_request,
                                                cache_addr,
                                                cache_cmd,
                                                cache_dataout
                                                );
 
 
// Parameter
`include        "parameter.v"
 
// Inputs
input reset;
input clk0;
input [padd_size - 1 : 0]cache_host_addr;
input [cmd_size  - 1 : 0]cache_host_cmd;
input cache_request;
input [data_size - 1 : 0]cache_host_datain;
input cache_bus_grant;
input [data_size - 1 : 0]cache_datain;
 
// Outputs
output [data_size - 1 : 0]cache_host_dataout;
output cache_hit;
output cache_miss;
output cache_bus_request;
output [padd_size - 1 : 0]cache_addr;
output [cmd_size  - 1 : 0]cache_cmd;
output [data_size - 1 : 0]cache_dataout;
 
// Signal Declarations
wire reset;
wire clk0;
wire [padd_size - 1 : 0]cache_host_addr;
wire [cmd_size  - 1 : 0]cache_host_cmd;
wire cache_request;
wire [data_size - 1 : 0]cache_host_datain;
wire cache_bus_grant;
wire [data_size - 1 : 0]cache_datain;
 
reg [data_size - 1 : 0]cache_host_dataout;
reg cache_hit;
reg cache_miss;
wire cache_bus_request;
reg [padd_size - 1 : 0]cache_addr;
reg [cmd_size  - 1 : 0]cache_cmd;
reg [data_size - 1 : 0]cache_dataout;
 
wire [cache_line_size - 1 : 0]instruction_cache_datain_way0;
wire [cache_line_size - 1 : 0]instruction_cache_datain_way1;
wire [cache_line_size - 1 : 0]instruction_cache_datain_way2;
wire [cache_line_size - 1 : 0]instruction_cache_datain_way3;
wire [cache_line_size - 1 : 0]instruction_cache_dataout_way0;
wire [cache_line_size - 1 : 0]instruction_cache_dataout_way1;
wire [cache_line_size - 1 : 0]instruction_cache_dataout_way2;
wire [cache_line_size - 1 : 0]instruction_cache_dataout_way3;
 
wire cache_wr;
reg  [cache_valid - 1 : 0]valid0;
reg  [cache_valid - 1 : 0]valid1;
reg  [cache_valid - 1 : 0]valid2;
reg  [cache_valid - 1 : 0]valid3;
wire [cache_tag - 1 : 0]tag;
wire [cache_tag - 1 : 0]read_tag0;
wire [cache_tag - 1 : 0]read_tag1;
wire [cache_tag - 1 : 0]read_tag2;
wire [cache_tag - 1 : 0]read_tag3;
 
wire [cache_valid - 1 : 0]wvalid0;
wire [cache_valid - 1 : 0]wvalid1;
wire [cache_valid - 1 : 0]wvalid2;
wire [cache_valid - 1 : 0]wvalid3;
 
 
/********* Internal Register of Instruction cache configuration *********/
reg [cache_reg_width - 1 : 0] cache_register [cache_reg_depth - 1 : 0];
 
 
 
// Assignment statments
assign cache_bus_request = cache_miss;
assign cache_wr = (cache_host_cmd == 010) ? 1'b1 : 1'b0;
 
assign tag = cache_host_addr[23:5];
assign read_tag0 = instruction_cache_dataout_way0[50:32];
assign read_tag1 = instruction_cache_dataout_way1[50:32];
assign read_tag2 = instruction_cache_dataout_way2[50:32];
assign read_tag3 = instruction_cache_dataout_way3[50:32];
assign instruction_cache_datain_way0 = ({wvalid0,tag,cache_datain});
assign instruction_cache_datain_way1 = ({wvalid1,tag,cache_datain});
assign instruction_cache_datain_way2 = ({wvalid2,tag,cache_datain});
assign instruction_cache_datain_way3 = ({wvalid3,tag,cache_datain});
 
assign wvalid0 = valid0;
assign wvalid1 = valid1;
assign wvalid2 = valid2;
assign wvalid3 = valid3;
 
/********************************** Sub Level Instantiation *********************************/
 
 
instruction_cache_way0 instruction_cache_way0_0 (// Input
                                                                                                                                .A(cache_host_addr[4:0]),
                                                                                                                                .CLK(clk0),
                                                                                                                                .D(instruction_cache_datain_way0),
                                                                                                                                .WE(cache_wr),
                                                                                                                                .SPO(instruction_cache_dataout_way0));
 
 
instruction_cache_way1 instruction_cache_way1_0 (// Input
                                                                                                                                .A(cache_host_addr[4:0]),
                                                                                                                                .CLK(clk0),
                                                                                                                                .D(instruction_cache_datain_way1),
                                                                                                                                .WE(cache_wr),
                                                                                                                                .SPO(instruction_cache_dataout_way1));
 
 
instruction_cache_way2 instruction_cache_way2_0 (// Input
                                                                                                                                .A(cache_host_addr[4:0]),
                                                                                                                                .CLK(clk0),
                                                                                                                                .D(instruction_cache_datain_way2),
                                                                                                                                .WE(cache_wr),
                                                                                                                                .SPO(instruction_cache_dataout_way2));
 
 
instruction_cache_way3 instruction_cache_way3_0 (// Input
                                                                                                                                .A(cache_host_addr[4:0]),
                                                                                                                                .CLK(clk0),
                                                                                                                                .D(instruction_cache_datain_way3),
                                                                                                                                .WE(cache_wr),
                                                                                                                                .SPO(instruction_cache_dataout_way3));
 
 
 
// Generate the LRU talbe
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                valid0 <= 2'b00;
                valid1 <= 2'b00;
                valid2 <= 2'b10;
                valid3 <= 2'b10;
        end
        else
        begin
                if((cache_wr == 1'b1) && (wvalid0 == 2'b00))
                        valid0 <= 2'b01;
                else
                if((cache_wr == 1'b1) && (wvalid0 == 2'b01))
                        valid0 <= 2'b00;
                else
                if((cache_wr == 1'b1) && (wvalid1 == 2'b00))
                        valid1 <= 2'b01;
                else
                if((cache_wr == 1'b1) && (wvalid1 == 2'b01))
                        valid1 <= 2'b00;
                else
                if((cache_wr == 1'b1) && (wvalid2 == 2'b10))
                        valid2 <= 2'b11;
                else
                if((cache_wr == 1'b1) && (wvalid2 == 2'b11))
                        valid2 <= 2'b10;
                else
                if((cache_wr == 1'b1) && (wvalid3 == 2'b10))
                        valid3 <= 2'b11;
                else
                if((cache_wr == 1'b1) && (wvalid3 == 2'b11))
                        valid3 <= 2'b10;
        end
end
 
 
// Check for cache way validity, if matches generate the cache hit signal
// else generate cache miss signal
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
                cache_dataout <= 32'h0;
        else
        if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag0 == cache_host_addr[23:5]))
        begin
                cache_hit <= 1'b1;
                cache_dataout <= instruction_cache_dataout_way0[31:0];
        end
        else
        if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag1 == cache_host_addr[23:5]))
        begin
                cache_hit <= 1'b1;
                cache_dataout <= instruction_cache_dataout_way1[31:0];
        end
        else
        if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag2 == cache_host_addr[23:5]))
        begin
                cache_hit <= 1'b1;
                cache_dataout <= instruction_cache_dataout_way2[31:0];
        end
        else
        if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag3 == cache_host_addr[23:5]))
        begin
                cache_hit <= 1'b1;
                cache_dataout <= instruction_cache_dataout_way3[31:0];
        end
        else
        if((cache_request == 1'b1) && (cache_host_cmd == 001))
        begin
                cache_miss <= 1'b1;
                cache_hit  <= 1'b0;
                cache_dataout <= 32'h0;
        end
        else
        begin
                cache_miss <= 1'b0;
                cache_hit  <= 1'b0;
                cache_dataout <= 32'h0;
        end
end
 
 
// Access to internal register by CPU address and command signals (write/read)
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                cache_host_dataout <= 32'h0;
                cache_register[0] <= 32'h0;
                cache_register[1] <= 32'h0;
                cache_register[2] <= 32'h0;
                cache_register[3] <= 32'h0;
                cache_register[4] <= 32'h0;
                cache_register[5] <= 32'h0;
                cache_register[6] <= 32'h0;
                cache_register[7] <= 32'h0;
        end
        else
        begin
                if(cache_host_cmd == 3'b010)    // Write from Host to Cache internal Registers
                begin
                        case (cache_host_addr)
 
                                24'h080018:     cache_register[0] <= cache_host_datain;  // Status Register
                                24'h080019:     cache_register[1] <= cache_host_datain; // Read Master Start Address
                                24'h08001A:     cache_register[2] <= cache_host_datain; // Write Master Start Address
                                24'h08001B:     cache_register[3] <= cache_host_datain; // Length in Bytes
                                24'h08001C:     cache_register[4] <= cache_host_datain; // Reserved
                                24'h08001D:     cache_register[5] <= cache_host_datain;         // Reserved
                                24'h08001E:     cache_register[6] <= cache_host_datain; // Control
                                24'h08001F:     cache_register[7] <= cache_host_datain;         // Reserved
                        endcase
                end
                else
                if(cache_host_cmd == 3'b001)    // Read from Cache internal Registers to Host
                begin
                        case (cache_host_addr)
 
                                24'h080018:     cache_host_dataout <= cache_register[0];
                                24'h080019:     cache_host_dataout <= cache_register[1];
                                24'h08001A:     cache_host_dataout <= cache_register[2];
                                24'h08001B:     cache_host_dataout <= cache_register[3];
                                24'h08001C:     cache_host_dataout <= cache_register[4];
                                24'h08001D:     cache_host_dataout <= cache_register[5];
                                24'h08001E:     cache_host_dataout <= cache_register[6];
                                24'h08001F:     cache_host_dataout <= cache_register[7];
                        endcase
                end
        end
end
 
 
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                cache_addr <= 24'h0;
                cache_cmd <= 3'h0;
        end
        else
        begin
                cache_addr <= cache_bus_grant & cache_host_addr;
                cache_cmd <= cache_bus_grant & cache_host_cmd;
        end
end
 
endmodule

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Subversion Repositories embedded_risc

[/] [embedded_risc/] [trunk/] [Verilog/] [lru_instruction_cache.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	26	hosseinami	`/**********************************************************`
2			`MODULE: Sub Level Least Recently Used Instruction Cache`
3
4			`FILE NAME: lru_instruction_cache.v`
5			`VERSION: 1.0`
6			`DATE: May 7th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the top level RTL code of LRU`
12			`instruction Cache verilog code.`
13
14			`It will instantiate the following blocks in the ASIC:`
15
16			`1) Instruction Cache Way 0`
17			`2) Instruction Cache Way 1`
18			`3) Instruction Cache Way 2`
19			`4) Instruction Cache Way 3`
20
21
22			`Hossein Amidi`
23			`(C) April 2002`
24
25			`*********************************************************/`
26
27			`// DEFINES`
28			`timescale 1ns / 10ps
29
30			`// TOP MODULE`
31			`module lru_instruction_cache(// Inputs`
32			`reset,`
33			`clk0,`
34			`cache_host_addr,`
35			`cache_host_cmd,`
36			`cache_request,`
37			`cache_host_datain,`
38			`cache_bus_grant,`
39			`cache_datain,`
40			`// Outputs`
41			`cache_host_dataout,`
42			`cache_hit,`
43			`cache_miss,`
44			`cache_bus_request,`
45			`cache_addr,`
46			`cache_cmd,`
47			`cache_dataout`
48			`);`
49
50
51			`// Parameter`
52			`include "parameter.v"
53
54			`// Inputs`
55			`input reset;`
56			`input clk0;`
57			`input [padd_size - 1 : 0]cache_host_addr;`
58			`input [cmd_size - 1 : 0]cache_host_cmd;`
59			`input cache_request;`
60			`input [data_size - 1 : 0]cache_host_datain;`
61			`input cache_bus_grant;`
62			`input [data_size - 1 : 0]cache_datain;`
63
64			`// Outputs`
65			`output [data_size - 1 : 0]cache_host_dataout;`
66			`output cache_hit;`
67			`output cache_miss;`
68			`output cache_bus_request;`
69			`output [padd_size - 1 : 0]cache_addr;`
70			`output [cmd_size - 1 : 0]cache_cmd;`
71			`output [data_size - 1 : 0]cache_dataout;`
72
73			`// Signal Declarations`
74			`wire reset;`
75			`wire clk0;`
76			`wire [padd_size - 1 : 0]cache_host_addr;`
77			`wire [cmd_size - 1 : 0]cache_host_cmd;`
78			`wire cache_request;`
79			`wire [data_size - 1 : 0]cache_host_datain;`
80			`wire cache_bus_grant;`
81			`wire [data_size - 1 : 0]cache_datain;`
82
83			`reg [data_size - 1 : 0]cache_host_dataout;`
84			`reg cache_hit;`
85			`reg cache_miss;`
86			`wire cache_bus_request;`
87			`reg [padd_size - 1 : 0]cache_addr;`
88			`reg [cmd_size - 1 : 0]cache_cmd;`
89			`reg [data_size - 1 : 0]cache_dataout;`
90
91			`wire [cache_line_size - 1 : 0]instruction_cache_datain_way0;`
92			`wire [cache_line_size - 1 : 0]instruction_cache_datain_way1;`
93			`wire [cache_line_size - 1 : 0]instruction_cache_datain_way2;`
94			`wire [cache_line_size - 1 : 0]instruction_cache_datain_way3;`
95			`wire [cache_line_size - 1 : 0]instruction_cache_dataout_way0;`
96			`wire [cache_line_size - 1 : 0]instruction_cache_dataout_way1;`
97			`wire [cache_line_size - 1 : 0]instruction_cache_dataout_way2;`
98			`wire [cache_line_size - 1 : 0]instruction_cache_dataout_way3;`
99
100			`wire cache_wr;`
101			`reg [cache_valid - 1 : 0]valid0;`
102			`reg [cache_valid - 1 : 0]valid1;`
103			`reg [cache_valid - 1 : 0]valid2;`
104			`reg [cache_valid - 1 : 0]valid3;`
105			`wire [cache_tag - 1 : 0]tag;`
106			`wire [cache_tag - 1 : 0]read_tag0;`
107			`wire [cache_tag - 1 : 0]read_tag1;`
108			`wire [cache_tag - 1 : 0]read_tag2;`
109			`wire [cache_tag - 1 : 0]read_tag3;`
110
111			`wire [cache_valid - 1 : 0]wvalid0;`
112			`wire [cache_valid - 1 : 0]wvalid1;`
113			`wire [cache_valid - 1 : 0]wvalid2;`
114			`wire [cache_valid - 1 : 0]wvalid3;`
115
116
117			`/******* Internal Register of Instruction cache configuration *******/`
118			`reg [cache_reg_width - 1 : 0] cache_register [cache_reg_depth - 1 : 0];`
119
120
121
122			`// Assignment statments`
123			`assign cache_bus_request = cache_miss;`
124			`assign cache_wr = (cache_host_cmd == 010) ? 1'b1 : 1'b0;`
125
126			`assign tag = cache_host_addr[23:5];`
127			`assign read_tag0 = instruction_cache_dataout_way0[50:32];`
128			`assign read_tag1 = instruction_cache_dataout_way1[50:32];`
129			`assign read_tag2 = instruction_cache_dataout_way2[50:32];`
130			`assign read_tag3 = instruction_cache_dataout_way3[50:32];`
131			`assign instruction_cache_datain_way0 = ({wvalid0,tag,cache_datain});`
132			`assign instruction_cache_datain_way1 = ({wvalid1,tag,cache_datain});`
133			`assign instruction_cache_datain_way2 = ({wvalid2,tag,cache_datain});`
134			`assign instruction_cache_datain_way3 = ({wvalid3,tag,cache_datain});`
135
136			`assign wvalid0 = valid0;`
137			`assign wvalid1 = valid1;`
138			`assign wvalid2 = valid2;`
139			`assign wvalid3 = valid3;`
140
141			`/******************************** Sub Level Instantiation *******************************/`
142
143
144			`instruction_cache_way0 instruction_cache_way0_0 (// Input`
145			`.A(cache_host_addr[4:0]),`
146			`.CLK(clk0),`
147			`.D(instruction_cache_datain_way0),`
148			`.WE(cache_wr),`
149			`.SPO(instruction_cache_dataout_way0));`
150
151
152			`instruction_cache_way1 instruction_cache_way1_0 (// Input`
153			`.A(cache_host_addr[4:0]),`
154			`.CLK(clk0),`
155			`.D(instruction_cache_datain_way1),`
156			`.WE(cache_wr),`
157			`.SPO(instruction_cache_dataout_way1));`
158
159
160			`instruction_cache_way2 instruction_cache_way2_0 (// Input`
161			`.A(cache_host_addr[4:0]),`
162			`.CLK(clk0),`
163			`.D(instruction_cache_datain_way2),`
164			`.WE(cache_wr),`
165			`.SPO(instruction_cache_dataout_way2));`
166
167
168			`instruction_cache_way3 instruction_cache_way3_0 (// Input`
169			`.A(cache_host_addr[4:0]),`
170			`.CLK(clk0),`
171			`.D(instruction_cache_datain_way3),`
172			`.WE(cache_wr),`
173			`.SPO(instruction_cache_dataout_way3));`
174
175
176
177			`// Generate the LRU talbe`
178			`always @(posedge reset or posedge clk0)`
179			`begin`
180			`if(reset == 1'b1)`
181			`begin`
182			`valid0 <= 2'b00;`
183			`valid1 <= 2'b00;`
184			`valid2 <= 2'b10;`
185			`valid3 <= 2'b10;`
186			`end`
187			`else`
188			`begin`
189			`if((cache_wr == 1'b1) && (wvalid0 == 2'b00))`
190			`valid0 <= 2'b01;`
191			`else`
192			`if((cache_wr == 1'b1) && (wvalid0 == 2'b01))`
193			`valid0 <= 2'b00;`
194			`else`
195			`if((cache_wr == 1'b1) && (wvalid1 == 2'b00))`
196			`valid1 <= 2'b01;`
197			`else`
198			`if((cache_wr == 1'b1) && (wvalid1 == 2'b01))`
199			`valid1 <= 2'b00;`
200			`else`
201			`if((cache_wr == 1'b1) && (wvalid2 == 2'b10))`
202			`valid2 <= 2'b11;`
203			`else`
204			`if((cache_wr == 1'b1) && (wvalid2 == 2'b11))`
205			`valid2 <= 2'b10;`
206			`else`
207			`if((cache_wr == 1'b1) && (wvalid3 == 2'b10))`
208			`valid3 <= 2'b11;`
209			`else`
210			`if((cache_wr == 1'b1) && (wvalid3 == 2'b11))`
211			`valid3 <= 2'b10;`
212			`end`
213			`end`
214
215
216			`// Check for cache way validity, if matches generate the cache hit signal`
217			`// else generate cache miss signal`
218			`always @(posedge reset or posedge clk0)`
219			`begin`
220			`if(reset == 1'b1)`
221			`cache_dataout <= 32'h0;`
222			`else`
223			`if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag0 == cache_host_addr[23:5]))`
224			`begin`
225			`cache_hit <= 1'b1;`
226			`cache_dataout <= instruction_cache_dataout_way0[31:0];`
227			`end`
228			`else`
229			`if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag1 == cache_host_addr[23:5]))`
230			`begin`
231			`cache_hit <= 1'b1;`
232			`cache_dataout <= instruction_cache_dataout_way1[31:0];`
233			`end`
234			`else`
235			`if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag2 == cache_host_addr[23:5]))`
236			`begin`
237			`cache_hit <= 1'b1;`
238			`cache_dataout <= instruction_cache_dataout_way2[31:0];`
239			`end`
240			`else`
241			`if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag3 == cache_host_addr[23:5]))`
242			`begin`
243			`cache_hit <= 1'b1;`
244			`cache_dataout <= instruction_cache_dataout_way3[31:0];`
245			`end`
246			`else`
247			`if((cache_request == 1'b1) && (cache_host_cmd == 001))`
248			`begin`
249			`cache_miss <= 1'b1;`
250			`cache_hit <= 1'b0;`
251			`cache_dataout <= 32'h0;`
252			`end`
253			`else`
254			`begin`
255			`cache_miss <= 1'b0;`
256			`cache_hit <= 1'b0;`
257			`cache_dataout <= 32'h0;`
258			`end`
259			`end`
260
261
262			`// Access to internal register by CPU address and command signals (write/read)`
263			`always @(posedge reset or posedge clk0)`
264			`begin`
265			`if(reset == 1'b1)`
266			`begin`
267			`cache_host_dataout <= 32'h0;`
268			`cache_register[0] <= 32'h0;`
269			`cache_register[1] <= 32'h0;`
270			`cache_register[2] <= 32'h0;`
271			`cache_register[3] <= 32'h0;`
272			`cache_register[4] <= 32'h0;`
273			`cache_register[5] <= 32'h0;`
274			`cache_register[6] <= 32'h0;`
275			`cache_register[7] <= 32'h0;`
276			`end`
277			`else`
278			`begin`
279			`if(cache_host_cmd == 3'b010) // Write from Host to Cache internal Registers`
280			`begin`
281			`case (cache_host_addr)`
282
283			`24'h080018: cache_register[0] <= cache_host_datain; // Status Register`
284			`24'h080019: cache_register[1] <= cache_host_datain; // Read Master Start Address`
285			`24'h08001A: cache_register[2] <= cache_host_datain; // Write Master Start Address`
286			`24'h08001B: cache_register[3] <= cache_host_datain; // Length in Bytes`
287			`24'h08001C: cache_register[4] <= cache_host_datain; // Reserved`
288			`24'h08001D: cache_register[5] <= cache_host_datain; // Reserved`
289			`24'h08001E: cache_register[6] <= cache_host_datain; // Control`
290			`24'h08001F: cache_register[7] <= cache_host_datain; // Reserved`
291			`endcase`
292			`end`
293			`else`
294			`if(cache_host_cmd == 3'b001) // Read from Cache internal Registers to Host`
295			`begin`
296			`case (cache_host_addr)`
297
298			`24'h080018: cache_host_dataout <= cache_register[0];`
299			`24'h080019: cache_host_dataout <= cache_register[1];`
300			`24'h08001A: cache_host_dataout <= cache_register[2];`
301			`24'h08001B: cache_host_dataout <= cache_register[3];`
302			`24'h08001C: cache_host_dataout <= cache_register[4];`
303			`24'h08001D: cache_host_dataout <= cache_register[5];`
304			`24'h08001E: cache_host_dataout <= cache_register[6];`
305			`24'h08001F: cache_host_dataout <= cache_register[7];`
306			`endcase`
307			`end`
308			`end`
309			`end`
310
311
312			`always @(posedge reset or posedge clk0)`
313			`begin`
314			`if(reset == 1'b1)`
315			`begin`
316			`cache_addr <= 24'h0;`
317			`cache_cmd <= 3'h0;`
318			`end`
319			`else`
320			`begin`
321			`cache_addr <= cache_bus_grant & cache_host_addr;`
322			`cache_cmd <= cache_bus_grant & cache_host_cmd;`
323			`end`
324			`end`
325
326			`endmodule`