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[/] [embedded_risc/] [trunk/] [Verilog/] [oe_generator.v] - Blame information for rev 27

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/*********************************************************
 MODULE:                Sub Level SDRAM Output Enable Generator
 
 FILE NAME:     oe_generator.v
 VERSION:       1.0
 DATE:          April 28th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the sub level RTL code of SDRAM Controller ASIC verilog
 code. It will generate the Output Enable signal.
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
module oe_generator(// Input
                                                        reset,
                                                        clk0,
                                                        page_mod,
                                                        do_writea1,
                                                        bur_len,
                                                        cas_lat,
                                                        do_preacharge,
                                                        do_reada,
                                                        do_refresh,
                                                        // Output
                                                        oe,
                                                        oe4
                                                        );
 
 
// Parameter
`include        "parameter.v"
 
// Input
input reset;
input clk0;
input page_mod;
input do_writea1;
input [burst_size - 1 : 0]bur_len;
input [cas_size - 1 : 0]cas_lat;
input do_preacharge;
input do_reada;
input do_refresh;
 
// Output
output oe;
output oe4;
 
// Internal wire and reg signals
wire reset;
wire clk0;
wire page_mod;
wire do_writea1;
wire [burst_size - 1 : 0]bur_len;
wire [cas_size - 1 : 0]cas_lat;
wire do_preacharge;
wire do_reada;
wire do_refresh;
 
reg oe;
reg oe4;
 
reg oe1;
reg oe2;
reg oe3;
reg [7:0]oe_shift;
 
// Assignment
 
 
// logic that generates the oe signal for the data path module
// For normal burst write he duration of oe is dependent on the configured burst length.
// For page mode accesses(page_mod=1) the oe signal is turned on at the start of the write command
// and is left on until a preacharge(page burst terminate) is detected.
//
always @(posedge reset or posedge clk0)
begin
        if (reset == 1'b1)
        begin
                oe_shift <= 0;
                oe1      <= 0;
                oe2      <= 0;
                oe       <= 0;
        end
        else
        begin
                if (page_mod == 0)
                begin
                        if (do_writea1 == 1)
                        begin
                                if (bur_len == 1)                     //  Set the shift register to the appropriate
                                        oe_shift <= 0;                // value based on burst length.
                                else if (bur_len == 2)
                                        oe_shift <= 1;
                                else if (bur_len == 4)
                                        oe_shift <= 7;
                                else if (bur_len == 8)
                                        oe_shift <= 127;
                                oe1 <= 1;
                        end
                        else
                        begin
                                oe_shift[6:0] <= oe_shift[7:1];       // Do the shift operation
                                oe_shift[7]   <= 0;
                                oe1  <= oe_shift[0];
                                oe2  <= oe1;
                                oe3  <= oe2;
                                oe4   <= oe3;
                                if (cas_lat == 2)
                                        oe <= oe3;
                                else
                                        oe <= oe4;
                        end
                end
                else
                begin
                        if (do_writea1 == 1)                                    // oe generation for page mode accesses
                                oe4   <= 1;
                        else if (do_preacharge == 1 | do_reada == 1 | do_refresh)
                                oe4   <= 0;
                        oe <= oe4;
                end
 
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level SDRAM Output Enable Generator`
3
4			`FILE NAME: oe_generator.v`
5			`VERSION: 1.0`
6			`DATE: April 28th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog`
12			`code. It will generate the Output Enable signal.`
13
14			`Hossein Amidi`
15			`(C) April 2002`
16
17			`*********************************************************/`
18
19			`// DEFINES`
20			`timescale 1ns / 10ps
21
22			`module oe_generator(// Input`
23			`reset,`
24			`clk0,`
25			`page_mod,`
26			`do_writea1,`
27			`bur_len,`
28			`cas_lat,`
29			`do_preacharge,`
30			`do_reada,`
31			`do_refresh,`
32			`// Output`
33			`oe,`
34			`oe4`
35			`);`
36
37
38			`// Parameter`
39			`include "parameter.v"
40
41			`// Input`
42			`input reset;`
43			`input clk0;`
44			`input page_mod;`
45			`input do_writea1;`
46			`input [burst_size - 1 : 0]bur_len;`
47			`input [cas_size - 1 : 0]cas_lat;`
48			`input do_preacharge;`
49			`input do_reada;`
50			`input do_refresh;`
51
52			`// Output`
53			`output oe;`
54			`output oe4;`
55
56			`// Internal wire and reg signals`
57			`wire reset;`
58			`wire clk0;`
59			`wire page_mod;`
60			`wire do_writea1;`
61			`wire [burst_size - 1 : 0]bur_len;`
62			`wire [cas_size - 1 : 0]cas_lat;`
63			`wire do_preacharge;`
64			`wire do_reada;`
65			`wire do_refresh;`
66
67			`reg oe;`
68			`reg oe4;`
69
70			`reg oe1;`
71			`reg oe2;`
72			`reg oe3;`
73			`reg [7:0]oe_shift;`
74
75			`// Assignment`
76
77
78			`// logic that generates the oe signal for the data path module`
79			`// For normal burst write he duration of oe is dependent on the configured burst length.`
80			`// For page mode accesses(page_mod=1) the oe signal is turned on at the start of the write command`
81			`// and is left on until a preacharge(page burst terminate) is detected.`
82			`//`
83			`always @(posedge reset or posedge clk0)`
84			`begin`
85			`if (reset == 1'b1)`
86			`begin`
87			`oe_shift <= 0;`
88			`oe1 <= 0;`
89			`oe2 <= 0;`
90			`oe <= 0;`
91			`end`
92			`else`
93			`begin`
94			`if (page_mod == 0)`
95			`begin`
96			`if (do_writea1 == 1)`
97			`begin`
98			`if (bur_len == 1) // Set the shift register to the appropriate`
99			`oe_shift <= 0; // value based on burst length.`
100			`else if (bur_len == 2)`
101			`oe_shift <= 1;`
102			`else if (bur_len == 4)`
103			`oe_shift <= 7;`
104			`else if (bur_len == 8)`
105			`oe_shift <= 127;`
106			`oe1 <= 1;`
107			`end`
108			`else`
109			`begin`
110			`oe_shift[6:0] <= oe_shift[7:1]; // Do the shift operation`
111			`oe_shift[7] <= 0;`
112			`oe1 <= oe_shift[0];`
113			`oe2 <= oe1;`
114			`oe3 <= oe2;`
115			`oe4 <= oe3;`
116			`if (cas_lat == 2)`
117			`oe <= oe3;`
118			`else`
119			`oe <= oe4;`
120			`end`
121			`end`
122			`else`
123			`begin`
124			`if (do_writea1 == 1) // oe generation for page mode accesses`
125			`oe4 <= 1;`
126			`else if (do_preacharge == 1 \| do_reada == 1 \| do_refresh)`
127			`oe4 <= 0;`
128			`oe <= oe4;`
129			`end`
130
131			`end`
132			`end`
133
134			`endmodule`

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[/] [embedded_risc/] [trunk/] [Verilog/] [oe_generator.v] - Blame information for rev 27