OpenCores
URL https://opencores.org/ocsvn/embedded_risc/embedded_risc/trunk

Subversion Repositories embedded_risc

[/] [embedded_risc/] [trunk/] [Verilog/] [ref_ack.v] - Blame information for rev 27

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 hosseinami
/*********************************************************
2
 MODULE:                Sub Level SDRAM Refresh Acknowledge
3
 
4
 FILE NAME:     ref_ack.v
5
 VERSION:       1.0
6
 DATE:          April 28th, 2002
7
 AUTHOR:                Hossein Amidi
8
 COMPANY:
9
 CODE TYPE:     Register Transfer Level
10
 
11
 DESCRIPTION:   This module is the sub level RTL code of SDRAM Controller ASIC verilog
12
 code. It is the Refresh Acknowledge block.
13
 
14
 
15
 Hossein Amidi
16
 (C) April 2002
17
 
18
*********************************************************/
19
 
20
// DEFINES
21
`timescale 1ns / 10ps
22
 
23
module ref_ack(// Input
24
                                        reset,
25
                                        clk0,
26
                                        do_refresh,
27
                                        do_reada,
28
                                        do_writea,
29
                                        do_preacharge,
30
                                        do_load_mod,
31
                                        ref_req,
32
                                        // Output
33
                                        cmack,
34
                                        ref_ack
35
                                        );
36
 
37
// Parameter
38
`include        "parameter.v"
39
 
40
// Input
41
input reset;
42
input clk0;
43
input do_refresh;
44
input do_reada;
45
input do_writea;
46
input do_preacharge;
47
input do_load_mod;
48
input ref_req;
49
 
50
// Output
51
output cmack;
52
output ref_ack;
53
 
54
// Internal wire and reg signals
55
wire reset;
56
wire clk0;
57
wire do_refresh;
58
wire do_reada;
59
wire do_writea;
60
wire do_preacharge;
61
wire do_load_mod;
62
wire ref_req;
63
 
64
reg     cmack;
65
reg   ref_ack;
66
 
67
// Assignment
68
 
69
// This always block generates the command acknowledge, cmack, signal.
70
// It also generates the acknowledge signal, ref_ack, that acknowledges
71
// a refresh request that was generated by the internal refresh timer circuit.
72
always @(posedge reset or posedge clk0)
73
begin
74
 
75
        if (reset == 1'b1)
76
        begin
77
                cmack    <= 0;
78
                ref_ack  <= 0;
79
        end
80
 
81
        else
82
        begin
83
                if (do_refresh == 1 & ref_req == 1)                   // Internal refresh timer refresh request
84
                        ref_ack <= 1;
85
                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_preacharge == 1)   // externa  commands
86
                         | (do_load_mod))
87
                        cmack <= 1;
88
                else
89
                begin
90
                        ref_ack <= 0;
91
                        cmack   <= 0;
92
                end
93
        end
94
end
95
 
96
 
97
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.