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[/] [embedded_risc/] [trunk/] [Verilog/] [ref_timer.v] - Blame information for rev 29

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/*********************************************************
 MODULE:                Sub Level Refresh Timer
 
 FILE NAME:     ref_timer.v
 VERSION:       1.0
 DATE:          April 28th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the sub level RTL code of SDRAM Controller ASIC verilog
 code. It will generate the internal refresh counter.
 
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
module ref_timer(// Input
                                                reset,
                                                clk0,
                                                refresh_count,
                                                bur_len,
                                                ref_ack,
                                                // Output
                                                ref_req
                                                );
 
// Parameter
`include        "parameter.v"
 
// Input
input reset;
input clk0;
input [15:0]refresh_count;
input [burst_size - 1 : 0]bur_len;
input ref_ack;
 
// Output
output ref_req;
 
// Internal wire and reg signals
reg ref_req;
 
reg [15:0]refresh_timer;                 // 16-bit refresh counter Max. 65536
reg rftimer_zero;
 
 
// Assignment
 
 
// Refresh Timer
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                refresh_timer <= 16'h0000;
                rftimer_zero  <= 1'b0;
                ref_req       <= 1'b0;
        end
        else
        begin
                if(rftimer_zero == 1'b1)
                        refresh_timer <= refresh_count;
                else
                        if(bur_len != 3'b000)
                                refresh_timer <= refresh_timer - 1'b1;
                        if((refresh_timer == 0) & (bur_len != 3'b000))
                        begin
                                rftimer_zero <= 1'b1;
                                ref_req <= 1'b1;
                        end
                        else
                                if(ref_ack == 1'b1)
                                begin
                                        rftimer_zero <= 1'b0;
                                        ref_req <= 1'b0;
                                end
        end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level Refresh Timer`
3
4			`FILE NAME: ref_timer.v`
5			`VERSION: 1.0`
6			`DATE: April 28th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog`
12			`code. It will generate the internal refresh counter.`
13
14
15			`Hossein Amidi`
16			`(C) April 2002`
17
18			`*********************************************************/`
19
20			`// DEFINES`
21			`timescale 1ns / 10ps
22			`module ref_timer(// Input`
23			`reset,`
24			`clk0,`
25			`refresh_count,`
26			`bur_len,`
27			`ref_ack,`
28			`// Output`
29			`ref_req`
30			`);`
31
32			`// Parameter`
33			`include "parameter.v"
34
35			`// Input`
36			`input reset;`
37			`input clk0;`
38			`input [15:0]refresh_count;`
39			`input [burst_size - 1 : 0]bur_len;`
40			`input ref_ack;`
41
42			`// Output`
43			`output ref_req;`
44
45			`// Internal wire and reg signals`
46			`reg ref_req;`
47
48			`reg [15:0]refresh_timer; // 16-bit refresh counter Max. 65536`
49			`reg rftimer_zero;`
50
51
52			`// Assignment`
53
54
55			`// Refresh Timer`
56			`always @(posedge reset or posedge clk0)`
57			`begin`
58			`if(reset == 1'b1)`
59			`begin`
60			`refresh_timer <= 16'h0000;`
61			`rftimer_zero <= 1'b0;`
62			`ref_req <= 1'b0;`
63			`end`
64			`else`
65			`begin`
66			`if(rftimer_zero == 1'b1)`
67			`refresh_timer <= refresh_count;`
68			`else`
69			`if(bur_len != 3'b000)`
70			`refresh_timer <= refresh_timer - 1'b1;`
71			`if((refresh_timer == 0) & (bur_len != 3'b000))`
72			`begin`
73			`rftimer_zero <= 1'b1;`
74			`ref_req <= 1'b1;`
75			`end`
76			`else`
77			`if(ref_ack == 1'b1)`
78			`begin`
79			`rftimer_zero <= 1'b0;`
80			`ref_req <= 1'b0;`
81			`end`
82			`end`
83			`end`
84
85
86			`endmodule`

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[/] [embedded_risc/] [trunk/] [Verilog/] [ref_timer.v] - Blame information for rev 29