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/*********************************************************
 MODULE:                Top Level System On A Chip Design
 
 FILE NAME:     soc.v
 DATE:          May 7th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the top level RTL code of System On a Chip Verilog code.
 It will instantiate the following blocks in the ASIC:
 
 1)   Vertex STARTUP
 2)     DLL
 3)     RISC uProcessor
 4)     DMA Cntrl
 5)     LRU Data Cache
 6)     LRU Instruction Cache
 7)     Bus Arbiter
 8)     UART
 9)     Timer
 10)  Flash Controller
 11)    SDRAM Controller
 
 Hossein Amidi
 (C) May 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
// TOP MODULE
module soc(     // Inputs
                                                clk,
                                                reset,
                                                irq,
                                                ser_rxd,
                                                flash_datain,
                                                mem_datain,
                                                // Outputs
                                                pll_lock,
                                                addr,
                                                cs,
                                                ras,
                                                cas,
                                                we,
                                                dqm,
                                                cke,
                                                ba,
                                                pllclk,
                                                halted,
                                                ser_txd,
                                                flash_cle,
                                                flash_ale,
                                                flash_ce,
                                                flash_re,
                                                flash_we,
                                                flash_wp,
                                                flash_rb,
                                                flash_irq,
                                                flash_dataout,
                                                mem_dataout,
                                                mem_addr,
                                                mem_req,
                                                mem_rdwr,
                                                // Inouts
                                                dq
                                                );
 
// Parameter
`include        "parameter.v"
 
 
// Inputs
input clk;
input reset;
input irq;
input ser_rxd;
input [flash_size - 1 : 0]flash_datain;
input [data_size - 1 : 0]mem_datain;
 
// Outputs
output pll_lock;
output [add_size - 1 : 0]addr;
output [cs_size  - 1 : 0]cs;
output ras;
output cas;
output we;
output [dqm_size - 1 : 0]dqm;
output cke;
output [ba_size - 1 : 0]ba;
output pllclk;
output halted;
output ser_txd;
output flash_cle;
output flash_ale;
output flash_ce;
output flash_re;
output flash_we;
output flash_wp;
output flash_rb;
output flash_irq;
output [flash_size - 1 : 0]flash_dataout;
output [data_size -1 : 0]mem_dataout;
output [padd_size - 1 : 0]mem_addr;
output mem_req;
output mem_rdwr;
 
// Inouts
inout [data_size - 1 : 0]dq;
 
 
// Signal Declarations
wire clk;
wire reset;
wire irq;
wire [add_size - 1 : 0]addr;
wire [cs_size - 1 : 0]cs;
wire ras;
wire cas;
wire we;
wire [dqm_size - 1 : 0]dqm;
wire cke;
wire [ba_size - 1 : 0]ba;
wire pllclk;
wire halted;
wire [data_size - 1 : 0]dq;
 
wire system_irq;
 
// RISC Signal Declarations
wire [irq_size - 1 : 0]interrupt;
wire cmdack;
wire [arbiter_bus_size - 1 : 0]bus_grant;
wire [data_size - 1 : 0]dcache_host_datain;
wire [data_size - 1 : 0]icache_host_datain;
wire dcache_hit;
wire dcache_miss;
wire icache_hit;
wire icache_miss;
wire [data_size - 1 : 0]dma_host_datain;
wire [padd_size - 1 : 0]host_addr;
wire [cmd_size - 1 : 0]host_cmd;
wire [dqm_size - 1 : 0]host_dm;
wire [arbiter_bus_size - 1 : 0]bus_request;
wire dcache_request;
wire icache_request;
wire [data_size - 1 : 0]dma_host_dataout;
wire [data_size - 1 : 0]dcache_host_dataout;
wire [data_size - 1 : 0]icache_host_dataout;
 
// DMA Signal Declarations
wire [fifo_size - 1 : 0]dma_rd_datain;
wire [fifo_size - 1 : 0]dma_wr_datain;
wire dma_irq;
wire [padd_size - 1 : 0]dma_rd_addr;
wire [padd_size - 1 : 0]dma_wr_addr;
wire [cmd_size - 1 : 0]dma_rd_cmd;
wire [fifo_size - 1 : 0]dma_wr_dataout;
wire [fifo_size - 1 : 0]dma_rd_dataout;
wire dma_busy;
 
 
// LRU Data Cache Signal Declarations
wire [data_size - 1 : 0]dcache_datain;
wire [padd_size - 1 : 0]dcache_addr;
wire [cmd_size - 1 : 0]dcache_cmd;
wire [data_size - 1 : 0]dcache_dataout;
wire [padd_size - 1 : 0]sdram_addr;
wire [cmd_size - 1 : 0]sdram_cmd;
 
 
// LRU Instruction Cache Signal Declarations
wire [data_size - 1 : 0]icache_datain;
wire [padd_size - 1 : 0]icache_addr;
wire [cmd_size - 1 : 0]icache_cmd;
wire [data_size - 1 : 0]icache_dataout;
 
 
// Bus Arbiter Signal Declarations
wire [data_size - 1 : 0]sdram_datain;
wire [data_size - 1 : 0]sdram_dataout;
 
 
// SDRAM Controller Signal Declarations
 
 
// UART Signal Declarations
wire uart_cs;
wire uart_rd;
wire uart_wr;
wire ser_rxd;
wire ser_txd;
wire [data_size - 1 : 0]uart_host_datain;
wire [data_size - 1 : 0]uart_host_dataout;
 
// Timer Signal Declarations
wire [data_size - 1 : 0]timer_host_datain;
wire timer_irq;
wire [data_size - 1 : 0]timer_host_dataout;
 
 
// Flash Controller Signal Decelaration
wire [data_size - 1 : 0]flash_host_dataout;
wire [flash_size - 1 : 0]flash_datain;
wire [data_size - 1 : 0]flash_host_datain;
wire flash_cle;
wire flash_ale;
wire flash_ce;
wire flash_re;
wire flash_we;
wire flash_wp;
wire flash_rb;
wire flash_irq;
wire [flash_size - 1 : 0]flash_dataout;
 
 
// Memory
wire [data_size - 1 :0]mem_dataout;
wire [data_size - 1 :0]mem_datain;
wire mem_req;
wire mem_rdwr;
wire [padd_size - 1 : 0]mem_addr;
 
assign mem_addr = host_addr;
 
 
 
 
// Assignment statments
assign system_irq = irq;
assign interrupt = {timer_irq,dma_irq,system_irq};
 
/*--------------------------- Module Instantiation ----------------------------*/
 
STARTUP_VIRTEX u22 (.GSR(reset));
 
/*--------------------------- DLL Instantiation Block ----------------------------*/
wire CLKIN_w;
wire clk0;
 
wire CLK0_dll, CLK90_dll, CLK180_dll, CLK2X_dll, CLKDV2_dll;
wire clk0_90, clk0_180, clk0_2x, clk0_dv2;
wire pll_lock;
 
IBUFG clkpad (.I(clk), .O(CLKIN_w));
 
CLKDLL dll_0 (.CLKIN(CLKIN_w), .CLKFB(clk0), .RST(reset),
            .CLK0(CLK0_dll), .CLK90(CLK90_dll), .CLK180(CLK180_dll), .CLK270(),
            .CLK2X(CLK2X_dll), .CLKDV(CLKDV2_dll), .LOCKED(pll_lock));
 
BUFG  u1 (.I(CLK0_dll),   .O(clk0));
BUFG  u2 (.I(CLK180_dll),  .O(clk0_180));
BUFG  u3 (.I(CLK2X_dll), .O(clk0_2x));
 
 
 
//assign pllclk = clk0_180;
 
assign pllclk = clk0;
 
/****************************** Sub Level Block Instantiation ****************************/
 
risc uProcessor0(       // Input
                                                .reset(reset),
                                                .clk0(clk0),
                                                .pll_lock(pll_lock),
                                                .interrupt(interrupt),
                                                .cmdack(cmdack),
                                                .dcache_datain(dcache_host_datain),
                                                .dcache_hit(dcache_hit),
                                                .dcache_miss(dcache_miss),
                                                .icache_datain(icache_host_datain),
                                                .icache_hit(icache_hit),
                                                .icache_miss(icache_miss),
                                                .dma_datain(dma_host_datain),
                                                .dma_busy(dma_busy),
                                                .timer_host_datain(timer_host_datain),
                                                .flash_host_datain(flash_host_datain),
                                                .uart_host_datain(uart_host_datain),
                                                .mem_datain(mem_datain),
                                                // Output
                                                .paddr(host_addr),
                                                .cmd(host_cmd),
                                                .dm(host_dm),
                                                .dcache_request(dcache_request),
                                                .icache_request(icache_request),
                                                .dma_dataout(dma_host_dataout),
                                                .dcache_dataout(dcache_host_dataout),
                                                .icache_dataout(icache_host_dataout),
                                                .timer_host_dataout(timer_host_dataout),
                                                .flash_host_dataout(flash_host_dataout),
                                                .uart_host_dataout(uart_host_dataout),
                                                .mem_dataout(mem_dataout),
                                                .mem_req(mem_req),
                                                .mem_rdwr(mem_rdwr),
                                                .halted(halted)
                                                );
 
 
dma_cntrl dma_cntrl0(// Input
                                                        .reset(reset),
                                                        .clk0(clk0),
                                                        .dma_host_addr(host_addr),
                                                        .dma_host_cmd(host_cmd),
                                                        .dma_host_datain(dma_host_dataout),
                                                        .dma_bus_grant(bus_grant[2]),
                                                        .dma_rd_datain(dma_rd_datain),
                                                        .dma_wr_datain(dma_wr_datain),
                                                        // Output
                                                        .dma_host_dataout(dma_host_datain),
                                                        .dma_irq(dma_irq),
                                                        .dma_bus_req(bus_request[2]),
                                                        .dma_rd_addr(dma_rd_addr),
                                                        .dma_wr_addr(dma_wr_addr),
                                                        .dma_wr_dataout(dma_wr_dataout),
                                                        .dma_rd_cmd(dma_rd_cmd),
                                                        .dma_busy(dma_busy),
                                                        .uart_cs(uart_cs),
                                                        .uart_rd(uart_rd),
                                                        .uart_wr(uart_wr),
                                                        .dma_rd_dataout(dma_rd_dataout)
                                                        );
 
 
 
lru_data_cache lru_data_cache0(// Input
                                                                                .reset(reset),
                                                                                .clk0(clk0),
                                                                                .cache_host_addr(host_addr),
                                                                                .cache_host_cmd(host_cmd),
                                                                                .cache_request(dcache_request),
                                                                                .cache_host_datain(dcache_host_dataout),
                                                                                .cache_bus_grant(bus_grant[0]),
                                                                                .cache_datain(dcache_datain),
                                                                                // Output
                                                                                .cache_host_dataout(dcache_host_datain),
                                                                                .cache_hit(dcache_hit),
                                                                                .cache_miss(dcache_miss),
                                                                                .cache_bus_request(bus_request[0]),
                                                                                .cache_addr(dcache_addr),
                                                                                .cache_cmd(dcache_cmd),
                                                                                .cache_dataout(dcache_dataout)
                                                                                );
 
 
lru_instruction_cache lru_inst_cache0(// Input
                                                                                                        .reset(reset),
                                                                                                        .clk0(clk0),
                                                                                                        .cache_host_addr(host_addr),
                                                                                                        .cache_host_cmd(host_cmd),
                                                                                                        .cache_request(icache_request),
                                                                                                        .cache_host_datain(icache_host_dataout),
                                                                                                        .cache_bus_grant(bus_grant[1]),
                                                                                                        .cache_datain(icache_datain),
                                                                                                        // Output
                                                                                                        .cache_host_dataout(icache_host_datain),
                                                                                                        .cache_hit(icache_hit),
                                                                                                        .cache_miss(icache_miss),
                                                                                                        .cache_bus_request(bus_request[1]),
                                                                                                        .cache_addr(icache_addr),
                                                                                                        .cache_cmd(icache_cmd),
                                                                                                        .cache_dataout(icache_dataout)
                                                                                                        );
 
 
bus_arbiter  bus_arbiter0(      // Input
                                                                        .reset(reset),
                                                                        .clk0(clk0),
                                                                        .bus_request(bus_request),
                                                                        .dma_dataout(dma_wr_dataout),
                                                                        .dma_addr(dma_rd_addr),
                                                                        .dma_cmd(dma_rd_cmd),
                                                                        .dcache_dataout(dcache_dataout),
                                                                        .dcache_addr(dcache_addr),
                                                                        .dcache_cmd(dcache_cmd),
                                                                        .icache_dataout(icache_dataout),
                                                                        .icache_addr(icache_addr),
                                                                        .icache_cmd(icache_cmd),
                                                                        .sdram_dataout(sdram_dataout),
                                                                        // Output
                                                                        .bus_grant(bus_grant),
                                                                        .dma_datain(dma_wr_datain),
                                                                        .dcache_datain(dcache_datain),
                                                                        .icache_datain(icache_datain),
                                                                        .sdram_addr(sdram_addr),
                                                                        .sdram_cmd(sdram_cmd),
                                                                        .sdram_datain(sdram_datain)
                                                                        );
 
 
uart  uart0(// Input
                                .reset(reset),
                                .clk0(clk0),
                                .uart_addr(dma_wr_addr),
                                .uart_host_addr(host_addr),
                                .uart_host_cmd(host_cmd),
                                .uart_cmd(dma_rd_cmd),
                                .uart_host_datain(uart_host_dataout),
                                .uart_cs(uart_cs),
                                .uart_rd(uart_rd),
                                .uart_wr(uart_wr),
                                .ser_rxd(ser_rxd),
                                .uart_datain(dma_rd_dataout),
                                // Output
                                .ser_txd(ser_txd),
                                .uart_host_dataout(uart_host_datain),
                                .uart_dataout(dma_rd_datain)
                                );
 
 
timer   timer0( // Input
                                                .reset(reset),
                                                .clk0(clk0),
                                                .timer_host_datain(timer_host_dataout),
                                                .timer_cmd(host_cmd),
                                                .timer_addr(host_addr),
                                                // Output
                                                .timer_host_dataout(timer_host_datain),
                                                .timer_irq(timer_irq)
                                                );
 
 
flash_ctrl flash_ctrl0(// Inputs
                                                                .reset(reset),
                                                                .clk0(clk0),
                                                                .flash_host_addr(host_addr),
                                                                .flash_host_cmd(host_cmd),
                                                                .flash_host_dataout(flash_host_dataout),
                                                                .flash_datain(flash_datain),
                                                                // Outputs
                                                                .flash_host_datain(flash_host_datain),
                                                                .flash_cle(flash_cle),
                                                                .flash_ale(flash_ale),
                                                                .flash_ce(flash_ce),
                                                                .flash_re(flash_re),
                                                                .flash_we(flash_we),
                                                                .flash_wp(flash_wp),
                                                                .flash_rb(flash_rb),
                                                                .flash_irq(flash_irq),
                                                                .flash_dataout(flash_dataout)
                                                                );
 
 
 
sdram_ctrl sdram_ctrl0(// Inputs
                                                                .clk0(clk0),
                                                                .clk0_2x(clk0_2x),
                                                                .reset(reset),
                                                                .paddr(sdram_addr),
                                                                .cmd(sdram_cmd),
                                                                .dm(host_dm),
                                                                .datain(sdram_datain),
                                                                // Outputs
                                                                .cmdack(cmdack),
                                                                .addr(addr),
                                                                .cs(cs),
                                                                .ras(ras),
                                                                .cas(cas),
                                                                .we(we),
                                                                .dqm(dqm),
                                                                .cke(cke),
                                                                .ba(ba),
                                                                .dataout(sdram_dataout),
                                                                // Inouts
                                                                .dq(dq)
                                                                );
 
endmodule

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[/] [embedded_risc/] [trunk/] [Verilog/] [soc.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Top Level System On A Chip Design`
3
4			`FILE NAME: soc.v`
5			`DATE: May 7th, 2002`
6			`AUTHOR: Hossein Amidi`
7			`COMPANY:`
8			`CODE TYPE: Register Transfer Level`
9
10			`DESCRIPTION: This module is the top level RTL code of System On a Chip Verilog code.`
11			`It will instantiate the following blocks in the ASIC:`
12
13			`1) Vertex STARTUP`
14			`2) DLL`
15			`3) RISC uProcessor`
16			`4) DMA Cntrl`
17			`5) LRU Data Cache`
18			`6) LRU Instruction Cache`
19			`7) Bus Arbiter`
20			`8) UART`
21			`9) Timer`
22			`10) Flash Controller`
23			`11) SDRAM Controller`
24
25			`Hossein Amidi`
26			`(C) May 2002`
27
28			`*********************************************************/`
29
30			`// DEFINES`
31			`timescale 1ns / 10ps
32
33			`// TOP MODULE`
34			`module soc( // Inputs`
35			`clk,`
36			`reset,`
37			`irq,`
38			`ser_rxd,`
39			`flash_datain,`
40			`mem_datain,`
41			`// Outputs`
42			`pll_lock,`
43			`addr,`
44			`cs,`
45			`ras,`
46			`cas,`
47			`we,`
48			`dqm,`
49			`cke,`
50			`ba,`
51			`pllclk,`
52			`halted,`
53			`ser_txd,`
54			`flash_cle,`
55			`flash_ale,`
56			`flash_ce,`
57			`flash_re,`
58			`flash_we,`
59			`flash_wp,`
60			`flash_rb,`
61			`flash_irq,`
62			`flash_dataout,`
63			`mem_dataout,`
64			`mem_addr,`
65			`mem_req,`
66			`mem_rdwr,`
67			`// Inouts`
68			`dq`
69			`);`
70
71			`// Parameter`
72			`include "parameter.v"
73
74
75			`// Inputs`
76			`input clk;`
77			`input reset;`
78			`input irq;`
79			`input ser_rxd;`
80			`input [flash_size - 1 : 0]flash_datain;`
81			`input [data_size - 1 : 0]mem_datain;`
82
83			`// Outputs`
84			`output pll_lock;`
85			`output [add_size - 1 : 0]addr;`
86			`output [cs_size - 1 : 0]cs;`
87			`output ras;`
88			`output cas;`
89			`output we;`
90			`output [dqm_size - 1 : 0]dqm;`
91			`output cke;`
92			`output [ba_size - 1 : 0]ba;`
93			`output pllclk;`
94			`output halted;`
95			`output ser_txd;`
96			`output flash_cle;`
97			`output flash_ale;`
98			`output flash_ce;`
99			`output flash_re;`
100			`output flash_we;`
101			`output flash_wp;`
102			`output flash_rb;`
103			`output flash_irq;`
104			`output [flash_size - 1 : 0]flash_dataout;`
105			`output [data_size -1 : 0]mem_dataout;`
106			`output [padd_size - 1 : 0]mem_addr;`
107			`output mem_req;`
108			`output mem_rdwr;`
109
110			`// Inouts`
111			`inout [data_size - 1 : 0]dq;`
112
113
114			`// Signal Declarations`
115			`wire clk;`
116			`wire reset;`
117			`wire irq;`
118			`wire [add_size - 1 : 0]addr;`
119			`wire [cs_size - 1 : 0]cs;`
120			`wire ras;`
121			`wire cas;`
122			`wire we;`
123			`wire [dqm_size - 1 : 0]dqm;`
124			`wire cke;`
125			`wire [ba_size - 1 : 0]ba;`
126			`wire pllclk;`
127			`wire halted;`
128			`wire [data_size - 1 : 0]dq;`
129
130			`wire system_irq;`
131
132			`// RISC Signal Declarations`
133			`wire [irq_size - 1 : 0]interrupt;`
134			`wire cmdack;`
135			`wire [arbiter_bus_size - 1 : 0]bus_grant;`
136			`wire [data_size - 1 : 0]dcache_host_datain;`
137			`wire [data_size - 1 : 0]icache_host_datain;`
138			`wire dcache_hit;`
139			`wire dcache_miss;`
140			`wire icache_hit;`
141			`wire icache_miss;`
142			`wire [data_size - 1 : 0]dma_host_datain;`
143			`wire [padd_size - 1 : 0]host_addr;`
144			`wire [cmd_size - 1 : 0]host_cmd;`
145			`wire [dqm_size - 1 : 0]host_dm;`
146			`wire [arbiter_bus_size - 1 : 0]bus_request;`
147			`wire dcache_request;`
148			`wire icache_request;`
149			`wire [data_size - 1 : 0]dma_host_dataout;`
150			`wire [data_size - 1 : 0]dcache_host_dataout;`
151			`wire [data_size - 1 : 0]icache_host_dataout;`
152
153			`// DMA Signal Declarations`
154			`wire [fifo_size - 1 : 0]dma_rd_datain;`
155			`wire [fifo_size - 1 : 0]dma_wr_datain;`
156			`wire dma_irq;`
157			`wire [padd_size - 1 : 0]dma_rd_addr;`
158			`wire [padd_size - 1 : 0]dma_wr_addr;`
159			`wire [cmd_size - 1 : 0]dma_rd_cmd;`
160			`wire [fifo_size - 1 : 0]dma_wr_dataout;`
161			`wire [fifo_size - 1 : 0]dma_rd_dataout;`
162			`wire dma_busy;`
163
164
165			`// LRU Data Cache Signal Declarations`
166			`wire [data_size - 1 : 0]dcache_datain;`
167			`wire [padd_size - 1 : 0]dcache_addr;`
168			`wire [cmd_size - 1 : 0]dcache_cmd;`
169			`wire [data_size - 1 : 0]dcache_dataout;`
170			`wire [padd_size - 1 : 0]sdram_addr;`
171			`wire [cmd_size - 1 : 0]sdram_cmd;`
172
173
174			`// LRU Instruction Cache Signal Declarations`
175			`wire [data_size - 1 : 0]icache_datain;`
176			`wire [padd_size - 1 : 0]icache_addr;`
177			`wire [cmd_size - 1 : 0]icache_cmd;`
178			`wire [data_size - 1 : 0]icache_dataout;`
179
180
181			`// Bus Arbiter Signal Declarations`
182			`wire [data_size - 1 : 0]sdram_datain;`
183			`wire [data_size - 1 : 0]sdram_dataout;`
184
185
186			`// SDRAM Controller Signal Declarations`
187
188
189			`// UART Signal Declarations`
190			`wire uart_cs;`
191			`wire uart_rd;`
192			`wire uart_wr;`
193			`wire ser_rxd;`
194			`wire ser_txd;`
195			`wire [data_size - 1 : 0]uart_host_datain;`
196			`wire [data_size - 1 : 0]uart_host_dataout;`
197
198			`// Timer Signal Declarations`
199			`wire [data_size - 1 : 0]timer_host_datain;`
200			`wire timer_irq;`
201			`wire [data_size - 1 : 0]timer_host_dataout;`
202
203
204			`// Flash Controller Signal Decelaration`
205			`wire [data_size - 1 : 0]flash_host_dataout;`
206			`wire [flash_size - 1 : 0]flash_datain;`
207			`wire [data_size - 1 : 0]flash_host_datain;`
208			`wire flash_cle;`
209			`wire flash_ale;`
210			`wire flash_ce;`
211			`wire flash_re;`
212			`wire flash_we;`
213			`wire flash_wp;`
214			`wire flash_rb;`
215			`wire flash_irq;`
216			`wire [flash_size - 1 : 0]flash_dataout;`
217
218
219			`// Memory`
220			`wire [data_size - 1 :0]mem_dataout;`
221			`wire [data_size - 1 :0]mem_datain;`
222			`wire mem_req;`
223			`wire mem_rdwr;`
224			`wire [padd_size - 1 : 0]mem_addr;`
225
226			`assign mem_addr = host_addr;`
227
228
229
230
231			`// Assignment statments`
232			`assign system_irq = irq;`
233			`assign interrupt = {timer_irq,dma_irq,system_irq};`
234
235			`/--------------------------- Module Instantiation ----------------------------/`
236
237			`STARTUP_VIRTEX u22 (.GSR(reset));`
238
239			`/--------------------------- DLL Instantiation Block ----------------------------/`
240			`wire CLKIN_w;`
241			`wire clk0;`
242
243			`wire CLK0_dll, CLK90_dll, CLK180_dll, CLK2X_dll, CLKDV2_dll;`
244			`wire clk0_90, clk0_180, clk0_2x, clk0_dv2;`
245			`wire pll_lock;`
246
247			`IBUFG clkpad (.I(clk), .O(CLKIN_w));`
248
249			`CLKDLL dll_0 (.CLKIN(CLKIN_w), .CLKFB(clk0), .RST(reset),`
250			`.CLK0(CLK0_dll), .CLK90(CLK90_dll), .CLK180(CLK180_dll), .CLK270(),`
251			`.CLK2X(CLK2X_dll), .CLKDV(CLKDV2_dll), .LOCKED(pll_lock));`
252
253			`BUFG u1 (.I(CLK0_dll), .O(clk0));`
254			`BUFG u2 (.I(CLK180_dll), .O(clk0_180));`
255			`BUFG u3 (.I(CLK2X_dll), .O(clk0_2x));`
256
257
258
259			`//assign pllclk = clk0_180;`
260
261			`assign pllclk = clk0;`
262
263			`/**************************** Sub Level Block Instantiation **************************/`
264
265			`risc uProcessor0( // Input`
266			`.reset(reset),`
267			`.clk0(clk0),`
268			`.pll_lock(pll_lock),`
269			`.interrupt(interrupt),`
270			`.cmdack(cmdack),`
271			`.dcache_datain(dcache_host_datain),`
272			`.dcache_hit(dcache_hit),`
273			`.dcache_miss(dcache_miss),`
274			`.icache_datain(icache_host_datain),`
275			`.icache_hit(icache_hit),`
276			`.icache_miss(icache_miss),`
277			`.dma_datain(dma_host_datain),`
278			`.dma_busy(dma_busy),`
279			`.timer_host_datain(timer_host_datain),`
280			`.flash_host_datain(flash_host_datain),`
281			`.uart_host_datain(uart_host_datain),`
282			`.mem_datain(mem_datain),`
283			`// Output`
284			`.paddr(host_addr),`
285			`.cmd(host_cmd),`
286			`.dm(host_dm),`
287			`.dcache_request(dcache_request),`
288			`.icache_request(icache_request),`
289			`.dma_dataout(dma_host_dataout),`
290			`.dcache_dataout(dcache_host_dataout),`
291			`.icache_dataout(icache_host_dataout),`
292			`.timer_host_dataout(timer_host_dataout),`
293			`.flash_host_dataout(flash_host_dataout),`
294			`.uart_host_dataout(uart_host_dataout),`
295			`.mem_dataout(mem_dataout),`
296			`.mem_req(mem_req),`
297			`.mem_rdwr(mem_rdwr),`
298			`.halted(halted)`
299			`);`
300
301
302			`dma_cntrl dma_cntrl0(// Input`
303			`.reset(reset),`
304			`.clk0(clk0),`
305			`.dma_host_addr(host_addr),`
306			`.dma_host_cmd(host_cmd),`
307			`.dma_host_datain(dma_host_dataout),`
308			`.dma_bus_grant(bus_grant[2]),`
309			`.dma_rd_datain(dma_rd_datain),`
310			`.dma_wr_datain(dma_wr_datain),`
311			`// Output`
312			`.dma_host_dataout(dma_host_datain),`
313			`.dma_irq(dma_irq),`
314			`.dma_bus_req(bus_request[2]),`
315			`.dma_rd_addr(dma_rd_addr),`
316			`.dma_wr_addr(dma_wr_addr),`
317			`.dma_wr_dataout(dma_wr_dataout),`
318			`.dma_rd_cmd(dma_rd_cmd),`
319			`.dma_busy(dma_busy),`
320			`.uart_cs(uart_cs),`
321			`.uart_rd(uart_rd),`
322			`.uart_wr(uart_wr),`
323			`.dma_rd_dataout(dma_rd_dataout)`
324			`);`
325
326
327
328			`lru_data_cache lru_data_cache0(// Input`
329			`.reset(reset),`
330			`.clk0(clk0),`
331			`.cache_host_addr(host_addr),`
332			`.cache_host_cmd(host_cmd),`
333			`.cache_request(dcache_request),`
334			`.cache_host_datain(dcache_host_dataout),`
335			`.cache_bus_grant(bus_grant[0]),`
336			`.cache_datain(dcache_datain),`
337			`// Output`
338			`.cache_host_dataout(dcache_host_datain),`
339			`.cache_hit(dcache_hit),`
340			`.cache_miss(dcache_miss),`
341			`.cache_bus_request(bus_request[0]),`
342			`.cache_addr(dcache_addr),`
343			`.cache_cmd(dcache_cmd),`
344			`.cache_dataout(dcache_dataout)`
345			`);`
346
347
348			`lru_instruction_cache lru_inst_cache0(// Input`
349			`.reset(reset),`
350			`.clk0(clk0),`
351			`.cache_host_addr(host_addr),`
352			`.cache_host_cmd(host_cmd),`
353			`.cache_request(icache_request),`
354			`.cache_host_datain(icache_host_dataout),`
355			`.cache_bus_grant(bus_grant[1]),`
356			`.cache_datain(icache_datain),`
357			`// Output`
358			`.cache_host_dataout(icache_host_datain),`
359			`.cache_hit(icache_hit),`
360			`.cache_miss(icache_miss),`
361			`.cache_bus_request(bus_request[1]),`
362			`.cache_addr(icache_addr),`
363			`.cache_cmd(icache_cmd),`
364			`.cache_dataout(icache_dataout)`
365			`);`
366
367
368			`bus_arbiter bus_arbiter0( // Input`
369			`.reset(reset),`
370			`.clk0(clk0),`
371			`.bus_request(bus_request),`
372			`.dma_dataout(dma_wr_dataout),`
373			`.dma_addr(dma_rd_addr),`
374			`.dma_cmd(dma_rd_cmd),`
375			`.dcache_dataout(dcache_dataout),`
376			`.dcache_addr(dcache_addr),`
377			`.dcache_cmd(dcache_cmd),`
378			`.icache_dataout(icache_dataout),`
379			`.icache_addr(icache_addr),`
380			`.icache_cmd(icache_cmd),`
381			`.sdram_dataout(sdram_dataout),`
382			`// Output`
383			`.bus_grant(bus_grant),`
384			`.dma_datain(dma_wr_datain),`
385			`.dcache_datain(dcache_datain),`
386			`.icache_datain(icache_datain),`
387			`.sdram_addr(sdram_addr),`
388			`.sdram_cmd(sdram_cmd),`
389			`.sdram_datain(sdram_datain)`
390			`);`
391
392
393			`uart uart0(// Input`
394			`.reset(reset),`
395			`.clk0(clk0),`
396			`.uart_addr(dma_wr_addr),`
397			`.uart_host_addr(host_addr),`
398			`.uart_host_cmd(host_cmd),`
399			`.uart_cmd(dma_rd_cmd),`
400			`.uart_host_datain(uart_host_dataout),`
401			`.uart_cs(uart_cs),`
402			`.uart_rd(uart_rd),`
403			`.uart_wr(uart_wr),`
404			`.ser_rxd(ser_rxd),`
405			`.uart_datain(dma_rd_dataout),`
406			`// Output`
407			`.ser_txd(ser_txd),`
408			`.uart_host_dataout(uart_host_datain),`
409			`.uart_dataout(dma_rd_datain)`
410			`);`
411
412
413			`timer timer0( // Input`
414			`.reset(reset),`
415			`.clk0(clk0),`
416			`.timer_host_datain(timer_host_dataout),`
417			`.timer_cmd(host_cmd),`
418			`.timer_addr(host_addr),`
419			`// Output`
420			`.timer_host_dataout(timer_host_datain),`
421			`.timer_irq(timer_irq)`
422			`);`
423
424
425			`flash_ctrl flash_ctrl0(// Inputs`
426			`.reset(reset),`
427			`.clk0(clk0),`
428			`.flash_host_addr(host_addr),`
429			`.flash_host_cmd(host_cmd),`
430			`.flash_host_dataout(flash_host_dataout),`
431			`.flash_datain(flash_datain),`
432			`// Outputs`
433			`.flash_host_datain(flash_host_datain),`
434			`.flash_cle(flash_cle),`
435			`.flash_ale(flash_ale),`
436			`.flash_ce(flash_ce),`
437			`.flash_re(flash_re),`
438			`.flash_we(flash_we),`
439			`.flash_wp(flash_wp),`
440			`.flash_rb(flash_rb),`
441			`.flash_irq(flash_irq),`
442			`.flash_dataout(flash_dataout)`
443			`);`
444
445
446
447			`sdram_ctrl sdram_ctrl0(// Inputs`
448			`.clk0(clk0),`
449			`.clk0_2x(clk0_2x),`
450			`.reset(reset),`
451			`.paddr(sdram_addr),`
452			`.cmd(sdram_cmd),`
453			`.dm(host_dm),`
454			`.datain(sdram_datain),`
455			`// Outputs`
456			`.cmdack(cmdack),`
457			`.addr(addr),`
458			`.cs(cs),`
459			`.ras(ras),`
460			`.cas(cas),`
461			`.we(we),`
462			`.dqm(dqm),`
463			`.cke(cke),`
464			`.ba(ba),`
465			`.dataout(sdram_dataout),`
466			`// Inouts`
467			`.dq(dq)`
468			`);`
469
470			`endmodule`