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[/] [embedded_risc/] [trunk/] [Verilog/] [uart.v] - Blame information for rev 27

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1 26 hosseinami 
/*********************************************************
2 
 MODULE:                Sub Level UART Device
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4 
 FILE NAME:     uart.v
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 VERSION:       1.0
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 DATE:          May 14th, 2002
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 AUTHOR:                Hossein Amidi
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 COMPANY:
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 CODE TYPE:     Register Transfer Level
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11 
 DESCRIPTION:   This module is the top level RTL code of UART verilog code.
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13 
 It will instantiate the following blocks in the ASIC:
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15 
 
16 
 Hossein Amidi
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 (C) April 2002
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19 
*********************************************************/
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// DEFINES
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`timescale 1ns / 10ps
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// TOP MODULE
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module uart(// Inputs
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                                reset,
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                                clk0,
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                                uart_addr,
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                                uart_host_addr,
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                           uart_host_cmd,
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                                uart_cmd,
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                                uart_host_datain,
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                                uart_cs,
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                                uart_rd,
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                                uart_wr,
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                                ser_rxd,
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                                uart_datain,
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                                // Outputs
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                                ser_txd,
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                                uart_host_dataout,
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                                uart_dataout
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                                );
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// Parameter
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`include        "parameter.v"
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// Inputs
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input reset;
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input clk0;
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input [padd_size - 1 : 0]uart_addr;
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input [padd_size - 1 : 0]uart_host_addr;
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input [cmd_size - 1 : 0]uart_host_cmd;
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input [cmd_size - 1 : 0]uart_cmd;
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input [data_size - 1 : 0]uart_host_datain;
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input uart_cs;
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input uart_rd;
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input uart_wr;
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input ser_rxd;
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input [Byte_size - 1 : 0]uart_datain;
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// Outputs
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output ser_txd;
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output [data_size - 1 : 0]uart_host_dataout;
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output [Byte_size - 1 : 0]uart_dataout;
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// Signal Declarations
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wire reset;
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wire clk0;
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wire [padd_size - 1 : 0]uart_addr;
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wire [padd_size - 1 : 0]uart_host_addr;
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wire [cmd_size - 1 : 0]uart_host_cmd;
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wire [cmd_size - 1 : 0]uart_cmd;
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wire [data_size - 1 : 0]uart_host_datain;
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wire uart_cs;
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wire uart_rd;
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wire uart_wr;
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wire ser_rxd;
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wire [Byte_size - 1 : 0]uart_datain;
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reg ser_txd;
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reg [data_size - 1 : 0]uart_host_dataout;
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wire [Byte_size - 1 : 0]uart_dataout;
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reg [Byte_size - 1 : 0]ruart_dataout;
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// Internal Registers
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reg [Byte_size - 1 : 0]uart_reg_dataout;
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reg [Byte_size -1 : 0]shift_reg_in;
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reg [Byte_size -1 : 0]shift_reg_out;
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reg [uart_cnt_size - 1 : 0]serin_cnt;
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reg [uart_cnt_size - 1 : 0]serout_cnt;
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reg byte_in;
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reg byte_out;
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// Assignment statments
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assign uart_dataout = ruart_dataout;
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/***************** Internal Register of Uart configuration *******************/
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reg [uart_reg_width - 1 : 0] uart_register [uart_reg_depth - 1 : 0];
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105 
 
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// Circuit for internal Register
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always @(posedge reset or posedge clk0)
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begin
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        if(reset == 1'b1)
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        begin
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                uart_host_dataout <= 32'h0;
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                uart_register[0] <= 32'h0;
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                uart_register[1] <= 32'h0;
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                uart_register[2] <= 32'h0;
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                uart_register[3] <= 32'h0;
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                uart_register[4] <= 32'h0;
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                uart_register[5] <= 32'h0;
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                uart_register[6] <= 32'h0;
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                uart_register[7] <= 32'h0;
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        end
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        else
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        begin
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                if(uart_host_cmd == 3'b010)
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                begin
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                        case(uart_host_addr)
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                                24'h080024: uart_register[0] <= uart_host_datain;
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                                24'h080025: uart_register[1] <= uart_host_datain;
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                                24'h080026: uart_register[2] <= uart_host_datain;
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                                24'h080027: uart_register[3] <= uart_host_datain;
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                                24'h080028: uart_register[4] <= uart_host_datain;
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                                24'h080029: uart_register[5] <= uart_host_datain;
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                                24'h08002A: uart_register[6] <= uart_host_datain;
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                                24'h08002B: uart_register[7] <= uart_host_datain;
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                        endcase
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                end
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                else
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                if(uart_host_cmd == 3'b001)
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                begin
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                        case(uart_host_addr)
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                                24'h080024: uart_host_dataout <= uart_register[0];
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                                24'h080025: uart_host_dataout <= uart_register[1];
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                                24'h080026: uart_host_dataout <= uart_register[2];
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                                24'h080027: uart_host_dataout <= uart_register[3];
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                                24'h080028: uart_host_dataout <= uart_register[4];
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                                24'h080029: uart_host_dataout <= uart_register[5];
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                                24'h08002A: uart_host_dataout <= uart_register[6];
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                                24'h08002B: uart_host_dataout <= uart_register[7];
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                        endcase
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                end
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        end
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end
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// Circuit for reciever side
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always @(posedge reset or posedge clk0)
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begin
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        if(reset == 1'b1)
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        begin
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                shift_reg_in  <= 8'h0;
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        end
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        else
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        if((uart_wr == 1'b1) && (uart_rd == 1'b0) && (byte_in == 1'b0))
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        begin
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                shift_reg_in[7] <= shift_reg_in[6];
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                shift_reg_in[6] <= shift_reg_in[5];
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                shift_reg_in[5] <= shift_reg_in[4];
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                shift_reg_in[4] <= shift_reg_in[3];
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                shift_reg_in[3] <= shift_reg_in[2];
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                shift_reg_in[2] <= shift_reg_in[1];
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                shift_reg_in[1] <= shift_reg_in[0];
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                shift_reg_in[0] <= ser_rxd;
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        end
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        else
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                shift_reg_in <= shift_reg_in;
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end
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always @(posedge reset or posedge clk0)
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begin
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        if(reset == 1'b1)
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                ruart_dataout <= 8'h0;
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        else
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        if((uart_wr == 1'b1) && (uart_rd == 1'b0) && (byte_in == 1'b1))
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        begin
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          ruart_dataout[0] <= shift_reg_in[0];
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          ruart_dataout[1] <= shift_reg_in[1];
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          ruart_dataout[2] <= shift_reg_in[2];
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          ruart_dataout[3] <= shift_reg_in[3];
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          ruart_dataout[4] <= shift_reg_in[4];
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          ruart_dataout[5] <= shift_reg_in[5];
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          ruart_dataout[6] <= shift_reg_in[6];
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          ruart_dataout[7] <= shift_reg_in[7];
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        end
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end
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// Circuit for transmitter side
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always @(posedge reset or posedge clk0)
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begin
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        if(reset == 1'b1)
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        begin
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                shift_reg_out <= 8'h0;
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                ser_txd <= 1'b0;
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        end
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        else
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        if((uart_wr == 1'b0) && (uart_rd == 1'b1) && (byte_out == 1'b0))
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        begin
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                ser_txd <= shift_reg_out[7];
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                shift_reg_out[7] <= shift_reg_out[6];
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                shift_reg_out[6] <= shift_reg_out[5];
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                shift_reg_out[5] <= shift_reg_out[4];
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                shift_reg_out[4] <= shift_reg_out[3];
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                shift_reg_out[3] <= shift_reg_out[2];
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                shift_reg_out[2] <= shift_reg_out[1];
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                shift_reg_out[1] <= shift_reg_out[0];
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        end
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        else
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        if((uart_wr == 1'b0) && (uart_rd == 1'b1) && (byte_out == 1'b1))
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                shift_reg_out <= uart_datain;
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end
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// Serial Input Byte Counter
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always @(posedge reset or posedge clk0)
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begin
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        if(reset == 1'b1)
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        begin
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                serin_cnt <= 3'b000;
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                byte_in <= 1'b0;
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        end
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        else
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        if((uart_cs == 1'b1) && (uart_wr == 1'b1) && (uart_rd == 1'b0))
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                serin_cnt <= serin_cnt + 1;
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        else
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        if(serin_cnt == 3'b111)
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                byte_in <= 1'b1;
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        else
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        begin
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                byte_in <= 1'b0;
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                serin_cnt <= serin_cnt;
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        end
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end
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// Serial Output Byte Counter
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always @(posedge reset or posedge clk0)
249 
begin
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        if(reset == 1'b1)
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        begin
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                serout_cnt <= 3'b000;
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                byte_out <= 1'b0;
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        end
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        else
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        if((uart_cs == 1'b1) && (uart_wr == 1'b0) && (uart_rd == 1'b1))
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                serout_cnt <= serout_cnt + 1;
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        else
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        if(serout_cnt == 3'b111)
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                byte_out <= 1'b1;
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        else
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        begin
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                byte_out <= 1'b0;
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                serout_cnt <= serout_cnt;
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        end
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end
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endmodule

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