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aloy.amber |
-- megafunction wizard: %In-System Sources and Probes%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altsource_probe
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-- ============================================================
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-- File Name: sp.vhd
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-- Megafunction Name(s):
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-- altsource_probe
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 10.1 Build 153 11/29/2010 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2010 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY sp IS
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PORT
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(
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probe : IN STD_LOGIC_VECTOR (510 DOWNTO 0);
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source : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
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);
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END sp;
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ARCHITECTURE SYN OF sp IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0);
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COMPONENT altsource_probe
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GENERIC (
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enable_metastability : STRING;
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instance_id : STRING;
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probe_width : NATURAL;
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sld_auto_instance_index : STRING;
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sld_instance_index : NATURAL;
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source_initial_value : STRING;
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source_width : NATURAL;
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lpm_type : STRING
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);
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PORT (
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probe : IN STD_LOGIC_VECTOR (510 DOWNTO 0);
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source : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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source <= sub_wire0(127 DOWNTO 0);
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altsource_probe_component : altsource_probe
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GENERIC MAP (
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enable_metastability => "NO",
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instance_id => "SP",
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probe_width => 511,
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sld_auto_instance_index => "YES",
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sld_instance_index => 0,
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source_initial_value => " 0",
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source_width => 128,
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lpm_type => "altsource_probe"
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)
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PORT MAP (
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probe => probe,
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source => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO"
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-- Retrieval info: CONSTANT: INSTANCE_ID STRING "SP"
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-- Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "511"
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-- Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
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-- Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
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-- Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
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-- Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "128"
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-- Retrieval info: USED_PORT: probe 0 0 511 0 INPUT NODEFVAL "probe[510..0]"
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-- Retrieval info: USED_PORT: source 0 0 128 0 OUTPUT NODEFVAL "source[127..0]"
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-- Retrieval info: CONNECT: @probe 0 0 511 0 probe 0 0 511 0
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-- Retrieval info: CONNECT: source 0 0 128 0 @source 0 0 128 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sp.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sp.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sp.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sp.bsf TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sp_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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