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[/] [epc_rfid_transponder/] [trunk/] [symbdec.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------     
--
--     Title          : EPC Class1 Gen2 RFID Tag - Symbol Decoder   
--
--     File name      : symbdec.vhd 
--
--     Description    : Tag symbol decoder detects valid frames decoding command 
--                      preambles and frame-syncs.    
--
--     Authors        : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>
--
--     Rev. History   : 21 june 06 - First Draft 
--                                 
-------------------------------------------------------------------------------            
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.numeric_std.all;
library work;
use work.epc_tag.all;
 
 
entity SymbolDecoder is
  generic (
    LOG2_10_TARI_CK_CYC        : integer := 9;  -- Log2(clock cycles for 10 maximum TARI value) (def:
-- Log2(490) = 9 @TCk=520ns)
    DELIMITIER_TIME_CK_CYC_MIN : integer := 22;  -- Min Clock cycles for 12,5 us delimitier
    DELIMITIER_TIME_CK_CYC_MAX : integer := 24);  -- Max Clock cycles for 12,5 us delimitier
 
  port (
    clk      : in  std_logic;
    rst_n    : in  std_logic;
    tdi      : in  std_logic;
    en       : in  std_logic;
    start    : in  std_logic;
    sserror  : out std_logic;
    ssovalid : out std_logic;
    sso      : out std_logic);          -- serial symbol output
 
end SymbolDecoder;
 
 
architecture symbdec1 of SymbolDecoder is
 
  component COUNTERCLR
    generic (
      width : integer);
    port (
      clk    : in  std_logic;
      rst_n  : in  std_logic;
      en     : in  std_logic;
      clear  : in  std_logic;
      outcnt : out std_logic_vector(width-1 downto 0));
  end component;
 
  type RecFSM_t is (st0_Start, st0b_Delimitier, st1_Dat0H, st2_Dat0L, st3_RTcalH, st4_RTcalL, st5_Sym0H, st6_Sym0L, st6b_Sym0L_TR, st7_SymH, st8_SymL, st9_SymH_TR, st10_SymL_TR);
 
  signal StRec, NextStRec                      : RecFSM_t;
  signal CntEn, CntClr                         : std_logic;
  signal CntEn_i, CntClr_i                     : std_logic;
  signal TRCalEn, RTCalEn                      : std_logic;
  signal TRCalEn_i, RTCalEn_i                  : std_logic;
  signal TARI4En, TARI4En_i                    : std_logic;
  signal CntReg, RTCalReg, TRCalReg            : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);
  signal RTCaldiv2Reg, TARI4Reg                : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);
  signal RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2 : std_logic;
  signal Symb_GRTH_TARI4                       : std_logic;
  signal ssovalid_i, sso_i, sserror_i          : std_logic;
  signal DelimitierComparisoOK                 : std_logic;
 
begin  -- Receiver1
 
  RTCaldiv2Reg <= '0' & RTCalReg(LOG2_10_TARI_CK_CYC-1 downto 1);
 
  SYNCRO : process(clk, rst_n)
  begin  -- process
    if clk'event and clk = '1' then
      if rst_n = '0' then
        CntEn    <= '0';
        TRCalEn  <= '0';
        RTCalEn  <= '0';
        TARI4En  <= '0';
        sserror  <= '0';
        ssovalid <= '0';
        sso      <= '0';
        StRec    <= st0_start;
      else
        if en = '1' then
          StRec    <= NextStRec;
          CntEn    <= CntEn_i;
          TRCalEn  <= TRCalEn_i;
          RTCalEn  <= RTCalEn_i;
          TARI4En  <= TARI4En_i;
          CntClr   <= CntClr_i;
          sserror  <= sserror_i;
          ssovalid <= ssovalid_i;
          sso      <= sso_i;
        end if;
      end if;
    end if;
  end process;
 
 
  NEXT_ST : process (StRec, tdi, start, TRCalEn, Symb_GRTH_TARI4, DelimitierComparisoOK)
  begin  -- process NEXT_ST
    NextStRec <= StRec;
    case StRec is
      when st0_Start =>
        if tdi = '0' then
          NextStRec <= st0b_Delimitier;
        end if;
      when st0b_Delimitier =>
        if tdi = '1' then
          if DelimitierComparisoOK = '1' then
            NextStRec <= st1_Dat0H;
          else
            NextStRec <= st0_Start;
          end if;
        end if;
      when st1_Dat0H =>
        if tdi = '0' then
          NextStRec <= st2_Dat0L;
        end if;
      when st2_Dat0L =>
        if tdi = '1' then
          NextStRec <= st3_RTcalH;
        end if;
      when st3_RTcalH =>
        if tdi = '0' then
          NextStRec <= st4_RTcalL;
        end if;
      when st4_RTcalL =>
        if tdi = '1' then
          NextStRec <= st5_Sym0H;
        end if;
      when st5_Sym0H =>
        if tdi = '0' then
          NextStRec <= st6_Sym0L;
        end if;
      when st6_Sym0L =>
        if TRCalEn = '1' then
          NextStRec <= st6b_Sym0L_TR;
        elsif tdi = '1' then
          NextStRec <= st7_SymH;
        end if;
      when st6b_Sym0L_TR =>
        if tdi = '1' then
          NextStRec <= st9_SymH_TR;
        end if;
      when st9_SymH_TR =>
        if tdi = '0' then
          NextStRec <= st10_SymL_TR;
        end if;
      when st10_SymL_TR =>
        if tdi = '1' then
          NextStRec <= st7_SymH;
        end if;
      when st7_SymH =>
        if Symb_GRTH_TARI4 = '1' then
          NextStRec <= st0_Start;
        elsif start = '1'then
          NextStRec <= st0_Start;
        elsif tdi = '0' then
          NextStRec <= st8_SymL;
        end if;
      when st8_SymL =>
        if Symb_GRTH_TARI4 = '1' then
          NextStRec <= st0_Start;
        elsif start = '1' then
          NextStRec <= st0_Start;
        elsif tdi = '1' then
          NextStRec <= st7_SymH;
        end if;
      when others =>
        NextStRec <= st0_start;
    end case;
  end process NEXT_ST;
 
 
  OUTPUT_DEC : process (StRec, tdi, RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2, Symb_GRTH_TARI4)
  begin  -- process OUTPUT_DEC
    CntEn_i    <= '0';
    TRCalEn_i  <= '0';
    RTCalEn_i  <= '0';
    TARI4En_i  <= '0';
    CntClr_i   <= '0';
    sserror_i  <= '0';
    ssovalid_i <= '0';
    sso_i      <= '0';
 
    case StRec is
      when st0_Start =>
        CntClr_i <= '1';
      when st0b_Delimitier =>
        if tdi = '0' then
          CntEn_i <= '1';
        else
          CntClr_i <= '1';
        end if;
      when st1_Dat0H =>
        CntEn_i <= '1';
      when st2_Dat0L =>
        if tdi = '0' then
          CntEn_i <= '1';
        else
          CntClr_i  <= '1';
          TARI4En_i <= '1';
        end if;
      when st3_RTcalH =>
        if tdi = '1' then
          CntEn_i <= '1';
        else
          -- Load RTCal value
          CntClr_i  <= '1';
          RTCalEn_i <= '1';
        end if;
      when st4_RTcalL =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when st5_Sym0H =>
        if tdi = '1' then
          CntEn_i <= '1';
        else
          CntClr_i <= '1';
          if RTCal_GRTH_TRCal = '1' then
            -- Send valid Symbol
            ssovalid_i <= '1';
            if Symb_GRTH_RTCaldiv2 = '1' then
              sso_i <= '1';
            else
              sso_i <= '0';
            end if;
          else
            -- Load TRCal value (Preamble detected ("Query" comm.))
            TRCalEn_i <= '1';
          end if;
        end if;
      when st6_Sym0L =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when st6b_Sym0L_TR =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when st7_SymH =>
        if Symb_GRTH_TARI4 = '1' then
          sserror_i <= '1';
        elsif tdi = '1' then
          CntEn_i <= '1';
        else
          -- Send valid Symbol
          -- CntClr_i   <= '1';
          ssovalid_i <= '1';
          if Symb_GRTH_RTCaldiv2 = '1' then
            sso_i <= '1';
          else
            sso_i <= '0';
          end if;
        end if;
      when st8_SymL =>
        if Symb_GRTH_TARI4 = '1' then
          sserror_i <= '1';
        elsif tdi = '1' then
          CntClr_i <= '1';
        end if;
      when st9_SymH_TR =>
        if tdi = '1' then
          CntEn_i <= '1';
        else
          -- Send valid Symbol
          CntClr_i   <= '1';
          ssovalid_i <= '1';
          if Symb_GRTH_RTCaldiv2 = '1' then
            sso_i <= '1';
          else
            sso_i <= '0';
          end if;
        end if;
      when st10_SymL_TR =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when others => null;
    end case;
  end process OUTPUT_DEC;
 
 
  GRTH1 : process (RTCalReg, CntReg)
  begin  -- process EQUAL
    if RTCalReg > CntReg then
      RTCal_GRTH_TRCal <= '1';
    else
      RTCal_GRTH_TRCal <= '0';
    end if;
  end process GRTH1;
 
  GRTH2 : process (CntReg, RTCaldiv2Reg)
  begin  -- process EQUAL
    if CntReg > RTCaldiv2Reg then
      Symb_GRTH_RTCaldiv2 <= '1';
    else
      Symb_GRTH_RTCaldiv2 <= '0';
    end if;
  end process GRTH2;
 
  GRTH3 : process (CntReg, TARI4Reg)
  begin  -- process EQUAL
    if CntReg > TARI4Reg then
      Symb_GRTH_TARI4 <= '1';
    else
      Symb_GRTH_TARI4 <= '0';
    end if;
  end process GRTH3;
 
  DELIMITIER_COMPARISON : process (CntReg)
  begin  -- process DELIMITIER_COMPARISON
    if conv_integer(CntReg) > DELIMITIER_TIME_CK_CYC_MIN or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MIN then
      if conv_integer(CntReg) < DELIMITIER_TIME_CK_CYC_MAX or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MAX then
        DelimitierComparisoOK <= '1';
      else
        DelimitierComparisoOK <= '0';
      end if;
    else
      DelimitierComparisoOK <= '0';
    end if;
  end process DELIMITIER_COMPARISON;
 
  RTCALR : process (clk, rst_n)
  begin  -- process RTCALREG
    if rst_n = '0' then                 -- asynchronous reset (active low)
      RTCalReg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if RTCalEn = '1' then
        RTCalReg <= CntReg;
      end if;
    end if;
  end process RTCALR;
 
  TRCALR : process (clk, rst_n)
  begin  -- process RTCALREG
    if rst_n = '0' then                 -- asynchronous reset (active low)
      TRCalReg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if TRCalEn = '1' then
        TRCalReg <= CntReg;
      end if;
    end if;
  end process TRCALR;
 
  TARI4R : process (clk, rst_n)
  begin  -- process TARI4R
    if rst_n = '0' then                 -- asynchronous reset (active low)
      TARI4Reg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if TARI4En = '1' then
        TARI4Reg <= CntReg(LOG2_10_TARI_CK_CYC-3 downto 0) & "00";  --Multiplied by 4
      end if;
    end if;
  end process TARI4R;
 
  COUNTERCLR_1 : COUNTERCLR
    generic map (
      width => LOG2_10_TARI_CK_CYC)
    port map (
      clk    => clk,
      rst_n  => rst_n,
      en     => CntEn,
      clear  => CntClr,
      outcnt => CntReg);
 
end symbdec1;

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Subversion Repositories epc_rfid_transponder

[/] [epc_rfid_transponder/] [trunk/] [symbdec.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	erwing	`-------------------------------------------------------------------------------`
2			`-------------------------------------------------------------------------------`
3			`--`
4			`-- Title : EPC Class1 Gen2 RFID Tag - Symbol Decoder`
5			`--`
6			`-- File name : symbdec.vhd`
7			`--`
8			`-- Description : Tag symbol decoder detects valid frames decoding command`
9			`-- preambles and frame-syncs.`
10			`--`
11			`-- Authors : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>`
12			`--`
13			`-- Rev. History : 21 june 06 - First Draft`
14			`--`
15			`-------------------------------------------------------------------------------`
16			`-------------------------------------------------------------------------------`
17
18			`library IEEE;`
19			`use IEEE.STD_LOGIC_1164.all;`
20			`use IEEE.std_logic_unsigned.all;`
21			`use IEEE.STD_LOGIC_ARITH.all;`
22			`use ieee.numeric_std.all;`
23			`library work;`
24			`use work.epc_tag.all;`
25
26
27			`entity SymbolDecoder is`
28			`generic (`
29			`LOG2_10_TARI_CK_CYC : integer := 9; -- Log2(clock cycles for 10 maximum TARI value) (def:`
30			`-- Log2(490) = 9 @TCk=520ns)`
31			`DELIMITIER_TIME_CK_CYC_MIN : integer := 22; -- Min Clock cycles for 12,5 us delimitier`
32			`DELIMITIER_TIME_CK_CYC_MAX : integer := 24); -- Max Clock cycles for 12,5 us delimitier`
33
34			`port (`
35			`clk : in std_logic;`
36			`rst_n : in std_logic;`
37			`tdi : in std_logic;`
38			`en : in std_logic;`
39			`start : in std_logic;`
40			`sserror : out std_logic;`
41			`ssovalid : out std_logic;`
42			`sso : out std_logic); -- serial symbol output`
43
44			`end SymbolDecoder;`
45
46
47			`architecture symbdec1 of SymbolDecoder is`
48
49			`component COUNTERCLR`
50			`generic (`
51			`width : integer);`
52			`port (`
53			`clk : in std_logic;`
54			`rst_n : in std_logic;`
55			`en : in std_logic;`
56			`clear : in std_logic;`
57			`outcnt : out std_logic_vector(width-1 downto 0));`
58			`end component;`
59
60			`type RecFSM_t is (st0_Start, st0b_Delimitier, st1_Dat0H, st2_Dat0L, st3_RTcalH, st4_RTcalL, st5_Sym0H, st6_Sym0L, st6b_Sym0L_TR, st7_SymH, st8_SymL, st9_SymH_TR, st10_SymL_TR);`
61
62			`signal StRec, NextStRec : RecFSM_t;`
63			`signal CntEn, CntClr : std_logic;`
64			`signal CntEn_i, CntClr_i : std_logic;`
65			`signal TRCalEn, RTCalEn : std_logic;`
66			`signal TRCalEn_i, RTCalEn_i : std_logic;`
67			`signal TARI4En, TARI4En_i : std_logic;`
68			`signal CntReg, RTCalReg, TRCalReg : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);`
69			`signal RTCaldiv2Reg, TARI4Reg : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);`
70			`signal RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2 : std_logic;`
71			`signal Symb_GRTH_TARI4 : std_logic;`
72			`signal ssovalid_i, sso_i, sserror_i : std_logic;`
73			`signal DelimitierComparisoOK : std_logic;`
74
75			`begin -- Receiver1`
76
77			`RTCaldiv2Reg <= '0' & RTCalReg(LOG2_10_TARI_CK_CYC-1 downto 1);`
78
79			`SYNCRO : process(clk, rst_n)`
80			`begin -- process`
81			`if clk'event and clk = '1' then`
82			`if rst_n = '0' then`
83			`CntEn <= '0';`
84			`TRCalEn <= '0';`
85			`RTCalEn <= '0';`
86			`TARI4En <= '0';`
87			`sserror <= '0';`
88			`ssovalid <= '0';`
89			`sso <= '0';`
90			`StRec <= st0_start;`
91			`else`
92			`if en = '1' then`
93			`StRec <= NextStRec;`
94			`CntEn <= CntEn_i;`
95			`TRCalEn <= TRCalEn_i;`
96			`RTCalEn <= RTCalEn_i;`
97			`TARI4En <= TARI4En_i;`
98			`CntClr <= CntClr_i;`
99			`sserror <= sserror_i;`
100			`ssovalid <= ssovalid_i;`
101			`sso <= sso_i;`
102			`end if;`
103			`end if;`
104			`end if;`
105			`end process;`
106
107
108			`NEXT_ST : process (StRec, tdi, start, TRCalEn, Symb_GRTH_TARI4, DelimitierComparisoOK)`
109			`begin -- process NEXT_ST`
110			`NextStRec <= StRec;`
111			`case StRec is`
112			`when st0_Start =>`
113			`if tdi = '0' then`
114			`NextStRec <= st0b_Delimitier;`
115			`end if;`
116			`when st0b_Delimitier =>`
117			`if tdi = '1' then`
118			`if DelimitierComparisoOK = '1' then`
119			`NextStRec <= st1_Dat0H;`
120			`else`
121			`NextStRec <= st0_Start;`
122			`end if;`
123			`end if;`
124			`when st1_Dat0H =>`
125			`if tdi = '0' then`
126			`NextStRec <= st2_Dat0L;`
127			`end if;`
128			`when st2_Dat0L =>`
129			`if tdi = '1' then`
130			`NextStRec <= st3_RTcalH;`
131			`end if;`
132			`when st3_RTcalH =>`
133			`if tdi = '0' then`
134			`NextStRec <= st4_RTcalL;`
135			`end if;`
136			`when st4_RTcalL =>`
137			`if tdi = '1' then`
138			`NextStRec <= st5_Sym0H;`
139			`end if;`
140			`when st5_Sym0H =>`
141			`if tdi = '0' then`
142			`NextStRec <= st6_Sym0L;`
143			`end if;`
144			`when st6_Sym0L =>`
145			`if TRCalEn = '1' then`
146			`NextStRec <= st6b_Sym0L_TR;`
147			`elsif tdi = '1' then`
148			`NextStRec <= st7_SymH;`
149			`end if;`
150			`when st6b_Sym0L_TR =>`
151			`if tdi = '1' then`
152			`NextStRec <= st9_SymH_TR;`
153			`end if;`
154			`when st9_SymH_TR =>`
155			`if tdi = '0' then`
156			`NextStRec <= st10_SymL_TR;`
157			`end if;`
158			`when st10_SymL_TR =>`
159			`if tdi = '1' then`
160			`NextStRec <= st7_SymH;`
161			`end if;`
162			`when st7_SymH =>`
163			`if Symb_GRTH_TARI4 = '1' then`
164			`NextStRec <= st0_Start;`
165			`elsif start = '1'then`
166			`NextStRec <= st0_Start;`
167			`elsif tdi = '0' then`
168			`NextStRec <= st8_SymL;`
169			`end if;`
170			`when st8_SymL =>`
171			`if Symb_GRTH_TARI4 = '1' then`
172			`NextStRec <= st0_Start;`
173			`elsif start = '1' then`
174			`NextStRec <= st0_Start;`
175			`elsif tdi = '1' then`
176			`NextStRec <= st7_SymH;`
177			`end if;`
178			`when others =>`
179			`NextStRec <= st0_start;`
180			`end case;`
181			`end process NEXT_ST;`
182
183
184			`OUTPUT_DEC : process (StRec, tdi, RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2, Symb_GRTH_TARI4)`
185			`begin -- process OUTPUT_DEC`
186			`CntEn_i <= '0';`
187			`TRCalEn_i <= '0';`
188			`RTCalEn_i <= '0';`
189			`TARI4En_i <= '0';`
190			`CntClr_i <= '0';`
191			`sserror_i <= '0';`
192			`ssovalid_i <= '0';`
193			`sso_i <= '0';`
194
195			`case StRec is`
196			`when st0_Start =>`
197			`CntClr_i <= '1';`
198			`when st0b_Delimitier =>`
199			`if tdi = '0' then`
200			`CntEn_i <= '1';`
201			`else`
202			`CntClr_i <= '1';`
203			`end if;`
204			`when st1_Dat0H =>`
205			`CntEn_i <= '1';`
206			`when st2_Dat0L =>`
207			`if tdi = '0' then`
208			`CntEn_i <= '1';`
209			`else`
210			`CntClr_i <= '1';`
211			`TARI4En_i <= '1';`
212			`end if;`
213			`when st3_RTcalH =>`
214			`if tdi = '1' then`
215			`CntEn_i <= '1';`
216			`else`
217			`-- Load RTCal value`
218			`CntClr_i <= '1';`
219			`RTCalEn_i <= '1';`
220			`end if;`
221			`when st4_RTcalL =>`
222			`if tdi = '1' then`
223			`CntEn_i <= '1';`
224			`end if;`
225			`when st5_Sym0H =>`
226			`if tdi = '1' then`
227			`CntEn_i <= '1';`
228			`else`
229			`CntClr_i <= '1';`
230			`if RTCal_GRTH_TRCal = '1' then`
231			`-- Send valid Symbol`
232			`ssovalid_i <= '1';`
233			`if Symb_GRTH_RTCaldiv2 = '1' then`
234			`sso_i <= '1';`
235			`else`
236			`sso_i <= '0';`
237			`end if;`
238			`else`
239			`-- Load TRCal value (Preamble detected ("Query" comm.))`
240			`TRCalEn_i <= '1';`
241			`end if;`
242			`end if;`
243			`when st6_Sym0L =>`
244			`if tdi = '1' then`
245			`CntEn_i <= '1';`
246			`end if;`
247			`when st6b_Sym0L_TR =>`
248			`if tdi = '1' then`
249			`CntEn_i <= '1';`
250			`end if;`
251			`when st7_SymH =>`
252			`if Symb_GRTH_TARI4 = '1' then`
253			`sserror_i <= '1';`
254			`elsif tdi = '1' then`
255			`CntEn_i <= '1';`
256			`else`
257			`-- Send valid Symbol`
258			`-- CntClr_i <= '1';`
259			`ssovalid_i <= '1';`
260			`if Symb_GRTH_RTCaldiv2 = '1' then`
261			`sso_i <= '1';`
262			`else`
263			`sso_i <= '0';`
264			`end if;`
265			`end if;`
266			`when st8_SymL =>`
267			`if Symb_GRTH_TARI4 = '1' then`
268			`sserror_i <= '1';`
269			`elsif tdi = '1' then`
270			`CntClr_i <= '1';`
271			`end if;`
272			`when st9_SymH_TR =>`
273			`if tdi = '1' then`
274			`CntEn_i <= '1';`
275			`else`
276			`-- Send valid Symbol`
277			`CntClr_i <= '1';`
278			`ssovalid_i <= '1';`
279			`if Symb_GRTH_RTCaldiv2 = '1' then`
280			`sso_i <= '1';`
281			`else`
282			`sso_i <= '0';`
283			`end if;`
284			`end if;`
285			`when st10_SymL_TR =>`
286			`if tdi = '1' then`
287			`CntEn_i <= '1';`
288			`end if;`
289			`when others => null;`
290			`end case;`
291			`end process OUTPUT_DEC;`
292
293
294			`GRTH1 : process (RTCalReg, CntReg)`
295			`begin -- process EQUAL`
296			`if RTCalReg > CntReg then`
297			`RTCal_GRTH_TRCal <= '1';`
298			`else`
299			`RTCal_GRTH_TRCal <= '0';`
300			`end if;`
301			`end process GRTH1;`
302
303			`GRTH2 : process (CntReg, RTCaldiv2Reg)`
304			`begin -- process EQUAL`
305			`if CntReg > RTCaldiv2Reg then`
306			`Symb_GRTH_RTCaldiv2 <= '1';`
307			`else`
308			`Symb_GRTH_RTCaldiv2 <= '0';`
309			`end if;`
310			`end process GRTH2;`
311
312			`GRTH3 : process (CntReg, TARI4Reg)`
313			`begin -- process EQUAL`
314			`if CntReg > TARI4Reg then`
315			`Symb_GRTH_TARI4 <= '1';`
316			`else`
317			`Symb_GRTH_TARI4 <= '0';`
318			`end if;`
319			`end process GRTH3;`
320
321			`DELIMITIER_COMPARISON : process (CntReg)`
322			`begin -- process DELIMITIER_COMPARISON`
323			`if conv_integer(CntReg) > DELIMITIER_TIME_CK_CYC_MIN or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MIN then`
324			`if conv_integer(CntReg) < DELIMITIER_TIME_CK_CYC_MAX or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MAX then`
325			`DelimitierComparisoOK <= '1';`
326			`else`
327			`DelimitierComparisoOK <= '0';`
328			`end if;`
329			`else`
330			`DelimitierComparisoOK <= '0';`
331			`end if;`
332			`end process DELIMITIER_COMPARISON;`
333
334			`RTCALR : process (clk, rst_n)`
335			`begin -- process RTCALREG`
336			`if rst_n = '0' then -- asynchronous reset (active low)`
337			`RTCalReg <= (others => '0');`
338			`elsif clk'event and clk = '1' then -- rising clock edge`
339			`if RTCalEn = '1' then`
340			`RTCalReg <= CntReg;`
341			`end if;`
342			`end if;`
343			`end process RTCALR;`
344
345			`TRCALR : process (clk, rst_n)`
346			`begin -- process RTCALREG`
347			`if rst_n = '0' then -- asynchronous reset (active low)`
348			`TRCalReg <= (others => '0');`
349			`elsif clk'event and clk = '1' then -- rising clock edge`
350			`if TRCalEn = '1' then`
351			`TRCalReg <= CntReg;`
352			`end if;`
353			`end if;`
354			`end process TRCALR;`
355
356			`TARI4R : process (clk, rst_n)`
357			`begin -- process TARI4R`
358			`if rst_n = '0' then -- asynchronous reset (active low)`
359			`TARI4Reg <= (others => '0');`
360			`elsif clk'event and clk = '1' then -- rising clock edge`
361			`if TARI4En = '1' then`
362			`TARI4Reg <= CntReg(LOG2_10_TARI_CK_CYC-3 downto 0) & "00"; --Multiplied by 4`
363			`end if;`
364			`end if;`
365			`end process TARI4R;`
366
367			`COUNTERCLR_1 : COUNTERCLR`
368			`generic map (`
369			`width => LOG2_10_TARI_CK_CYC)`
370			`port map (`
371			`clk => clk,`
372			`rst_n => rst_n,`
373			`en => CntEn,`
374			`clear => CntClr,`
375			`outcnt => CntReg);`
376
377			`end symbdec1;`