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[/] [erp/] [web_uploads/] [ERPverilogcore.txt] - Blame information for rev 6

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// Educational (8 Bit) RISC Processor
// Just like a barebone 8 Bit CPU
//
//
// Designed By:
// Asif Nawaz, Shahzad Jehangir & Ishaq Muhammad - 25 July 2004
// asifnawaz@ieee.org, shahzad_j_k@yahoo.com,ishaq_tehk@yahoo.com
//
// The design originally started out as a CPLD design but due to certain limitations the core was redesigned for FPGA
 
// Below given 8 Bit processor core is fully synthesizable and successfully tested on Xess Spartan 2 FPGA development board
 
 
 
/************************************/
                /*CPU Instructions*/
 
`define         Multiply                        4'b0000
`define         Move                            4'b0001
`define         Add                             4'b0010
`define         Sub                             4'b0011
`define         AND                             4'b0100
`define         NAND                            4'b0101
`define         OR                              4'b0110
`define         NOR                             4'b0111
`define         Load                            4'b1000
`define         Ror                             4'b1010
`define         Rol                             4'b1011
`define         Not                             4'b1100
`define         Jump                            4'b1111
`define         Shl                             4'b1101
`define         Shr                             4'b1110
/*************************************/
 
 
 
 
 
/************************************/
                /*Alu Instructions*/
 
`define         AluMultiply                     4'b0000
`define         AluAdd                  4'b0010
`define         AluSub                  4'b0011
`define         AluAND                  4'b0100
`define         AluNAND                 4'b0101
`define         AluOR                           4'b0110
`define         AluNOR                  4'b0111
`define         AluRor                  4'b1010
`define         AluRol                          4'b1011
`define         AluNot                  4'b1100
`define         AluShl                          4'b1101
`define         AluShr                          4'b1110
/*************************************/
 
//Top level module proc which include the code for control unit and instantiate all other sub modules.
 
            //Externally generated inputs
module proc (Resetp, Holdp, Clockp,
 
                        //Input&output ports just for simulation purpose
                        led1h, led2h, Clock, PCount, pcoutput, Count, R0, R1, R2, R3, A, G);
 
//Port Decleration
 
        input Clockp;           //Externally generated clock signal
        input Resetp;           //Externally generated active high Reset signal
        input Holdp;            //Externally generated active low Hold signal
 
 
//The below given ports are only for simulation purpose
 
        output [6:0] led1h, led2h;      //input for the seven segment LED display
        output [7:0] PCount;            //8-bit output from the program counter
        output [15:0] pcoutput;         //16-bit instruction fetched from RAM
        output [1:0] Count;             //2-bit output from the machine cycle counter
 
        output [7:0] R0, R1, R2, R3, A, G;      //8-bit registers
        output Clock;                           //output clock signal for simulation
 
 
//Variables of type reg declaration
 
reg [7:0] BusWires;             //Used to store value for bus BusWires
reg [7:0] Exe;                  //Used to store the value to be displayed on 7 segment display
reg [7:0] Data;                 //Used to store the decoded data from 16-bit instruction
reg [7:0] Jmp;                  //Used to store the jump address
reg [1 : 0] Rx, Ry;             //Used to store the 2-bit value Rx & Ry, which act as input for 2to4 decoder
reg [3 : 0] F;                  //Used to store the 4-bit operand of the  16-bit instruction
reg [3:0] AddSub;               //Store 4-bit value which identify operation to be performed by ALU
reg [0:3] Rin, Rout;            //Store 4-bit value which identify one of the 4 registers to be activated for a given operation
reg  Done;                      //Store 1-bit value which identify the successful execution of an instruction
reg  Ain, Gin;                  //Store two 1-bit values and are used to save data in the A and G register
reg  Extern, Gout;              //Store two 1-bit values and are used in bus BusWires implementation
reg  Jset;                      //Store 1-bit value and is used for the jump instruction
 
//Variables of type wire declaration
 
wire [7:0] Sum;         //8-bit signal hold the output result from ALU
wire catch;             //1-bit enable signal for decoding of 16-bit instruction
wire JZ;                //1-bit signal used for jump instruction
wire [1:0] Count;       //2-bit output signal from machine cycle counter
wire [3:0] I;           //4-bit signal which identify the instruction function
wire [0:3] Xreg, Y;     //4-bit signal for the activation of any register form the 4 registers
 
wire [7:0] R0, R1, R2, R3, A, G;        //These 8 bit signals used to carry data for these registers
wire [7:0] PCount;                      //8-bit output signal form the program counter
wire [1:8] FuncReg;                     //8-bit signal for control unit
wire [1:8] Func;                        //8-bit signal for control unit
wire [15:0] pcoutput;                   //16-bit signal from the RAM
wire [6:0] led1, led2, led1h, led2h;    //7-bit signal for Display unit
 
 
//1-bit signal used for various operations
        wire  Clock, ClockS, Reset, Hold, Clockp, Resetp, Locked;
 
// Delay Locked Loop Buffer
 
        dll dll(Clockp, ClockS, Locked);
 
// Assign Clockp signal to Clock wire
 
        assign Clock = Locked ? ClockS : 1'b0 ;
 
// Input Buffers for Reset and Hold
 
        IBUF rst(.I(Resetp), .O(Reset));
        IBUF hld(.I(Holdp), .O(Hold));
 
// Output Buffers for Display
 
        OBUF led10(.I(led1[0]), .O(led1h[0]));
        OBUF led11(.I(led1[1]), .O(led1h[1]));
        OBUF led12(.I(led1[2]), .O(led1h[2]));
        OBUF led13(.I(led1[3]), .O(led1h[3]));
        OBUF led14(.I(led1[4]), .O(led1h[4]));
        OBUF led15(.I(led1[5]), .O(led1h[5]));
        OBUF led16(.I(led1[6]), .O(led1h[6]));
 
        OBUF led20(.I(led2[0]), .O(led2h[0]));
        OBUF led21(.I(led2[1]), .O(led2h[1]));
        OBUF led22(.I(led2[2]), .O(led2h[2]));
        OBUF led23(.I(led2[3]), .O(led2h[3]));
        OBUF led24(.I(led2[4]), .O(led2h[4]));
        OBUF led25(.I(led2[5]), .O(led2h[5]));
        OBUF led26(.I(led2[6]), .O(led2h[6]));
 
 
// Clear Signal generation
 
        wire Clear = Reset | (~Locked) ;
 
//Program Counter
 
        pcounter progcounter (Hold, Clear, Clock, Jmp, Jset, PCount, cmd, JZ);
 
//State Machine Counter
 
        upcount counter (Clear, Clock, Count, cmd, catch);
 
//Read RAM
 
        Ram ramreadload(Clock, cmd, PCount, Reset, pcoutput, catch );
 
 
//ALU
        alu alu(AddSub, A, BusWires, Sum);
 
//LED Display
 
        Display Dis1(Exe[3:0], Clock, Done, led1);
        Display Dis2(Exe[7:4], Clock, Done, led2);
 
//Control Unit
        //Instruction Decoding
 
        always @(catch or pcoutput)
                begin
                        F = pcoutput[15:12];
                        Rx = pcoutput[11:10];
                        Ry = pcoutput[9:8];
                        Data = pcoutput[7:0];
 
                end
 
        assign Func = {F, Rx, Ry};
        wire FRin = catch & ~Count[1] & ~Count[0];
        regn functionreg (Func, FRin, Clock, FuncReg);
 
        assign I = FuncReg[1:4];
        dec2to4 decX (FuncReg[5:6], 1'b1, Xreg);
        dec2to4 decY (FuncReg[7:8], 1'b1, Y);
 
        //Instruction implementation
 
        always @(Count or I or Xreg or Y  or Data or BusWires or G or JZ)
 
        begin
                        Extern = 1'b0;
                        Done = 1'b0;
                        Ain = 1'b0;
                        Gin = 1'b0;
                        Gout = 1'b0;
                        AddSub = 3'b000;
                        Rin = 4'b0;
                        Rout = 4'b0;
 
        begin
 
 
                        case (Count)
 
                                2'b00: ;        //No operation in T0
 
                                2'b01:          //define signals in time step T1
 
                                begin
                                        if (JZ == 1)                    // Check Jmp
                                                begin
                                                Jset = 1'b0;
                                                Jmp = 8'b00000000;
                                                end
 
                                        case (I)
 
                                                `Jump:                  //Jump
                                                begin
 
                                                        Jset = 1'b1;
                                                        Jmp = Data;
                                                        Done = 1'b1;
                                                        Exe = Data;
 
                                                end
 
                                                `Load:                  //Load
                                                begin
 
                                                        Extern = 1;
                                                        Rin = Xreg;
                                                        Done = 1'b1;
                                                        Exe = Data;
 
                                                end
 
                                                `Move:                  //Move
                                                begin
 
                                                        Rout = Y;
                                                        Rin = Xreg;
                                                        Done = 1'b1;
                                                        Exe = BusWires;
 
                                                end
 
                                                `Add, `Sub, `Multiply, `And, `Or, `Not, `Nor, `Nand, `Ror, `Rol, `Shl, `Shr:    //Add, Sub, Logical, Shift
                                                begin
                                                        Rout = Xreg;
                                                        Ain = 1'b1;
                                                end
 
                                            default: ;
 
                                           endcase
                                        end
 
                                  2'b10:   //define signals in time step T2
 
                                        case (I)
 
                                                `Not:                   //Not
                                                 begin
                                                        AddSub = `AluNot;
                                                        Gin = 1'b1;
                                                 end
 
                                                `Ror:                   //Rotate Right
                                                 begin
                                                        AddSub = `AluRor;
                                                        Gin = 1'b1;
                                                 end
 
                                                `Rol:                   //Rotate Left
                                                 begin
                                                        AddSub = `AluRol;
                                                        Gin = 1'b1;
                                                 end
 
                                                `Shl:                   //Shift Left
                                                 begin
                                                        AddSub = `AluShl;
                                                        Gin = 1'b1;
                                                 end
 
                                                `Shr:                   //Shift Right
                                                 begin
                                                        AddSub = `AluShl;
                                                        Gin = 1'b1;
                                                 end
 
                                                `Add:                   //Add
                                                 begin
                                                        Rout = Y;
                                                        AddSub = `AluAdd;
                                                        Gin = 1'b1;
                                                 end
 
                                                 `Sub:                  //Sub
                                                 begin
                                                        Rout = Y;
                                                        AddSub = `AluSub;
                                                        Gin = 1'b1;
                                                 end
 
                                                 `Multiply:             //Multiplication
                                                 begin
                                                        Rout = Y;
                                                        AddSub = `AluMultiply;
                                                        Gin = 1'b1;
                                                 end
 
                                                 `And:                  //and
                                                 begin
                                                        Rout = Y;
                                                        AddSub = `AluAnd;
                                                        Gin = 1'b1;
                                                 end
 
                                                 `Nand:                 //nand
                                                 begin
                                                        Rout=Y;
                                                        AddSub = `AluNand;
                                                        Gin=1'b1;
                                                 end
 
                                                 `Or:                   //or
                                                 begin
                                                        Rout=Y;
                                                        AddSub = `AluOr;
                                                        Gin=1'b1;
                                                 end
 
                                                 `Nor:                  //nor
                                                 begin
                                                        Rout=Y;
                                                        AddSub = `AluNor;
                                                        Gin=1'b1;
                                                 end
 
                                                 default: ;
 
 
                                           endcase
 
                                        2'b11:          //define signals in time step T2
                                        begin
 
                                                case (I)
 
                                                `Add, `Sub, `Multiply:                  // Add,Sub
                                                begin
                                                        Gout = 1'b1;
                                                        Rin = Xreg;
                                                        Done = 1'b1;
                                                        Exe = G;
                                                end
 
                                                `And, `Or, `Nand, `Nor, `Not:           //And, Or, Nand, Nor, Not
                                                begin
                                                        Gout = 1'b1;
                                                        Rin = Xreg;
                                                        Done = 1'b1;
                                                        Exe = G;
                                                end
 
                                                `Ror, `Rol, `Shl, `Shr:                 //Rotate right, Rotate left, Shift left, Shift right
                                                 begin
                                                        Gout = 1'b1;
                                                        Rin = Xreg;
                                                        Done = 1'b1;
                                                        Exe = G;
                                                end
 
                                                default: ;
 
                                                endcase
 
                                        end
                                endcase
                end
        end
 
//Register Creation
 
        regn reg_0 (BusWires[7:0], Rin[0], Clock, R0);
        regn reg_1 (BusWires[7:0], Rin[1], Clock, R1);
        regn reg_2 (BusWires[7:0], Rin[2], Clock, R2);
        regn reg_3 (BusWires[7:0], Rin[3], Clock, R3);
 
        regn reg_A (BusWires, Ain, Clock, A);
 
        regn reg_G (Sum, Gin, Clock, G);
 
 
//8 Bit Bus BusWires Implementation using Multiplexer
 
        wire [1:6] Sel = {Rout, Gout, Extern};
 
        always @(Sel or R0 or R1 or R2 or R3 or G or Data)
        begin
        if (Sel == 6'b100000)
                BusWires = R0;
        else if (Sel == 6'b010000)
                BusWires = R1;
        else if (Sel == 6'b001000)
                BusWires = R2;
        else if (Sel == 6'b000100)
                BusWires = R3;
        else if (Sel == 6'b000010)
                BusWires = G;
        else if (Sel == 6'b000001)
                BusWires = Data;
        else
                BusWires = 8'bz;
 
        end
 
endmodule
 
 
//Machine Cycle(T) Counter
 
module upcount(Clear, Clock, Q, cmd, catch);
 
        input Clear, Clock, cmd, catch;
        output [1:0] Q;
 
        wire Clear, Clock, cmd, catch;
        reg [1:0] Q;
 
        reg [3:0] RT1;
 
 
        always @(posedge Clock)
        begin
                        if (Clear == 1)
                        begin
                                Q <= 2'b00;
                                RT1 <= 4'b0000;
                        end
 
                        else if (cmd == 0)
                        begin
                                Q <= 2'b00;
                                RT1 <= 4'b0000;
                        end
 
                        else
                        begin
                                if (catch == 1'b1)
                                begin
                                        if (RT1 < 8'b0100)
                                        begin
                                                RT1 <= RT1 + 1;
                                                Q <= Q + 1 ;
                                        end
 
                                        else if (RT1 == 8'b1111)
                                        begin
                                                RT1 <= 4'b0100;
                                        end
 
                                        else
                                                RT1 <= RT1 + 1;
                                end
                                else
                                begin
                                        Q <= 2'b0;
                                        RT1 <= 4'b0000;
                                end
                        end
        end
 
 
endmodule
 
 
//2-4 Decoder
 
module dec2to4(W, En, Y);
        input [1:0] W;
        input En;
 
        wire [1:0] W;
        wire En;
 
        output [0:3] Y;
        reg [0:3] Y;
 
        always @(W or En)
        begin
                if (En == 1)
                        case (W)
                                0: Y = 4'b1000;
                                1: Y = 4'b0100;
                                2: Y = 4'b0010;
                                3: Y = 4'b0001;
                        endcase
                else
                        Y = 4'bz;
        end
endmodule
 
 
//8-Bit Register
 
module regn(R, Rin, Clock, Q);
        parameter n = 8;
 
        input [n-1:0] R;
        input Rin, Clock;
 
        wire [n-1:0] R;
        wire Rin, Clock;
 
        output [n-1:0] Q;
        reg [n-1:0] Q;
 
        always @(posedge Clock)
                if (Rin)
                        Q <= R;
 
endmodule
 
// 40K Block SRAM
//Read Ram
module Ram(Clock, cmd, PcAddr, Reset, Inst, En);
 
        input Clock, cmd;
        input [7:0] PcAddr;
        input Reset;
        output [15:0] Inst;
        output En;
 
        wire Clock, cmd;
        wire [7:0] PcAddr;
        wire Reset;
 
        wire [15:0] Inst;
        reg En, We, stop;
 
        reg [7:0]  WAddr, S;
        reg [15:0] WData;
        reg [15:0] Memory [0:10];
        reg enable, DoJob;
 
        wire [7:0] Store;
 
        integer  count;
 
        always @(Reset)
        begin
                if (Reset == 1)
                        begin
                                Memory[0] =     16'h80FA;
                                Memory[1] =     16'h84F5;
                                Memory[2] =     16'h8822;
                                Memory[3] =     16'h2400;
                                Memory[4] =     16'h1D00;
                                Memory[5] =     16'h3B00;
                                Memory[6] =     16'h4400;
                                Memory[7] =     16'h5400;
                                Memory[8] =     16'h6400;
                                Memory[9] =     16'h7400;
                                Memory[10] =    16'hF409;
                                enable = 1;
 
                        end
                else
                        begin
                                enable = 0;
                        end
        end
 
 
        always @(posedge Clock)
        begin
        if (Reset == 1)
                begin
                        if (enable == 1)
                        begin
                                if (count <= 10)
                                begin
 
                                WData = Memory[count];
                                WAddr <= WAddr + 1;
                                count <= count + 1;
                                DoJob = 1'b1;
                                end
 
                        end
                end
 
        else
                begin
 
                DoJob = 1'b0;
                count <= 0;
                WAddr <= 8'b0;
                WData = 16'b0;
                En = cmd;
                end
 
        end
 
        always @(negedge Clock)
        begin
                if (DoJob == 1)
                begin
                        stop = 1'b1;
                        We = 1'b1;
                        S = WAddr;
                end
                else if (cmd == 1)
                begin
                        stop = 1'b1;
                        We = 1'b0;
                        S = PcAddr;
 
                end
                else
                begin
                        stop = 1'b0;
                        We = 1'b0;
                end
        end
 
        RAMB4_S16 ram(.DO(Inst), .ADDR(S), .CLK(Clock), .DI(WData),
                                                .EN(stop), .RST(1'b0), .WE(We));
 
endmodule
 
//Program Counter
 
module pcounter(HButton, ClearCr, Clock, Jmp, Jset, Q1, cmd, Jz);
 
        input ClearCr, Clock;
        input HButton;
        input Jset;
        input [7:0] Jmp;
 
        wire ClearCr, Clock;
        wire HButton;
        wire Jset;
        wire [7:0] Jmp;
 
        output [7:0] Q1;
        output cmd;
        output Jz;
 
        reg [7:0] Q1;
 
        reg  work, cmd, Jz;
 
 
        always @(posedge Clock)
        begin
 
                if (ClearCr == 1)
                begin
                        Q1 <= 0;
                        work = 1'b0;
                end
 
                else    if (HButton == 0)
                begin
                        if (work != 1'b1)
                        begin
                        cmd = 1'b1;
                        work = 1'b1;
                                begin
                                if (Jset == 1)
                                        begin
                                        Q1 <= Jmp;
                                        Jz = 1'b1;
                                        end
                                else
                                        Q1 <= Q1 + 1 ;
                                end
                        end
                end
                else
                begin
                        cmd = 1'b0;
                        work = 1'b0;
                        Jz = 1'b0;
                end
        end
 
endmodule
 
 
 
//Arthematic Logic Unit
 
module alu (Inst, A, BusWires, Result);
 
        input [3:0] Inst;
        input [7:0] A, BusWires;
 
        wire [3:0] Inst;
        wire [7:0] A, BusWires;
 
        output [7:0] Result;
        //output Cout, Zout, Sout;
 
        reg [7:0] Result;
        reg Zout, Sout, Cout;
 
        always @(Inst  or A or BusWires or Result)
 
        begin
                Zout    = 1'b0;
                Sout    = 1'b0;
                Cout = 1'b0;
                Result = 8'b0;
 
 
        case (Inst)  // synopsis  parallel_case
 
 
                `AluMultiply:
                                        begin
                                        {Cout,Result}  = (A * BusWires);
                                        //Cout = Result[8];
                                        if (Result == 8'h00)
                                        Zout = 1'b1;
                                        if (Result[7] == 1)
                                        Sout = 1'b1;
                                        end
 
                `AluShl:                Result = {A[6:0], 1'b0};
                `AluShr:                Result = {1'b0, A[7:1]};
 
                `AluRol:                Result = {A[6:0], A[7]};
                `AluRor:                Result = {A[0], A[7:1]};
 
                `AluAdd:                begin
                                        {Cout,Result}  = (A + BusWires);
                                        //Cout = Result[8];
                                        if (Result == 8'h00)
                                        Zout = 1'b1;
                                        if (Result[7] == 1)
                                        Sout = 1'b1;
                                        end
 
                `AluSub:                begin
                                        {Cout,Result}  = (A - BusWires) ;
                                        //Cout = Result[8];
                                        if (Result == 8'h00)
                                        Zout = 1'b1;
                                        if (Result[7] == 1)
                                        Sout = 1'b1;
                                        end
 
                `AluAnd:                Result =   A & BusWires;
                `AluNand:               Result =  ~(A & BusWires);
                `AluOr:                 Result =   A | BusWires;
                `AluNor:                Result =  ~(A | BusWires);
                `AluNot:                Result =        ~(A);
 
                default:                begin
                                                Zout    = 1'b0;
                                                Sout    = 1'b0;
                                                Cout = 1'b0;
                                                Result = 8'b0;
                                        end
 
 
        endcase
 
        end
 
endmodule
 
 
 
 
 
/* Led: The 7 segment display */
 
module Display(buscontents, clk, Done, led);
 
        input [3:0] buscontents;
        input clk, Done;
 
        wire [3:0] buscontents;
        wire clk, Done;
 
        output [6:0] led;
 
        reg[6:0]        led;
 
        always @ (posedge clk)
                if (Done == 1)
                begin
                        case (buscontents)   // synopsis full_case parallel_case
 
                                4'b0000: led = 7'b1110111;
                                4'b0001: led = 7'b0010010;
                                4'b0010: led = 7'b1011101;
                                4'b0011: led = 7'b1011011;
                                4'b0100: led = 7'b0111010;
                                4'b0101: led = 7'b1101011;
                                4'b0110: led = 7'b1101111;
                                4'b0111: led = 7'b1010010;
                                4'b1000: led = 7'b1111111;
                                4'b1001: led = 7'b1111011;
                                4'b1010: led = 7'b1111110;
                                4'b1011: led = 7'b0101111;
                                4'b1100: led = 7'b0001101;
                                4'b1101: led = 7'b0011111;
                                4'b1110: led = 7'b1101101;
                                4'b1111: led = 7'b1101100;
                        endcase
                end
 
endmodule
 
 
//   Delay Lock Loops and Global clock buffers instantiation
 
module dll(CLKIN, CLK1X, LOCKED2X);
 
input CLKIN;
output CLK1X, LOCKED2X;
 
wire CLK1X;
 
wire CLKIN_w, CLK1X_dll, LOCKED2X;
 
 
        IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));
 
        CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK1X), .RST(1'b0),
                      .CLK0(CLK1X_dll), .CLK90(), .CLK180(), .CLK270(),
                      .CLK2X(), .CLKDV(), .LOCKED(LOCKED2X));
 
        BUFG   clk2xg (.I(CLK1X_dll),  .O(CLK1X));
 
        //OBUF   lckpad (.I(LOCKED2X), .O(LOCKED));
 
endmodule

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[/] [erp/] [web_uploads/] [ERPverilogcore.txt] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	root	`// Educational (8 Bit) RISC Processor`
2			`// Just like a barebone 8 Bit CPU`
3			`//`
4			`//`
5			`// Designed By:`
6			`// Asif Nawaz, Shahzad Jehangir & Ishaq Muhammad - 25 July 2004`
7			`// asifnawaz@ieee.org, shahzad_j_k@yahoo.com,ishaq_tehk@yahoo.com`
8			`//`
9			`// The design originally started out as a CPLD design but due to certain limitations the core was redesigned for FPGA`
10
11			`// Below given 8 Bit processor core is fully synthesizable and successfully tested on Xess Spartan 2 FPGA development board`
12
13
14
15			`/************************************/`
16			`/CPU Instructions/`
17
18			`define Multiply 4'b0000
19			`define Move 4'b0001
20			`define Add 4'b0010
21			`define Sub 4'b0011
22			`define AND 4'b0100
23			`define NAND 4'b0101
24			`define OR 4'b0110
25			`define NOR 4'b0111
26			`define Load 4'b1000
27			`define Ror 4'b1010
28			`define Rol 4'b1011
29			`define Not 4'b1100
30			`define Jump 4'b1111
31			`define Shl 4'b1101
32			`define Shr 4'b1110
33			`/*************************************/`
34
35
36
37
38
39			`/************************************/`
40			`/Alu Instructions/`
41
42			`define AluMultiply 4'b0000
43			`define AluAdd 4'b0010
44			`define AluSub 4'b0011
45			`define AluAND 4'b0100
46			`define AluNAND 4'b0101
47			`define AluOR 4'b0110
48			`define AluNOR 4'b0111
49			`define AluRor 4'b1010
50			`define AluRol 4'b1011
51			`define AluNot 4'b1100
52			`define AluShl 4'b1101
53			`define AluShr 4'b1110
54			`/*************************************/`
55
56			`//Top level module proc which include the code for control unit and instantiate all other sub modules.`
57
58			`//Externally generated inputs`
59			`module proc (Resetp, Holdp, Clockp,`
60
61			`//Input&output ports just for simulation purpose`
62			`led1h, led2h, Clock, PCount, pcoutput, Count, R0, R1, R2, R3, A, G);`
63
64			`//Port Decleration`
65
66			`input Clockp; //Externally generated clock signal`
67			`input Resetp; //Externally generated active high Reset signal`
68			`input Holdp; //Externally generated active low Hold signal`
69
70
71			`//The below given ports are only for simulation purpose`
72
73			`output [6:0] led1h, led2h; //input for the seven segment LED display`
74			`output [7:0] PCount; //8-bit output from the program counter`
75			`output [15:0] pcoutput; //16-bit instruction fetched from RAM`
76			`output [1:0] Count; //2-bit output from the machine cycle counter`
77
78			`output [7:0] R0, R1, R2, R3, A, G; //8-bit registers`
79			`output Clock; //output clock signal for simulation`
80
81
82			`//Variables of type reg declaration`
83
84			`reg [7:0] BusWires; //Used to store value for bus BusWires`
85			`reg [7:0] Exe; //Used to store the value to be displayed on 7 segment display`
86			`reg [7:0] Data; //Used to store the decoded data from 16-bit instruction`
87			`reg [7:0] Jmp; //Used to store the jump address`
88			`reg [1 : 0] Rx, Ry; //Used to store the 2-bit value Rx & Ry, which act as input for 2to4 decoder`
89			`reg [3 : 0] F; //Used to store the 4-bit operand of the 16-bit instruction`
90			`reg [3:0] AddSub; //Store 4-bit value which identify operation to be performed by ALU`
91			`reg [0:3] Rin, Rout; //Store 4-bit value which identify one of the 4 registers to be activated for a given operation`
92			`reg Done; //Store 1-bit value which identify the successful execution of an instruction`
93			`reg Ain, Gin; //Store two 1-bit values and are used to save data in the A and G register`
94			`reg Extern, Gout; //Store two 1-bit values and are used in bus BusWires implementation`
95			`reg Jset; //Store 1-bit value and is used for the jump instruction`
96
97			`//Variables of type wire declaration`
98
99			`wire [7:0] Sum; //8-bit signal hold the output result from ALU`
100			`wire catch; //1-bit enable signal for decoding of 16-bit instruction`
101			`wire JZ; //1-bit signal used for jump instruction`
102			`wire [1:0] Count; //2-bit output signal from machine cycle counter`
103			`wire [3:0] I; //4-bit signal which identify the instruction function`
104			`wire [0:3] Xreg, Y; //4-bit signal for the activation of any register form the 4 registers`
105
106			`wire [7:0] R0, R1, R2, R3, A, G; //These 8 bit signals used to carry data for these registers`
107			`wire [7:0] PCount; //8-bit output signal form the program counter`
108			`wire [1:8] FuncReg; //8-bit signal for control unit`
109			`wire [1:8] Func; //8-bit signal for control unit`
110			`wire [15:0] pcoutput; //16-bit signal from the RAM`
111			`wire [6:0] led1, led2, led1h, led2h; //7-bit signal for Display unit`
112
113
114			`//1-bit signal used for various operations`
115			`wire Clock, ClockS, Reset, Hold, Clockp, Resetp, Locked;`
116
117			`// Delay Locked Loop Buffer`
118
119			`dll dll(Clockp, ClockS, Locked);`
120
121			`// Assign Clockp signal to Clock wire`
122
123			`assign Clock = Locked ? ClockS : 1'b0 ;`
124
125			`// Input Buffers for Reset and Hold`
126
127			`IBUF rst(.I(Resetp), .O(Reset));`
128			`IBUF hld(.I(Holdp), .O(Hold));`
129
130			`// Output Buffers for Display`
131
132			`OBUF led10(.I(led1[0]), .O(led1h[0]));`
133			`OBUF led11(.I(led1[1]), .O(led1h[1]));`
134			`OBUF led12(.I(led1[2]), .O(led1h[2]));`
135			`OBUF led13(.I(led1[3]), .O(led1h[3]));`
136			`OBUF led14(.I(led1[4]), .O(led1h[4]));`
137			`OBUF led15(.I(led1[5]), .O(led1h[5]));`
138			`OBUF led16(.I(led1[6]), .O(led1h[6]));`
139
140			`OBUF led20(.I(led2[0]), .O(led2h[0]));`
141			`OBUF led21(.I(led2[1]), .O(led2h[1]));`
142			`OBUF led22(.I(led2[2]), .O(led2h[2]));`
143			`OBUF led23(.I(led2[3]), .O(led2h[3]));`
144			`OBUF led24(.I(led2[4]), .O(led2h[4]));`
145			`OBUF led25(.I(led2[5]), .O(led2h[5]));`
146			`OBUF led26(.I(led2[6]), .O(led2h[6]));`
147
148
149			`// Clear Signal generation`
150
151			`wire Clear = Reset \| (~Locked) ;`
152
153			`//Program Counter`
154
155			`pcounter progcounter (Hold, Clear, Clock, Jmp, Jset, PCount, cmd, JZ);`
156
157			`//State Machine Counter`
158
159			`upcount counter (Clear, Clock, Count, cmd, catch);`
160
161			`//Read RAM`
162
163			`Ram ramreadload(Clock, cmd, PCount, Reset, pcoutput, catch );`
164
165
166			`//ALU`
167			`alu alu(AddSub, A, BusWires, Sum);`
168
169			`//LED Display`
170
171			`Display Dis1(Exe[3:0], Clock, Done, led1);`
172			`Display Dis2(Exe[7:4], Clock, Done, led2);`
173
174			`//Control Unit`
175			`//Instruction Decoding`
176
177			`always @(catch or pcoutput)`
178			`begin`
179			`F = pcoutput[15:12];`
180			`Rx = pcoutput[11:10];`
181			`Ry = pcoutput[9:8];`
182			`Data = pcoutput[7:0];`
183
184			`end`
185
186			`assign Func = {F, Rx, Ry};`
187			`wire FRin = catch & ~Count[1] & ~Count[0];`
188			`regn functionreg (Func, FRin, Clock, FuncReg);`
189
190			`assign I = FuncReg[1:4];`
191			`dec2to4 decX (FuncReg[5:6], 1'b1, Xreg);`
192			`dec2to4 decY (FuncReg[7:8], 1'b1, Y);`
193
194			`//Instruction implementation`
195
196			`always @(Count or I or Xreg or Y or Data or BusWires or G or JZ)`
197
198			`begin`
199			`Extern = 1'b0;`
200			`Done = 1'b0;`
201			`Ain = 1'b0;`
202			`Gin = 1'b0;`
203			`Gout = 1'b0;`
204			`AddSub = 3'b000;`
205			`Rin = 4'b0;`
206			`Rout = 4'b0;`
207
208			`begin`
209
210
211			`case (Count)`
212
213			`2'b00: ; //No operation in T0`
214
215			`2'b01: //define signals in time step T1`
216
217			`begin`
218			`if (JZ == 1) // Check Jmp`
219			`begin`
220			`Jset = 1'b0;`
221			`Jmp = 8'b00000000;`
222			`end`
223
224			`case (I)`
225
226			`Jump: //Jump
227			`begin`
228
229			`Jset = 1'b1;`
230			`Jmp = Data;`
231			`Done = 1'b1;`
232			`Exe = Data;`
233
234			`end`
235
236			`Load: //Load
237			`begin`
238
239			`Extern = 1;`
240			`Rin = Xreg;`
241			`Done = 1'b1;`
242			`Exe = Data;`
243
244			`end`
245
246			`Move: //Move
247			`begin`
248
249			`Rout = Y;`
250			`Rin = Xreg;`
251			`Done = 1'b1;`
252			`Exe = BusWires;`
253
254			`end`
255
256			`Add, `Sub, `Multiply, `And, `Or, `Not, `Nor, `Nand, `Ror, `Rol, `Shl, `Shr: //Add, Sub, Logical, Shift
257			`begin`
258			`Rout = Xreg;`
259			`Ain = 1'b1;`
260			`end`
261
262			`default: ;`
263
264			`endcase`
265			`end`
266
267			`2'b10: //define signals in time step T2`
268
269			`case (I)`
270
271			`Not: //Not
272			`begin`
273			AddSub = `AluNot;
274			`Gin = 1'b1;`
275			`end`
276
277			`Ror: //Rotate Right
278			`begin`
279			AddSub = `AluRor;
280			`Gin = 1'b1;`
281			`end`
282
283			`Rol: //Rotate Left
284			`begin`
285			AddSub = `AluRol;
286			`Gin = 1'b1;`
287			`end`
288
289			`Shl: //Shift Left
290			`begin`
291			AddSub = `AluShl;
292			`Gin = 1'b1;`
293			`end`
294
295			`Shr: //Shift Right
296			`begin`
297			AddSub = `AluShl;
298			`Gin = 1'b1;`
299			`end`
300
301			`Add: //Add
302			`begin`
303			`Rout = Y;`
304			AddSub = `AluAdd;
305			`Gin = 1'b1;`
306			`end`
307
308			`Sub: //Sub
309			`begin`
310			`Rout = Y;`
311			AddSub = `AluSub;
312			`Gin = 1'b1;`
313			`end`
314
315			`Multiply: //Multiplication
316			`begin`
317			`Rout = Y;`
318			AddSub = `AluMultiply;
319			`Gin = 1'b1;`
320			`end`
321
322			`And: //and
323			`begin`
324			`Rout = Y;`
325			AddSub = `AluAnd;
326			`Gin = 1'b1;`
327			`end`
328
329			`Nand: //nand
330			`begin`
331			`Rout=Y;`
332			AddSub = `AluNand;
333			`Gin=1'b1;`
334			`end`
335
336			`Or: //or
337			`begin`
338			`Rout=Y;`
339			AddSub = `AluOr;
340			`Gin=1'b1;`
341			`end`
342
343			`Nor: //nor
344			`begin`
345			`Rout=Y;`
346			AddSub = `AluNor;
347			`Gin=1'b1;`
348			`end`
349
350			`default: ;`
351
352
353			`endcase`
354
355			`2'b11: //define signals in time step T2`
356			`begin`
357
358			`case (I)`
359
360			`Add, `Sub, `Multiply: // Add,Sub
361			`begin`
362			`Gout = 1'b1;`
363			`Rin = Xreg;`
364			`Done = 1'b1;`
365			`Exe = G;`
366			`end`
367
368			`And, `Or, `Nand, `Nor, `Not: //And, Or, Nand, Nor, Not
369			`begin`
370			`Gout = 1'b1;`
371			`Rin = Xreg;`
372			`Done = 1'b1;`
373			`Exe = G;`
374			`end`
375
376			`Ror, `Rol, `Shl, `Shr: //Rotate right, Rotate left, Shift left, Shift right
377			`begin`
378			`Gout = 1'b1;`
379			`Rin = Xreg;`
380			`Done = 1'b1;`
381			`Exe = G;`
382			`end`
383
384			`default: ;`
385
386			`endcase`
387
388			`end`
389			`endcase`
390			`end`
391			`end`
392
393			`//Register Creation`
394
395			`regn reg_0 (BusWires[7:0], Rin[0], Clock, R0);`
396			`regn reg_1 (BusWires[7:0], Rin[1], Clock, R1);`
397			`regn reg_2 (BusWires[7:0], Rin[2], Clock, R2);`
398			`regn reg_3 (BusWires[7:0], Rin[3], Clock, R3);`
399
400			`regn reg_A (BusWires, Ain, Clock, A);`
401
402			`regn reg_G (Sum, Gin, Clock, G);`
403
404
405			`//8 Bit Bus BusWires Implementation using Multiplexer`
406
407			`wire [1:6] Sel = {Rout, Gout, Extern};`
408
409			`always @(Sel or R0 or R1 or R2 or R3 or G or Data)`
410			`begin`
411			`if (Sel == 6'b100000)`
412			`BusWires = R0;`
413			`else if (Sel == 6'b010000)`
414			`BusWires = R1;`
415			`else if (Sel == 6'b001000)`
416			`BusWires = R2;`
417			`else if (Sel == 6'b000100)`
418			`BusWires = R3;`
419			`else if (Sel == 6'b000010)`
420			`BusWires = G;`
421			`else if (Sel == 6'b000001)`
422			`BusWires = Data;`
423			`else`
424			`BusWires = 8'bz;`
425
426			`end`
427
428			`endmodule`
429
430
431			`//Machine Cycle(T) Counter`
432
433			`module upcount(Clear, Clock, Q, cmd, catch);`
434
435			`input Clear, Clock, cmd, catch;`
436			`output [1:0] Q;`
437
438			`wire Clear, Clock, cmd, catch;`
439			`reg [1:0] Q;`
440
441			`reg [3:0] RT1;`
442
443
444			`always @(posedge Clock)`
445			`begin`
446			`if (Clear == 1)`
447			`begin`
448			`Q <= 2'b00;`
449			`RT1 <= 4'b0000;`
450			`end`
451
452			`else if (cmd == 0)`
453			`begin`
454			`Q <= 2'b00;`
455			`RT1 <= 4'b0000;`
456			`end`
457
458			`else`
459			`begin`
460			`if (catch == 1'b1)`
461			`begin`
462			`if (RT1 < 8'b0100)`
463			`begin`
464			`RT1 <= RT1 + 1;`
465			`Q <= Q + 1 ;`
466			`end`
467
468			`else if (RT1 == 8'b1111)`
469			`begin`
470			`RT1 <= 4'b0100;`
471			`end`
472
473			`else`
474			`RT1 <= RT1 + 1;`
475			`end`
476			`else`
477			`begin`
478			`Q <= 2'b0;`
479			`RT1 <= 4'b0000;`
480			`end`
481			`end`
482			`end`
483
484
485			`endmodule`
486
487
488			`//2-4 Decoder`
489
490			`module dec2to4(W, En, Y);`
491			`input [1:0] W;`
492			`input En;`
493
494			`wire [1:0] W;`
495			`wire En;`
496
497			`output [0:3] Y;`
498			`reg [0:3] Y;`
499
500			`always @(W or En)`
501			`begin`
502			`if (En == 1)`
503			`case (W)`
504			`0: Y = 4'b1000;`
505			`1: Y = 4'b0100;`
506			`2: Y = 4'b0010;`
507			`3: Y = 4'b0001;`
508			`endcase`
509			`else`
510			`Y = 4'bz;`
511			`end`
512			`endmodule`
513
514
515			`//8-Bit Register`
516
517			`module regn(R, Rin, Clock, Q);`
518			`parameter n = 8;`
519
520			`input [n-1:0] R;`
521			`input Rin, Clock;`
522
523			`wire [n-1:0] R;`
524			`wire Rin, Clock;`
525
526			`output [n-1:0] Q;`
527			`reg [n-1:0] Q;`
528
529			`always @(posedge Clock)`
530			`if (Rin)`
531			`Q <= R;`
532
533			`endmodule`
534
535			`// 40K Block SRAM`
536			`//Read Ram`
537			`module Ram(Clock, cmd, PcAddr, Reset, Inst, En);`
538
539			`input Clock, cmd;`
540			`input [7:0] PcAddr;`
541			`input Reset;`
542			`output [15:0] Inst;`
543			`output En;`
544
545			`wire Clock, cmd;`
546			`wire [7:0] PcAddr;`
547			`wire Reset;`
548
549			`wire [15:0] Inst;`
550			`reg En, We, stop;`
551
552			`reg [7:0] WAddr, S;`
553			`reg [15:0] WData;`
554			`reg [15:0] Memory [0:10];`
555			`reg enable, DoJob;`
556
557			`wire [7:0] Store;`
558
559			`integer count;`
560
561			`always @(Reset)`
562			`begin`
563			`if (Reset == 1)`
564			`begin`
565			`Memory[0] = 16'h80FA;`
566			`Memory[1] = 16'h84F5;`
567			`Memory[2] = 16'h8822;`
568			`Memory[3] = 16'h2400;`
569			`Memory[4] = 16'h1D00;`
570			`Memory[5] = 16'h3B00;`
571			`Memory[6] = 16'h4400;`
572			`Memory[7] = 16'h5400;`
573			`Memory[8] = 16'h6400;`
574			`Memory[9] = 16'h7400;`
575			`Memory[10] = 16'hF409;`
576			`enable = 1;`
577
578			`end`
579			`else`
580			`begin`
581			`enable = 0;`
582			`end`
583			`end`
584
585
586			`always @(posedge Clock)`
587			`begin`
588			`if (Reset == 1)`
589			`begin`
590			`if (enable == 1)`
591			`begin`
592			`if (count <= 10)`
593			`begin`
594
595			`WData = Memory[count];`
596			`WAddr <= WAddr + 1;`
597			`count <= count + 1;`
598			`DoJob = 1'b1;`
599			`end`
600
601			`end`
602			`end`
603
604			`else`
605			`begin`
606
607			`DoJob = 1'b0;`
608			`count <= 0;`
609			`WAddr <= 8'b0;`
610			`WData = 16'b0;`
611			`En = cmd;`
612			`end`
613
614			`end`
615
616			`always @(negedge Clock)`
617			`begin`
618			`if (DoJob == 1)`
619			`begin`
620			`stop = 1'b1;`
621			`We = 1'b1;`
622			`S = WAddr;`
623			`end`
624			`else if (cmd == 1)`
625			`begin`
626			`stop = 1'b1;`
627			`We = 1'b0;`
628			`S = PcAddr;`
629
630			`end`
631			`else`
632			`begin`
633			`stop = 1'b0;`
634			`We = 1'b0;`
635			`end`
636			`end`
637
638			`RAMB4_S16 ram(.DO(Inst), .ADDR(S), .CLK(Clock), .DI(WData),`
639			`.EN(stop), .RST(1'b0), .WE(We));`
640
641			`endmodule`
642
643			`//Program Counter`
644
645			`module pcounter(HButton, ClearCr, Clock, Jmp, Jset, Q1, cmd, Jz);`
646
647			`input ClearCr, Clock;`
648			`input HButton;`
649			`input Jset;`
650			`input [7:0] Jmp;`
651
652			`wire ClearCr, Clock;`
653			`wire HButton;`
654			`wire Jset;`
655			`wire [7:0] Jmp;`
656
657			`output [7:0] Q1;`
658			`output cmd;`
659			`output Jz;`
660
661			`reg [7:0] Q1;`
662
663			`reg work, cmd, Jz;`
664
665
666			`always @(posedge Clock)`
667			`begin`
668
669			`if (ClearCr == 1)`
670			`begin`
671			`Q1 <= 0;`
672			`work = 1'b0;`
673			`end`
674
675			`else if (HButton == 0)`
676			`begin`
677			`if (work != 1'b1)`
678			`begin`
679			`cmd = 1'b1;`
680			`work = 1'b1;`
681			`begin`
682			`if (Jset == 1)`
683			`begin`
684			`Q1 <= Jmp;`
685			`Jz = 1'b1;`
686			`end`
687			`else`
688			`Q1 <= Q1 + 1 ;`
689			`end`
690			`end`
691			`end`
692			`else`
693			`begin`
694			`cmd = 1'b0;`
695			`work = 1'b0;`
696			`Jz = 1'b0;`
697			`end`
698			`end`
699
700			`endmodule`
701
702
703
704			`//Arthematic Logic Unit`
705
706			`module alu (Inst, A, BusWires, Result);`
707
708			`input [3:0] Inst;`
709			`input [7:0] A, BusWires;`
710
711			`wire [3:0] Inst;`
712			`wire [7:0] A, BusWires;`
713
714			`output [7:0] Result;`
715			`//output Cout, Zout, Sout;`
716
717			`reg [7:0] Result;`
718			`reg Zout, Sout, Cout;`
719
720			`always @(Inst or A or BusWires or Result)`
721
722			`begin`
723			`Zout = 1'b0;`
724			`Sout = 1'b0;`
725			`Cout = 1'b0;`
726			`Result = 8'b0;`
727
728
729			`case (Inst) // synopsis parallel_case`
730
731
732			`AluMultiply:
733			`begin`
734			`{Cout,Result} = (A * BusWires);`
735			`//Cout = Result[8];`
736			`if (Result == 8'h00)`
737			`Zout = 1'b1;`
738			`if (Result[7] == 1)`
739			`Sout = 1'b1;`
740			`end`
741
742			`AluShl: Result = {A[6:0], 1'b0};
743			`AluShr: Result = {1'b0, A[7:1]};
744
745			`AluRol: Result = {A[6:0], A[7]};
746			`AluRor: Result = {A[0], A[7:1]};
747
748			`AluAdd: begin
749			`{Cout,Result} = (A + BusWires);`
750			`//Cout = Result[8];`
751			`if (Result == 8'h00)`
752			`Zout = 1'b1;`
753			`if (Result[7] == 1)`
754			`Sout = 1'b1;`
755			`end`
756
757			`AluSub: begin
758			`{Cout,Result} = (A - BusWires) ;`
759			`//Cout = Result[8];`
760			`if (Result == 8'h00)`
761			`Zout = 1'b1;`
762			`if (Result[7] == 1)`
763			`Sout = 1'b1;`
764			`end`
765
766			`AluAnd: Result = A & BusWires;
767			`AluNand: Result = ~(A & BusWires);
768			`AluOr: Result = A \| BusWires;
769			`AluNor: Result = ~(A \| BusWires);
770			`AluNot: Result = ~(A);
771
772			`default: begin`
773			`Zout = 1'b0;`
774			`Sout = 1'b0;`
775			`Cout = 1'b0;`
776			`Result = 8'b0;`
777			`end`
778
779
780			`endcase`
781
782			`end`
783
784			`endmodule`
785
786
787
788
789
790			`/* Led: The 7 segment display */`
791
792			`module Display(buscontents, clk, Done, led);`
793
794			`input [3:0] buscontents;`
795			`input clk, Done;`
796
797			`wire [3:0] buscontents;`
798			`wire clk, Done;`
799
800			`output [6:0] led;`
801
802			`reg[6:0] led;`
803
804			`always @ (posedge clk)`
805			`if (Done == 1)`
806			`begin`
807			`case (buscontents) // synopsis full_case parallel_case`
808
809			`4'b0000: led = 7'b1110111;`
810			`4'b0001: led = 7'b0010010;`
811			`4'b0010: led = 7'b1011101;`
812			`4'b0011: led = 7'b1011011;`
813			`4'b0100: led = 7'b0111010;`
814			`4'b0101: led = 7'b1101011;`
815			`4'b0110: led = 7'b1101111;`
816			`4'b0111: led = 7'b1010010;`
817			`4'b1000: led = 7'b1111111;`
818			`4'b1001: led = 7'b1111011;`
819			`4'b1010: led = 7'b1111110;`
820			`4'b1011: led = 7'b0101111;`
821			`4'b1100: led = 7'b0001101;`
822			`4'b1101: led = 7'b0011111;`
823			`4'b1110: led = 7'b1101101;`
824			`4'b1111: led = 7'b1101100;`
825			`endcase`
826			`end`
827
828			`endmodule`
829
830
831			`// Delay Lock Loops and Global clock buffers instantiation`
832
833			`module dll(CLKIN, CLK1X, LOCKED2X);`
834
835			`input CLKIN;`
836			`output CLK1X, LOCKED2X;`
837
838			`wire CLK1X;`
839
840			`wire CLKIN_w, CLK1X_dll, LOCKED2X;`
841
842
843			`IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));`
844
845			`CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK1X), .RST(1'b0),`
846			`.CLK0(CLK1X_dll), .CLK90(), .CLK180(), .CLK270(),`
847			`.CLK2X(), .CLKDV(), .LOCKED(LOCKED2X));`
848
849			`BUFG clk2xg (.I(CLK1X_dll), .O(CLK1X));`
850
851			`//OBUF lckpad (.I(LOCKED2X), .O(LOCKED));`
852
853			`endmodule`