URL
https://opencores.org/ocsvn/esoc/esoc/trunk
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| Line No. |
Rev |
Author |
Line |
| 1 |
41 |
lmaarsen |
[library]
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others = $MODEL_TECH/../modelsim.ini
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[Project]
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Project_Version = 6
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Project_DefaultLib = work
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Project_SortMethod = unused
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| 7 |
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Project_Files_Count = 3
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| 8 |
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Project_File_0 = D:/Documenten/Projects/eSoc/3. Sources/esoc.ews/design.hdl/esoc_packet_proces.vhd
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Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1320955423 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 0 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 1 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
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Project_File_1 = D:/Documenten/Projects/eSoc/3. Sources/esoc.ews/design.hdl/esoc_configuration.vhd
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Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1323439971 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 0 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 1 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
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Project_File_2 = D:/Documenten/Projects/eSoc/3. Sources/esoc.ews/design.hdl/esoc.vhd
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Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1323439971 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
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Project_Sim_Count = 0
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| 15 |
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Project_Folder_Count = 0
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Echo_Compile_Output = 1
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Save_Compile_Report = 1
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Project_Opt_Count = 0
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| 19 |
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ForceSoftPaths = 0
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| 20 |
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ReOpenSourceFiles = 1
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| 21 |
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CloseSourceFiles = 1
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| 22 |
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ProjectStatusDelay = 5000
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| 23 |
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VERILOG_DoubleClick = Edit
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| 24 |
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VERILOG_CustomDoubleClick =
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SYSTEMVERILOG_DoubleClick = Edit
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| 26 |
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SYSTEMVERILOG_CustomDoubleClick =
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| 27 |
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VHDL_DoubleClick = Edit
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| 28 |
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VHDL_CustomDoubleClick =
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| 29 |
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PSL_DoubleClick = Edit
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| 30 |
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PSL_CustomDoubleClick =
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| 31 |
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TEXT_DoubleClick = Edit
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| 32 |
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TEXT_CustomDoubleClick =
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| 33 |
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SYSTEMC_DoubleClick = Edit
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| 34 |
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SYSTEMC_CustomDoubleClick =
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| 35 |
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TCL_DoubleClick = Edit
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TCL_CustomDoubleClick =
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MACRO_DoubleClick = Edit
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| 38 |
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MACRO_CustomDoubleClick =
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| 39 |
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VCD_DoubleClick = Edit
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| 40 |
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VCD_CustomDoubleClick =
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| 41 |
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SDF_DoubleClick = Edit
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| 42 |
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SDF_CustomDoubleClick =
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| 43 |
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XML_DoubleClick = Edit
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| 44 |
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XML_CustomDoubleClick =
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| 45 |
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LOGFILE_DoubleClick = Edit
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| 46 |
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LOGFILE_CustomDoubleClick =
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| 47 |
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UCDB_DoubleClick = Edit
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| 48 |
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UCDB_CustomDoubleClick =
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| 49 |
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EditorState = {tabbed horizontal 1}
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| 50 |
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Project_Major_Version = 6
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| 51 |
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Project_Minor_Version = 3
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| 52 |
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[vsim]
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| 53 |
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RunLength = 10 us
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| 54 |
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StdArithNoWarnings = 1
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| 55 |
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NumericStdNoWarnings = 1
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