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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [esoc_ctrl_in.txt] - Blame information for rev 54

Line No.	Rev	Author	Line
1	41	lmaarsen	`--`
2			`-- Test R/W access through the control interface to ESOC`
3			`--`
4			`-- access the ESOC CONTROL UNIT`
5			`--`
6			`mr 8000 00000000`
7			`mr 8001 00010000`
8			`mr 8002 00000008`
9			`mw 8000 32100123`
10			`mr 8000 32100123`
11			`wt 100`
12			`--`
13			`-- access the ESOC DATA BUS ARBITER UNIT`
14			`--`
15			`mr 8800 00000000`
16			`mw 8800 FED00DEF`
17			`mr 8800 FED00DEF`
18			`wt 100`
19			`--`
20			`-- access the ESOC PORT 0 UNIT`
21			`--`
22			`mr 0005 000005EE`
23			`mw 0005 00000432`
24			`mr 0005 00000432`
25			`wt 100`
26			`mr 0180 00000001`
27			`mw 0180 ABC00ABC`
28			`mr 0180 ABC00ABC`
29			`wt 100`
30			`--`
31			`-- access the ESOC PORT 7 UNIT`
32			`--`
33			`mr 3805 000005EE`
34			`mw 3805 00000100`
35			`mr 3805 00000100`
36			`wt 100`
37			`mr 3980 00000001`
38			`mw 3980 12300321`
39			`mr 3980 12300321`
40			`wt 100`
41			`--`
42			`-- check all written registers again`
43			`--`
44			`mr 8000 32100123`
45			`mr 8800 FED00DEF`
46			`mr 0005 00000432`
47			`mr 0180 ABC00ABC`
48			`mr 3805 00000100`
49			`mr 3980 12300321`