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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [esoc_ctrl_out.txt] - Blame information for rev 56

Line No.	Rev	Author	Line
1	41	lmaarsen
2			`Test R/W access through the control interface to ESOC`
3
4			`access the ESOC CONTROL UNIT`
5
6			`mr 8000 00000000, expected 00000000, status: OK`
7			`mr 8001 00010000, expected 00010000, status: OK`
8			`mr 8002 00000008, expected 00000008, status: OK`
9			`mw 8000 32100123`
10			`mr 8000 32100123, expected 32100123, status: OK`
11
12			`access the ESOC DATA BUS ARBITER UNIT`
13
14			`mr 8800 00000000, expected 00000000, status: OK`
15			`mw 8800 FED00DEF`
16			`mr 8800 FED00DEF, expected FED00DEF, status: OK`
17
18			`access the ESOC PORT 0 UNIT`
19
20			`mr 0005 000005EE, expected 000005EE, status: OK`
21			`mw 0005 00000432`
22			`mr 0005 00000432, expected 00000432, status: OK`
23			`mr 0180 00000001, expected 00000001, status: OK`
24			`mw 0180 ABC00ABC`
25			`mr 0180 ABC00ABC, expected ABC00ABC, status: OK`
26
27			`access the ESOC PORT 7 UNIT`
28
29			`mr 3805 000005EE, expected 000005EE, status: OK`
30			`mw 3805 00000100`
31			`mr 3805 00000100, expected 00000100, status: OK`
32			`mr 3980 00000001, expected 00000001, status: OK`
33			`mw 3980 12300321`