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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [@m25@a@a256/] [_primary.vhd] - Blame information for rev 41

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Line No. Rev Author Line
1 41 lmaarsen
library verilog;
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use verilog.vl_types.all;
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entity M25AA256 is
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    port(
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        SI              : in     vl_logic;
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        SO              : out    vl_logic;
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        SCK             : in     vl_logic;
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        CS_N            : in     vl_logic;
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        WP_N            : in     vl_logic;
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        HOLD_N          : in     vl_logic;
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        RESET           : in     vl_logic
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    );
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end M25AA256;

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