<title>Sample Waveforms for esoc_fifo_512x16.vhd </title>
4
</head>
5
<body>
6
<h2><CENTER>Sample behavioral waveforms for design file esoc_fifo_512x16.vhd </CENTER></h2>
7
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design esoc_fifo_512x16.vhd. The design esoc_fifo_512x16.vhd has a depth of 512 words of 16 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
13
<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
