<title>Sample Waveforms for esoc_pll1_c3.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file esoc_pll1_c3.vhd </CENTER></h2>
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<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design esoc_pll1_c3.vhd. The design esoc_pll1_c3.vhd has Cyclone III AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
