OpenCores
URL https://opencores.org/ocsvn/esoc/esoc/trunk

Subversion Repositories esoc

[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_pll2_c3/] [esoc_pll2_c3_waveforms.html] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 42 lmaarsen
<html>
2
<head>
3
<title>Sample Waveforms for esoc_pll2_c3.vhd </title>
4
</head>
5
<body>
6
<h2><CENTER>Sample behavioral waveforms for design file esoc_pll2_c3.vhd </CENTER></h2>
7
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design esoc_pll2_c3.vhd. The design esoc_pll2_c3.vhd has Cyclone III AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Output port LOCKED  will go high when the PLL locks to the input clock. </P>
8
<CENTER><img src=esoc_pll2_c3_wave0.jpg> </CENTER>
9
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
10
<P><FONT size=3></P>
11
<P></P>
12
</body>
13
</html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.