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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [esoc_port_mac_bb.v] - Blame information for rev 47

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1 42 lmaarsen
// Generated by Triple Speed Ethernet 8.1 [Altera, IP Toolbench 1.3.0 Build 163]
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// ************************************************************
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// Copyright (C) 1991-2012 Altera Corporation
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// Any megafunction design, and related net list (encrypted or decrypted),
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// support information, device programming or simulation file, and any other
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// associated documentation or information provided by Altera or a partner
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// under Altera's Megafunction Partnership Program may be used only to
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// program PLD devices (but not masked PLD devices) from Altera.  Any other
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// use of such megafunction design, net list, support information, device
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// programming or simulation file, or any other related documentation or
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// information is prohibited for any other purpose, including, but not
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// limited to modification, reverse engineering, de-compiling, or use with
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// any other silicon devices, unless such use is explicitly licensed under
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// a separate agreement with Altera or a megafunction partner.  Title to
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// the intellectual property, including patents, copyrights, trademarks,
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// trade secrets, or maskworks, embodied in any such megafunction design,
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// net list, support information, device programming or simulation file, or
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// any other related documentation or information provided by Altera or a
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// megafunction partner, remains with Altera, the megafunction partner, or
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// their respective licensors.  No other licenses, including any licenses
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// needed under any third party's intellectual property, are provided herein.
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module esoc_port_mac (
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        ff_tx_crc_fwd,
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        ff_tx_data,
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        ff_tx_eop,
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        ff_tx_err,
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        ff_tx_mod,
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        ff_tx_sop,
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        ff_tx_wren,
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        ff_tx_clk,
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        ff_rx_rdy,
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        ff_rx_clk,
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        address,
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        read,
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        writedata,
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        write,
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        clk,
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        reset,
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        rgmii_in,
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        rx_control,
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        tx_clk,
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        rx_clk,
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        set_10,
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        set_1000,
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        xon_gen,
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        xoff_gen,
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        magic_sleep_n,
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        mdio_in,
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        ff_tx_rdy,
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        ff_rx_data,
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        ff_rx_dval,
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        ff_rx_eop,
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        ff_rx_mod,
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        ff_rx_sop,
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        rx_err,
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        rx_err_stat,
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        rx_frm_type,
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        ff_rx_dsav,
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        readdata,
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        waitrequest,
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        rgmii_out,
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        tx_control,
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        ena_10,
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        eth_mode,
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        ff_tx_septy,
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        tx_ff_uflow,
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        ff_rx_a_full,
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        ff_rx_a_empty,
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        ff_tx_a_full,
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        ff_tx_a_empty,
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        magic_wakeup,
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        mdio_out,
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        mdio_oen,
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        mdc);
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        input           ff_tx_crc_fwd;
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        input   [31:0]   ff_tx_data;
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        input           ff_tx_eop;
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        input           ff_tx_err;
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        input   [1:0]    ff_tx_mod;
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        input           ff_tx_sop;
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        input           ff_tx_wren;
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        input           ff_tx_clk;
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        input           ff_rx_rdy;
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        input           ff_rx_clk;
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        input   [7:0]    address;
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        input           read;
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        input   [31:0]   writedata;
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        input           write;
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        input           clk;
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        input           reset;
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        input   [3:0]    rgmii_in;
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        input           rx_control;
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        input           tx_clk;
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        input           rx_clk;
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        input           set_10;
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        input           set_1000;
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        input           xon_gen;
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        input           xoff_gen;
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        input           magic_sleep_n;
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        input           mdio_in;
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        output          ff_tx_rdy;
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        output  [31:0]   ff_rx_data;
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        output          ff_rx_dval;
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        output          ff_rx_eop;
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        output  [1:0]    ff_rx_mod;
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        output          ff_rx_sop;
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        output  [5:0]    rx_err;
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        output  [17:0]   rx_err_stat;
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        output  [3:0]    rx_frm_type;
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        output          ff_rx_dsav;
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        output  [31:0]   readdata;
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        output          waitrequest;
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        output  [3:0]    rgmii_out;
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        output          tx_control;
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        output          ena_10;
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        output          eth_mode;
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        output          ff_tx_septy;
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        output          tx_ff_uflow;
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        output          ff_rx_a_full;
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        output          ff_rx_a_empty;
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        output          ff_tx_a_full;
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        output          ff_tx_a_empty;
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        output          magic_wakeup;
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        output          mdio_out;
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        output          mdio_oen;
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        output          mdc;
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endmodule

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