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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [esoc_port_mac_nativelink.tcl] - Blame information for rev 42

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Line No. Rev Author Line
1 42 lmaarsen
#####################################################################################
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# Copyright (C) 1991-2007 Altera Corporation
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# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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# support information,  device programming or simulation file,  and any other
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# associated  documentation or information  provided by  Altera  or a partner
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# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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# other  use  of such  megafunction  design,  netlist,  support  information,
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# device programming or simulation file,  or any other  related documentation
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# or information  is prohibited  for  any  other purpose,  including, but not
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# limited to  modification,  reverse engineering,  de-compiling, or use  with
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# any other  silicon devices,  unless such use is  explicitly  licensed under
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# a separate agreement with  Altera  or a megafunction partner.  Title to the
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# intellectual property,  including patents,  copyrights,  trademarks,  trade
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# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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# support  information,  device programming or simulation file,  or any other
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# related documentation or information provided by  Altera  or a megafunction
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# partner, remains with Altera, the megafunction partner, or their respective
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# licensors. No other licenses, including any licenses needed under any third
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# party's intellectual property, are provided herein.
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#####################################################################################
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#####################################################################################
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# Altera Triple-Speed Ethernet Megacore NativeLink TCL script
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#
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# This script should be sourced from the Quartus II TCL console prior to 
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# simulating using NativeLink 
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#
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# Generated on Mon Nov 18 12:36:19 CET 2013
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#
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#####################################################################################
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#Set time scale
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set_global_assignment -name EDA_TIME_SCALE "1 ns" -section_id eda_simulation
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#Set eda netlist writer options
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VHDL" -section_id eda_simulation
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#Set to work in test bench mode
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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#Set testbench top level name and module name
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH esoc_port_mac_tb -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME esoc_port_mac_tb -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id esoc_port_mac_tb
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#Set design instance
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME esoc_port_mac -section_id esoc_port_mac_tb
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#Set simulation time
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set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "50 us" -section_id esoc_port_mac_tb
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#Set testbench component files
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethgen.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethgen2.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethgen32.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethmon.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethmon2.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethmon_32.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/top_ethmon32.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/mdio_reg.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/mdio_slave.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/top_mdio_slave.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/loopback_adapter.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/loopback_adapter_fifo.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/timing_adapter_8.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/timing_adapter_fifo_8.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/timing_adapter_32.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/top_ethgen8.vhd -section_id esoc_port_mac_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/altera_ethmodels_pack.vhd -section_id esoc_port_mac_tb
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#Set memory initialization files
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/esoc_port_mac/sdpm_altsyncram.hex -section_id esoc_port_mac_tb
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#Set top level testbench files
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set_global_assignment -name EDA_TEST_BENCH_FILE testbench/esoc_port_mac/esoc_port_mac_tb.vhd -section_id esoc_port_mac_tb
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