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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [model/] [ethgen.vhd] - Blame information for rev 42

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1 42 lmaarsen
-- -------------------------------------------------------------------------
2
-- -------------------------------------------------------------------------
3
--
4
-- Revision Control Information
5
--
6
-- $RCSfile: ethgen.vhd,v $
7
-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/vhdl/ethernet_model/gen/ethgen.vhd,v $
8
--
9
-- $Revision: #1 $
10
-- $Date: 2008/08/09 $
11
-- Check in by : $Author: sc-build $
12
-- Author      : SKNg/TTChong
13
--
14
-- Project     : Triple Speed Ethernet - 10/100/1000 MAC
15
--
16
-- Description : (Simulation only)
17
--
18
-- GMII Interface Ethernet Traffic Generator
19
-- Ethernet Traffic Generator for 8 bit MAC Atlantic client interface
20
--
21
-- 
22
-- ALTERA Confidential and Proprietary
23
-- Copyright 2006 (c) Altera Corporation
24
-- All rights reserved
25
--
26
-- -------------------------------------------------------------------------
27
-- -------------------------------------------------------------------------
28
 
29
 
30
 
31
library ieee ;
32
use ieee.std_logic_1164.all ;
33
use ieee.std_logic_arith.all ;
34
use ieee.std_logic_unsigned.all ;
35
 
36
entity ETHGENERATOR is
37
 
38
    generic (  THOLD          : time    := 1 ns;
39
                           ENABLE_SHIFT16 : integer := 0  --0 for false, 1 for true
40
                        );
41
    port (
42
 
43
      reset       : in std_logic ;     -- active high
44
 
45
        -- GMII receive interface: To be connected to MAC RX
46
      rx_clk      : in std_logic ;
47
      enable      : in std_logic ;
48
      rxd         : out std_logic_vector(7 downto 0);
49
      rx_dv       : out std_logic;
50
      rx_er       : out std_logic;
51
 
52
        -- Additional FIFO controls for FIFO test scenarios
53
 
54
      sop         : out std_logic;   -- pulse with first character
55
      eop         : out std_logic;   -- pulse with last  character
56
 
57
        -- Frame Contents definitions
58
 
59
      mac_reverse   : in std_logic;                     -- 1: dst/src are sent MSB first
60
      dst           : in std_logic_vector(47 downto 0); -- destination address
61
      src           : in std_logic_vector(47 downto 0); -- source address
62
 
63
      prmble_len    : in integer range 0 to 40;         -- length of preamble
64
      pquant        : in std_logic_vector(15 downto 0); -- Pause Quanta value
65
      vlan_ctl      : in std_logic_vector(15 downto 0); -- VLAN control info
66
      len           : in std_logic_vector(15 downto 0); -- Length of payload
67
      frmtype       : in std_logic_vector(15 downto 0); -- if non-null: type field instead length
68
 
69
      cntstart      : in integer range 0 to 255;  -- payload data counter start (first byte of payload)
70
      cntstep       : in integer range 0 to 255;  -- payload counter step (2nd byte in paylaod)
71
 
72
      ipg_len       : in integer range 0 to 32768;  -- inter packet gap (delay after CRC)
73
      wrong_pause_op : in std_logic ;                    -- Generate Pause Frame with Wrong Opcode       
74
      wrong_pause_lgth : in std_logic ;                    -- Generate Pause Frame with Wrong Opcode       
75
       -- Control
76
 
77
      payload_err   : in std_logic;  -- generate payload pattern error (last payload byte is wrong)
78
      prmbl_err     : in std_logic;
79
      crc_err       : in std_logic;
80
      vlan_en       : in std_logic;
81
      pause_gen     : in std_logic;
82
      pad_en        : in std_logic;
83
      phy_err       : in std_logic;
84
      end_err       : in std_logic;  -- keep rx_dv high one cycle after end of frame
85
      magic         : in std_logic;
86
      stack_vlan    : in std_logic;
87
 
88
      data_only     : in std_logic;  -- if set omits preamble, padding, CRC
89
 
90
      start         : in  std_logic;
91
      done          : out std_logic );
92
 
93
end ETHGENERATOR ;
94
 
95
architecture behave of ETHGENERATOR is
96
 
97
    -- local copied (registered) commands 
98
    -- ----------------------------------
99
 
100
    signal  imac_reverse   :  std_logic;                     -- 1: dst/src are sent MSB first
101
    signal  idst           :  std_logic_vector(47 downto 0); -- destination address
102
    signal  isrc           :  std_logic_vector(47 downto 0); -- source address
103
    signal  imagic         :  std_logic;                     -- generate magic packet
104
 
105
    signal  iprmble_len    :  integer range 0 to 40;  -- length of preamble
106
    signal  ipquant        :  std_logic_vector(15 downto 0); -- Pause Quanta value
107
    signal  ivlan_ctl      :  std_logic_vector(15 downto 0); -- VLAN control info
108
    signal  ilen           :  std_logic_vector(15 downto 0); -- Length of payload
109
    signal  ifrmtype          :  std_logic_vector(15 downto 0); -- if non-null: type field instead length
110
 
111
    signal  icntstart      :  integer range 0 to 255;  -- payload data counter start (first byte of payload)
112
    signal  icntstep       :  integer range 0 to 255;  -- payload counter step (2nd byte in paylaod)
113
    signal  iipg_len       :  integer range 0 to 32768; -- inter packet gap
114
 
115
    signal  ipayload_err     :  std_logic;
116
    signal  iprmbl_err     :  std_logic;
117
    signal  icrc_err       :  std_logic;
118
    signal  ivlan_en       :  std_logic;
119
    signal  istack_en      :  std_logic;
120
    signal  ipause_gen     :  std_logic;
121
    signal  ipad_en        :  std_logic;
122
    signal  iphy_err       :  std_logic;
123
    signal  iend_err       :  std_logic;
124
 
125
    signal  idata_only     :  std_logic;
126
 
127
 
128
    -- internal
129
 
130
    type  state_typ is (S_IDLE, S_PRMBL, S_SFD, S_STACK,
131
                                S_DST , S_SRC, S_PAUSE, S_TAG, S_LEN,
132
                                S_DATA, S_PAD, S_CRC, S_ENDERR, S_IPG, S_Dword32Aligned);
133
 
134
    signal state      : state_typ;
135
    signal last_state : state_typ;
136
    signal last_state_dly : state_typ;   -- delayed one again
137
 
138
    signal crc32 : std_logic_vector(31 downto 0);
139
 
140
    signal count : integer range 0 to 65535;
141
    signal poscnt: integer range 0 to 65535;       -- position in frame starts at first dst byte
142
 
143
    signal datacnt: integer range 0 to 255;
144
    signal rxdata: std_logic_vector(7 downto 0);   -- next data to put on the line
145
 
146
    signal sop_int: std_logic;
147
 
148
    signal rx_clk_gen: std_logic;
149
    signal enable_int: std_logic;
150
    signal dval_temp: std_logic;
151
    signal dout_temp: std_logic_vector (7 downto 0);
152
    signal sop_temp: std_logic;
153
    signal eop_temp: std_logic;
154
    signal derror_temp: std_logic;
155
    signal enable_reg: std_logic;
156
    signal done_temp: std_logic;
157
 
158
begin
159
 
160
 
161
    process (rx_clk, reset)
162
       begin
163
         if (reset = '1') then
164
           enable_reg <= '0';
165
         elsif (rising_edge(rx_clk)) then
166
           enable_reg <= enable;
167
         end if;
168
    end process;
169
 
170
    enable_int <= enable_reg;
171
    rxd        <= dout_temp;
172
    rx_dv      <= dval_temp;
173
    rx_er      <= derror_temp;
174
    sop        <= sop_temp;
175
    eop        <= eop_temp;
176
    done       <= done_temp;
177
    rx_clk_gen <= rx_clk and enable_int;
178
 
179
 
180
 -- -----------------------------------
181
 -- capture command when start asserted
182
 -- -----------------------------------
183
 
184
    process( rx_clk_gen, reset )
185
    begin
186
 
187
        if( reset='1') then
188
 
189
            imac_reverse   <= '0';               -- 1: dst/src are sent MSB first
190
        idst           <= (others => '0');   -- destination address
191
            isrc           <= (others => '0'); -- source address
192
            imagic         <= '0' ;
193
 
194
            iprmble_len    <= prmble_len;  -- length of preamble
195
            ipquant        <= (others => '0'); -- Pause Quanta value
196
            ivlan_ctl      <= (others => '0'); -- VLAN control info
197
            ilen           <= (others => '0'); -- Length of payload
198
            ifrmtype          <= (others => '0'); -- if non-null: type field instead length
199
 
200
            icntstart      <= 0;  -- payload data counter start (first byte of payload)
201
            icntstep       <= 0;  -- payload counter step (2nd byte in paylaod)
202
            iipg_len       <= 0;
203
 
204
            ipayload_err   <= '0';
205
            iprmbl_err     <= '0';
206
            icrc_err       <= '0';
207
            ivlan_en       <= '0';
208
            istack_en      <= '0';
209
            ipause_gen     <= '0';
210
            ipad_en        <= '0';
211
            iphy_err       <= '0';
212
            iend_err       <= '0';
213
            idata_only     <= '0';
214
 
215
        elsif( rx_clk_gen='1' and rx_clk_gen'event and start='1' and state=S_IDLE) then
216
 
217
            imac_reverse   <= mac_reverse;               -- 1: dst/src are sent MSB first
218
            idst           <= dst;   -- destination address
219
            isrc           <= src; -- source address
220
            imagic         <= magic;
221
 
222
            iprmble_len    <= prmble_len;  -- length of preamble
223
            ipquant        <= pquant; -- Pause Quanta value
224
            ivlan_ctl      <= vlan_ctl; -- VLAN control info
225
 
226
            if (magic='1') then
227
 
228
                ilen       <= conv_std_logic_vector(46, 16) ;
229
 
230
            else
231
 
232
                ilen       <= len; -- Length of payload
233
 
234
            end if ;
235
 
236
            ifrmtype       <= frmtype; -- if non-null: type field instead length
237
 
238
            icntstart      <= cntstart;  -- payload data counter start (first byte of payload)
239
            icntstep       <= cntstep;  -- payload counter step (2nd byte in paylaod)
240
            iipg_len       <= ipg_len;
241
 
242
            ipayload_err   <= payload_err;
243
            iprmbl_err     <= prmbl_err;
244
            icrc_err       <= crc_err;
245
            ivlan_en       <= vlan_en;
246
            istack_en      <= stack_vlan;
247
            ipause_gen     <= pause_gen;
248
            ipad_en        <= pad_en;
249
            iphy_err       <= phy_err;
250
            iend_err       <= end_err;
251
            idata_only     <= data_only;
252
 
253
        end if;
254
    end process;
255
 
256
 
257
 -- ----------------------------------------------
258
 -- CRC calculation over all bytes except preamble
259
 -- ----------------------------------------------
260
 
261
    process( rx_clk_gen, reset )
262
 
263
        variable crctmp : std_logic_vector(31 downto 0);
264
        variable i      : integer range 0 to 8;
265
 
266
    begin
267
        if( reset = '1' ) then
268
 
269
            crc32 <= (others => '1' );
270
 
271
        elsif( rx_clk_gen = '0' and rx_clk_gen'event ) then    -- need it ahead
272
 
273
            if( last_state=S_SFD ) then
274
 
275
                crc32 <= (others => '1' );    -- RESET CRC at start of DST
276
 
277
            elsif( (state /= S_IDLE) and
278
                   (state /= S_PRMBL) and
279
                   (last_state /= S_CRC ) ) then
280
 
281
                    crctmp := crc32;
282
 
283
                    for i in 0 to 7 loop      -- process all bits we have here
284
 
285
                       if( (rxdata(i) xor crctmp(31)) = '1' ) then
286
                         crctmp := to_stdlogicvector((to_bitvector(crctmp)) sll 1);  -- shift in a 0, will be xor'ed to 1 by the polynom
287
                         crctmp := crctmp xor X"04C11DB7";
288
                       else
289
                         crctmp := to_stdlogicvector((to_bitvector(crctmp)) sll 1);  -- shift in a 0
290
                       end if;
291
 
292
                   end loop;
293
 
294
                   crc32 <= crctmp;
295
 
296
            end if;
297
 
298
        end if;
299
 
300
    end process;
301
 
302
 -- ----------------------------------------------
303
 -- Push RX Data on GMII and 
304
 -- produce PHY error if requested during SRC address transmission
305
 -- ----------------------------------------------
306
 
307
    process( rx_clk_gen, reset )
308
    begin
309
        if( reset = '1' ) then
310
 
311
            dout_temp   <= (others => '0' );
312
            dval_temp <= '0';
313
            derror_temp <= '0';
314
 
315
        elsif( rx_clk_gen = '1' and rx_clk_gen'event ) then
316
 
317
            if( (last_state = S_IDLE) or (last_state=S_IPG)) then
318
 
319
                dout_temp   <= (others => '0') after THOLD;
320
                dval_temp <= '0' after THOLD;
321
 
322
            else
323
 
324
                -- Data and DV 
325
 
326
                dout_temp   <= rxdata after THOLD;
327
                dval_temp <= '1' after THOLD;
328
 
329
                -- PHY error in SRC field
330
 
331
                if( last_state=S_SRC and count=2 and iphy_err='1' and data_only='0') then
332
 
333
                    derror_temp <= '1' after THOLD;
334
 
335
                elsif (data_only='1' and iphy_err='1' and ((last_state/=S_IDLE and state=S_IDLE) or
336
                      (last_state/=S_IPG and state=S_IPG )) ) then
337
 
338
                        if( not(last_state=S_IPG and state=S_IDLE) ) then  -- if from ipg to idle, eop has been pulsed already
339
 
340
                                derror_temp <= '1' after THOLD;
341
 
342
                        end if;
343
 
344
                else
345
 
346
                    derror_temp <= '0' after THOLD;
347
 
348
                end if;
349
 
350
            end if;
351
 
352
        end if;
353
 
354
    end process;
355
 
356
 -- ----------------------------------------------
357
 -- SOP and EOP generation (helper for FIFO testing)
358
 -- ----------------------------------------------
359
 
360
    process( rx_clk_gen, reset )
361
    begin
362
      if( reset = '1' ) then
363
 
364
            sop_temp     <= '0';
365
            sop_int <= '0';
366
            eop_temp     <= '0';
367
 
368
      elsif(rx_clk_gen='1' and rx_clk_gen'event ) then
369
 
370
            if(last_state=S_IDLE and state/=S_IDLE) then
371
 
372
                sop_int <= '1';
373
 
374
            else
375
 
376
                sop_int <= '0';
377
 
378
            end if;
379
 
380
            if((last_state/=S_IDLE and state=S_IDLE) or
381
               (last_state/=S_IPG and state=S_IPG ) ) then
382
 
383
                if( not(last_state=S_IPG and state=S_IDLE) ) then  -- if from ipg to idle, eop has been pulsed already
384
 
385
                    eop_temp <= '1' after THOLD;
386
 
387
                end if;
388
 
389
            else
390
 
391
                eop_temp <= '0' after THOLD;
392
 
393
            end if;
394
 
395
            sop_temp <= sop_int after THOLD; -- need 1 delay
396
 
397
      end if;
398
    end process;
399
 
400
 
401
 
402
 -- ----------------------------------------------
403
 -- Position Counter: Starts with first octet of destination address
404
 -- ----------------------------------------------
405
 
406
    process( rx_clk_gen, reset )
407
    begin
408
      if( reset = '1' ) then
409
 
410
            poscnt <= 0;
411
 
412
      elsif(rx_clk_gen='1' and rx_clk_gen'event ) then
413
 
414
            if( (state=S_SFD) or
415
                (state=S_IDLE and start='1') ) then  -- in the data_only case necessary
416
 
417
                poscnt <= 0;                   -- is 1 with the first byte sent (prmbl or DST)
418
 
419
            else
420
 
421
                if( poscnt < 65535 ) then
422
 
423
                        poscnt <= poscnt +1;
424
 
425
                end if;
426
 
427
            end if;
428
     end if;
429
    end process;
430
 
431
 -- ----------------------------------------------
432
 -- Done indication
433
 -- ----------------------------------------------
434
    process( rx_clk_gen, reset )
435
    begin
436
      if( reset = '1' ) then
437
 
438
            done_temp <= '1';
439
 
440
      elsif(rx_clk_gen='1' and rx_clk_gen'event ) then
441
 
442
            if( state=S_IDLE ) then
443
 
444
                done_temp <= not start;
445
 
446
            else
447
 
448
                done_temp <= '0';
449
 
450
            end if;
451
 
452
      end if;
453
    end process;
454
 
455
 
456
 -- ----------------------------------------------
457
 -- Generator State Machine
458
 -- ----------------------------------------------
459
 
460
    process( rx_clk_gen, reset )
461
 
462
        variable hi,lo  : integer;
463
        variable cnttmp : integer range 0 to 65536;
464
        variable i      : integer;
465
 
466
    begin
467
      if( reset = '1' ) then
468
 
469
            state      <= S_IDLE;
470
            last_state <= S_IDLE;
471
 
472
            rxdata <= (others => 'X' );
473
            count  <= 0;
474
 
475
      elsif(rx_clk_gen='1' and rx_clk_gen'event ) then
476
 
477
          -- remember last state and increment internal counter
478
 
479
          last_state <= state;
480
          last_state_dly <= last_state;  -- for viewing only
481
 
482
          if(count < 65535) then
483
             cnttmp := count+1;
484
          else
485
             cnttmp := count ;
486
          end if;
487
 
488
 
489
          case state is
490
 
491
            when S_IDLE  => if( start='1' ) then
492
 
493
                                if( data_only='1' ) then    -- data only then skip preamble
494
                                   if (ENABLE_SHIFT16 = 0) then
495
                                     state <= S_DST;
496
                                   else
497
                                                                     state <= S_Dword32Aligned;
498
                                                                   end if;
499
                                    cnttmp  := 0;
500
 
501
                                elsif (iprmble_len=0) then
502
 
503
                                    state <= S_SFD ;
504
 
505
                                else
506
 
507
                                    state   <= S_PRMBL;
508
                                    cnttmp  := 1;
509
 
510
                                end if;
511
 
512
                            end if;
513
 
514
                            rxdata  <= (others => 'X' );
515
 
516
 
517
 
518
            when S_PRMBL => if( iprmble_len <= cnttmp ) then   -- one earlier
519
                                  state  <= S_SFD;
520
                            end if;
521
                            rxdata  <= X"55";
522
 
523
 
524
            when S_SFD   =>  state  <= S_DST;
525
                             cnttmp := 0;
526
 
527
                            if( iprmbl_err = '1' ) then
528
 
529
                                rxdata <= X"F5";  -- preamble error
530
 
531
                            else
532
 
533
                                rxdata <= X"D5";
534
 
535
                            end if;
536
 
537
 
538
                        when S_Dword32Aligned =>
539
 
540
                            if (count = 1) then
541
                                state <= S_DST;
542
                                                                cnttmp := 0;
543
                                                         end if;
544
 
545
                                                        case count is
546
                                                         when 0|1    => rxdata <= X"00";
547
                                                         when others => null;
548
                                                        end case;
549
 
550
            when S_DST   => if( count = 5) then
551
 
552
                                state  <= S_SRC;
553
                                cnttmp := 0;
554
 
555
                            end if;
556
 
557
                            if( mac_reverse='1' ) then
558
 
559
                                hi := 47-(count*8);
560
                                lo := 40-(count*8);
561
 
562
                            else
563
 
564
                                hi := (count*8)+7;
565
                                lo := (count*8);
566
 
567
                            end if;
568
 
569
                            rxdata(7 downto 0) <= idst(hi downto lo);
570
 
571
 
572
            when S_SRC   => if( count = 5) then
573
 
574
                                if( ipause_gen='1' ) then
575
 
576
                                    state  <= S_PAUSE;
577
 
578
                                elsif( ivlan_en='1' ) then
579
 
580
                                    state  <= S_TAG ;      -- VLAN follows
581
 
582
                                else
583
 
584
                                    state  <= S_LEN ;      -- normal frame
585
 
586
                                end if;
587
                                cnttmp := 0;
588
 
589
                            end if;
590
 
591
                            if( mac_reverse='1' ) then
592
 
593
                                hi := 47-(count*8);
594
                                lo := 40-(count*8);
595
 
596
                            else
597
 
598
                                hi := (count*8)+7;
599
                                lo := (count*8);
600
 
601
                            end if;
602
 
603
                            rxdata(7 downto 0) <= isrc(hi downto lo);
604
 
605
 
606
            when S_PAUSE =>
607
 
608
                            if(   count=0 ) then rxdata <= X"88";
609
                            elsif(count=1 ) then rxdata <= X"08";
610
                            elsif(count=2 ) then
611
 
612
                                if (wrong_pause_op='0') then
613
 
614
                                        rxdata <= X"00";
615
 
616
                                else
617
 
618
                                        rxdata <= X"03" ;
619
 
620
                                end if ;
621
 
622
                            elsif(count=3 ) then rxdata <= X"01";
623
                            elsif(count=4 ) then rxdata <= pquant(15 downto 8);
624
                            elsif(count=5 ) then
625
 
626
                                    rxdata <= pquant(7 downto 0);
627
 
628
                                    if (wrong_pause_lgth='1') then
629
 
630
                                        state <= S_LEN ;
631
 
632
                                    elsif( ipad_en='1' ) then
633
 
634
                                        state <= S_PAD;
635
 
636
                                    else
637
 
638
                                        state <= S_CRC;     -- error non-padded pause frame
639
 
640
                                    end if;
641
 
642
                                    cnttmp := 0;
643
 
644
                            end if;
645
 
646
            when S_TAG  =>  if(   count=0 ) then   rxdata <= X"81";
647
                            elsif(count=1 ) then   rxdata <= X"00";
648
                            elsif(count=2 ) then   rxdata <= ivlan_ctl(15 downto 8);
649
                            elsif(count=3 ) then
650
 
651
                                    rxdata <= ivlan_ctl(7  downto 0);
652
 
653
                                    if (istack_en='0') then
654
 
655
                                        state  <= S_LEN;
656
                                        cnttmp := 0;
657
 
658
                                     else
659
 
660
                                        state  <= S_STACK;
661
                                        cnttmp := 0;
662
 
663
                                     end if ;
664
 
665
                            end if;
666
 
667
            when S_STACK  =>  if(   count=0 ) then   rxdata <= X"81";
668
                              elsif(count=1 ) then   rxdata <= X"00";
669
                              elsif(count=2 ) then   rxdata <= ivlan_ctl(15 downto 8);
670
                              elsif(count=3 ) then
671
 
672
                                    rxdata <= ivlan_ctl(7  downto 0);
673
 
674
                                    state  <= S_LEN;
675
                                    cnttmp := 0;
676
 
677
                            end if;
678
 
679
            when S_LEN  =>
680
 
681
                           if( count = 0) then
682
 
683
                                if ( frmtype /= 0 ) then
684
 
685
                                    if (wrong_pause_lgth='1') then
686
 
687
                                        rxdata <= (others=>'0') ;
688
 
689
                                    else
690
 
691
                                        rxdata <= frmtype(15 downto 8);
692
 
693
                                    end if ;
694
 
695
                                else
696
 
697
                                    if (wrong_pause_lgth='1') then
698
 
699
                                        rxdata <= (others=>'0') ;
700
 
701
                                    else
702
 
703
                                        rxdata <= ilen(15 downto 8);      -- MSB
704
 
705
                                    end if ;
706
 
707
                                end if;
708
 
709
                            elsif( count=1 ) then
710
 
711
                                if( frmtype /= 0 ) then
712
 
713
                                    if (wrong_pause_lgth='1') then
714
 
715
                                        rxdata <= (others=>'0') ;
716
 
717
                                    else
718
 
719
                                        rxdata <= frmtype(7 downto 0);
720
 
721
                                    end if ;
722
 
723
                                else
724
 
725
                                    if (wrong_pause_lgth='1') then
726
 
727
                                        rxdata <= (others=>'0') ;
728
 
729
                                    else
730
 
731
                                        rxdata <= ilen(7 downto 0);       -- LSB
732
 
733
                                    end if ;
734
 
735
                                end if;
736
 
737
                                -- if zero length frame go directly to pad
738
 
739
                                if( ilen = 0 ) then
740
 
741
                                    if( idata_only='1' and iend_err='1') then
742
 
743
                                        state <= S_ENDERR;
744
 
745
                                    elsif( idata_only='1' ) then
746
 
747
                                        state <= S_IDLE;           -- stop immediately
748
 
749
                                    elsif( ipad_en = '1' ) then
750
 
751
                                        state <= S_PAD;
752
 
753
                                    else
754
 
755
                                        state <= S_CRC;
756
 
757
                                    end if;
758
                                else
759
 
760
                                    state <= S_DATA;
761
 
762
                                end if;
763
 
764
                                cnttmp := 0;
765
 
766
                            end if;
767
 
768
 
769
 
770
            when S_DATA   =>
771
 
772
 
773
                if (imagic='0') then
774
 
775
                              if(   count = 0) then
776
 
777
                                    if (wrong_pause_lgth='1') then
778
 
779
                                        rxdata <= (others=>'0') ;
780
 
781
                                    else
782
 
783
                                        rxdata  <= conv_std_logic_vector(icntstart,8);  -- first the init                                        
784
 
785
                                    end if ;
786
 
787
                                    datacnt <= icntstart;
788
 
789
                              elsif(count = 1 ) then
790
 
791
                                    if (wrong_pause_lgth='1') then
792
 
793
                                        rxdata <= (others=>'0') ;
794
 
795
                                    else
796
 
797
                                        rxdata  <= conv_std_logic_vector(icntstep,8);   -- then the step
798
 
799
                                    end if ;
800
 
801
                              else
802
 
803
                                   if (wrong_pause_lgth='1') then
804
 
805
                                        rxdata <= (others=>'0') ;
806
 
807
                                    else
808
 
809
                                        rxdata  <= conv_std_logic_vector(datacnt,8);    -- then data
810
 
811
                                    end if ;
812
 
813
                                    datacnt <= (datacnt + icntstep) mod 256;
814
 
815
                              end if;
816
 
817
 
818
                              -- check end of payload
819
 
820
                              if( count >= (conv_integer(ilen)-1) ) then
821
 
822
                                 if( idata_only='1') then
823
 
824
                                    if( iend_err='1' ) then
825
 
826
                                        state <= S_ENDERR;
827
 
828
                                    elsif( iipg_len /= 0 ) then
829
 
830
                                        state <= S_IPG;
831
                                        cnttmp := 0;
832
 
833
                                    else
834
 
835
                                        state <= S_IDLE;
836
 
837
                                    end if;
838
 
839
                                 elsif( (poscnt < (60-1)) and ipad_en='1' ) then  -- need to pad ?
840
 
841
                                    state <= S_PAD;
842
 
843
                                 else
844
 
845
                                    state <= S_CRC;
846
                                    cnttmp := 0;
847
 
848
                                 end if;
849
 
850
                                 -- modify last data byte if payload error was requested
851
 
852
                                 if( ipayload_err='1' ) then
853
 
854
                                    rxdata <= rxdata;  -- just keep the old value signals error
855
 
856
                                 end if;
857
 
858
                              end if;
859
 
860
                else
861
 
862
                   -- Magic Packet Generation
863
                   -- -----------------------
864
 
865
                        if (count=0 or count=1 or count=2 or count=3 or count=4 or count=5) then
866
 
867
                                rxdata <= X"55" ;
868
 
869
                        elsif (count=6 or count=12 or count=18 or count=24 or count=30 or count=36) then
870
 
871
                                rxdata <= idst(7 downto 0) ;
872
 
873
                        elsif (count=7 or count=13 or count=19 or count=25 or count=31 or count=37) then
874
 
875
                                rxdata <= idst(15 downto 8) ;
876
 
877
                        elsif (count=8 or count=14 or count=20 or count=26 or count=32 or count=38) then
878
 
879
                                rxdata <= idst(23 downto 16) ;
880
 
881
                        elsif (count=9 or count=15 or count=21 or count=27 or count=33 or count=39) then
882
 
883
                                rxdata <= idst(31 downto 24) ;
884
 
885
                        elsif (count=10 or count=16 or count=22 or count=28 or count=34 or count=40) then
886
 
887
                                rxdata <= idst(39 downto 32) ;
888
 
889
                        elsif (count=11 or count=17 or count=23 or count=29 or count=35) then -- or count=41) then
890
 
891
                                rxdata <= idst(47 downto 40) ;
892
 
893
                        elsif (count=41) then
894
 
895
                                state  <= S_PAD;
896
                                cnttmp := 0;
897
                                rxdata <= idst(47 downto 40) ;
898
 
899
                        end if ;
900
 
901
                end if ;
902
 
903
             when S_PAD    => rxdata <= (others => '0');   -- PAD BYTE
904
 
905
                              if( poscnt >= (60-1) ) then
906
 
907
                                  state <= S_CRC;
908
                                  cnttmp := 0;
909
 
910
                              end if;
911
 
912
 
913
             when S_CRC    => hi := 31-(count*8);
914
 
915
                              -- send CRC inverted, MSB of most significant byte first
916
 
917
                              for i in 0 to 7 loop
918
 
919
                                  rxdata(i) <= crc32(hi-i) xor '1' ;  -- first LSB is CRC MSB
920
 
921
                              end loop;
922
 
923
                              if( count=2 and icrc_err='1') then
924
 
925
                                  rxdata <= rxdata xor X"FF";   -- produce some wrong number
926
 
927
                              end if;
928
 
929
 
930
                              if( count=3) then
931
 
932
                                  if( iend_err='1' ) then
933
 
934
                                    state <= S_ENDERR;
935
 
936
                                  elsif( iipg_len > 0 ) then
937
 
938
                                    state <= S_IPG;
939
                                    cnttmp := 1;
940
 
941
                                  else
942
 
943
                                    state <= S_IDLE;
944
 
945
                                  end if;
946
 
947
                              end if;
948
 
949
 
950
            when S_ENDERR  =>  if( iipg_len = 0 ) then    -- delay dv going low by one cycle
951
 
952
                                    state <= S_IDLE;
953
 
954
                               else
955
 
956
                                    state <= S_IPG;
957
                                    cnttmp := 1;
958
 
959
                               end if;
960
 
961
 
962
            when S_IPG     =>  if( count >= iipg_len ) then   -- wait after last
963
 
964
                                    state <= S_IDLE;
965
 
966
                               end if;
967
 
968
             end case;
969
 
970
 
971
 
972
             -- load the counter with the new value                   
973
 
974
             count <= cnttmp;
975
 
976
 
977
      end if;
978
   end process;
979
 
980
 
981
 
982
end behave;
983
 
984
 

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