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-- -------------------------------------------------------------------------
-- -------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $RCSfile: ethgen2.vhd,v $
-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/vhdl/ethernet_model/gen/ethgen2.vhd,v $
--
-- $Revision: #1 $
-- $Date: 2008/08/09 $
-- Check in by : $Author: sc-build $
-- Author      : SKNg/TTChong
--
-- Project     : Triple Speed Ethernet - 10/100/1000 MAC
--
-- Description : (Simulation only)
--
-- MII Interface Ethernet Traffic Generator
-- 
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-- -------------------------------------------------------------------------
-- -------------------------------------------------------------------------
 
 
 
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
 
entity ETHGENERATOR2 is
 
    generic (  THOLD  : time := 1 ns);
 
    port (
 
      reset         : in std_logic ;     -- active high
 
        -- GMII receive interface: To be connected to MAC RX
 
      rx_clk        : in std_logic ;
      rxd           : out std_logic_vector(7 downto 0);
      rx_dv         : out std_logic;
      rx_er         : out std_logic;
 
        -- Additional FIFO controls for FIFO test scenarios
 
      sop           : out std_logic;   -- pulse with first character
      eop           : out std_logic;   -- pulse with last  character
 
       -- Mode of Operation
      ethernet_speed: in std_logic;
      mii_mode      : in std_logic;   -- 4-bit Nibbles (Fast Ethernet)
      rgmii_mode    : in std_logic;   -- 4-bit DDR (Reduced Gigabit)
 
 
        -- Frame Contents definitions
 
      mac_reverse   : in std_logic;                     -- 1: dst/src are sent MSB first
      dst           : in std_logic_vector(47 downto 0); -- destination address
      src           : in std_logic_vector(47 downto 0); -- source address
 
      prmble_len    : in integer range 0 to 40;         -- length of preamble
      pquant        : in std_logic_vector(15 downto 0); -- Pause Quanta value
      vlan_ctl      : in std_logic_vector(15 downto 0); -- VLAN control info
      len           : in std_logic_vector(15 downto 0); -- Length of payload
      frmtype       : in std_logic_vector(15 downto 0); -- if non-null: type field instead length
 
      cntstart      : in integer range 0 to 255;  -- payload data counter start (first byte of payload)
      cntstep       : in integer range 0 to 255;  -- payload counter step (2nd byte in paylaod)
 
      ipg_len       : in integer range 0 to 32768;  -- inter packet gap (delay after CRC)  
      wrong_pause_op: in std_logic ;                    -- Generate Pause Frame with Wrong Opcode       
      wrong_pause_lgth : in std_logic ;                    -- Generate Pause Frame with Wrong Opcode       
 
       -- Control
 
      payload_err   : in std_logic;  -- generate payload pattern error (last payload byte is wrong)
      prmbl_err     : in std_logic;
      crc_err       : in std_logic;
      vlan_en       : in std_logic;
      pause_gen     : in std_logic;
      pad_en        : in std_logic;
      phy_err       : in std_logic;
      end_err       : in std_logic;  -- keep rx_dv high one cycle after end of frame
      magic         : in std_logic;
      stack_vlan    : in std_logic;
 
      data_only     : in std_logic;  -- if set omits preamble, padding, CRC
 
      start         : in  std_logic;
      done          : out std_logic );
 
end ETHGENERATOR2 ;
 
architecture behave of ETHGENERATOR2 is
 
 
        -- GMII Generator
        -- --------------
 
        component ETHGENERATOR is
 
        generic (  THOLD  : time := 0.1 ns);
 
        port (
 
            reset         : in std_logic ;     -- active high
            rx_clk        : in std_logic ;
            enable        : in std_logic ;
            rxd           : out std_logic_vector(7 downto 0);
            rx_dv         : out std_logic;
            rx_er         : out std_logic;
            sop           : out std_logic;   -- pulse with first character
            eop           : out std_logic;   -- pulse with last  character
            mac_reverse   : in std_logic;                     -- 1: dst/src are sent MSB first
            dst           : in std_logic_vector(47 downto 0); -- destination address
            src           : in std_logic_vector(47 downto 0); -- source address
            prmble_len    : in integer range 0 to 40;         -- length of preamble
            pquant        : in std_logic_vector(15 downto 0); -- Pause Quanta value
            vlan_ctl      : in std_logic_vector(15 downto 0); -- VLAN control info
            len           : in std_logic_vector(15 downto 0); -- Length of payload
            frmtype       : in std_logic_vector(15 downto 0); -- if non-null: type field instead length
            cntstart      : in integer range 0 to 255;  -- payload data counter start (first byte of payload)
            cntstep       : in integer range 0 to 255;  -- payload counter step (2nd byte in paylaod)
            ipg_len       : in integer range 0 to 32768;  -- inter packet gap (delay after CRC)  
            payload_err   : in std_logic;  -- generate payload pattern error (last payload byte is wrong)
            prmbl_err     : in std_logic;
            crc_err       : in std_logic;
            vlan_en       : in std_logic;
            wrong_pause_op: in std_logic ;                    -- Generate Pause Frame with Wrong Opcode       
            wrong_pause_lgth : in std_logic ;                    -- Generate Pause Frame with Wrong Opcode       
            pause_gen     : in std_logic;
            pad_en        : in std_logic;
            phy_err       : in std_logic;
            end_err       : in std_logic;  -- keep rx_dv high one cycle after end of frame
            magic         : in std_logic;
            stack_vlan    : in std_logic;
            data_only     : in std_logic;  -- if set omits preamble, padding, CRC
            start         : in  std_logic;
            done          : out std_logic );
 
        end component ;
 
 
            -- GMII Generator Clock input and Outputs
 
        signal gmii_clk      : std_logic ;
        signal gmii_d        : std_logic_vector(7 downto 0);
        signal gmii_en       : std_logic;
        signal gmii_en_d     : std_logic;
        signal gmii_er       : std_logic;
        signal sop_gen       : std_logic;   -- pulse with first character
        signal eop_gen       : std_logic;   -- pulse with last  character
        signal done_gen      : std_logic;
 
        signal eop_int       : std_logic;   -- pulse with last  character
 
        signal sop_m         : std_logic;
        signal eop_m         : std_logic;
 
        signal start_gen     : std_logic_vector(1 downto 0);
 
        signal clk_div2 : std_logic;
 
        signal nib1     : std_logic_vector(3 downto 0);
 
        signal rgmii_en_er : std_logic;
        signal rgmii_dat   : std_logic_vector(3 downto 0);
        signal rgmii_dat_f : std_logic_vector(3 downto 0);  -- save upper nibble for falling edge
 
        signal mii_en   : std_logic;
        signal mii_er   : std_logic;
        signal mii_dat  : std_logic_vector(3 downto 0);
 
 
        signal gmii_err_d                       : std_logic;
        signal gmii_10_100_en_d         : std_logic;
        signal gmii_10_100_err_d        : std_logic;
        signal rgmii_10_100_en_er       : std_logic;
        signal rgmii_10_100_en_er_d     : std_logic;
        signal rgmii_10_100_en_er_d2: std_logic;
        signal rgmii_en_er_f            : std_logic;
        signal rgmii_10_100_en_er_f     : std_logic;
 
 
begin
 
        -- divide clock for nibble transfers 8-bit pathes
 
        process(reset, rx_clk)
        begin
                if(reset='1') then
 
                        clk_div2  <= '0';
                        start_gen <= "00";
 
                elsif( rx_clk'event and rx_clk='1') then
 
                        clk_div2 <= not(clk_div2);
 
                        if( start='1' ) then
 
                                start_gen <= (others => '1');
 
                        else
 
                                start_gen(1 downto 0) <= '0' & start_gen(1);  -- make it longer for MII mode
 
                        end if;
 
 
                end if;
 
        end process;
 
        -- multiplex GMII into RGMII/MII
 
        process(reset, gmii_clk)
        begin
                if(reset='1' ) then
 
                        rgmii_en_er <= '0';
                                                rgmii_en_er_f <= '0';
                        rgmii_dat   <= (others => '0');
                        rgmii_dat_f <= (others => '0');
 
                        sop_m <= '0';
                        eop_m <= '0';
                        gmii_en_d  <= '0';
                        gmii_err_d  <= '0';
 
                elsif( gmii_clk'event ) then   -- DDR
 
                        if( gmii_clk='1') then
 
                                gmii_en_d <= gmii_en;
                                done      <= done_gen and not(gmii_en);
 
                                -- FIFO signaling in right clock edge
 
                                sop_m   <= sop_gen;
                                eop_int <= eop_gen;
 
                                if( (mii_mode='1' or rgmii_mode = '1') and ethernet_speed ='0') then       -- not in MII, then EOP is 1 clock cycle already
 
                                        eop_m <= '0';
 
                                else
 
                                        eop_m <= eop_gen;
 
                                end if;
 
                                -- Data and Control
 
                                rgmii_en_er <= gmii_en after THOLD;
                                rgmii_dat   <= gmii_d(3 downto 0) after THOLD;
                                rgmii_dat_f <= gmii_d(7 downto 4);
 
                                mii_en      <= gmii_en after THOLD;
                                mii_er      <= gmii_er after THOLD;
 
                        else
                                rgmii_en_er <= (gmii_er xor gmii_en_d) after THOLD;
                                rgmii_dat   <= rgmii_dat_f after THOLD;   -- produce upper nibble 
 
                                if( (mii_mode='1' or rgmii_mode = '1') and ethernet_speed ='0') then
 
                                        sop_m     <= '0';
                                        eop_m     <= eop_int;
 
                                end if;
 
 
                        end if;
                end if;
 
        end process;
 
        -- connect clock
 
--        gmii_clk <= rx_clk when mii_mode='0' else clk_div2;
 
        process (rgmii_mode, mii_mode,ethernet_speed,clk_div2, rx_clk )
          begin
 
          if( ethernet_speed ='0') then
                  if (rgmii_mode ='1'or mii_mode ='1') then
                  gmii_clk <= clk_div2;
                  end if;
          else
 
                  gmii_clk <= rx_clk;
 
          end if;
 
        end process;
        -- connect output ports
 
        rxd(7 downto 4) <= "0000"      when (rgmii_mode='1' or mii_mode='1' or reset='1') else gmii_d(7 downto 4) after THOLD;
        rxd(3 downto 0) <= rgmii_dat   when (rgmii_mode='1' or mii_mode='1' or reset='1') else gmii_d(3 downto 0) after THOLD;
 
        rx_dv           <= '0' when reset='1' else
                           rgmii_en_er when rgmii_mode='1' else
                           mii_en      when mii_mode='1' else
                           gmii_en after THOLD;
 
        rx_er           <= '0' when reset='1' else
                           '0'         when rgmii_mode='1' else
                           mii_er      when mii_mode='1' else
                           gmii_er after THOLD;
 
 
        sop <= sop_m after THOLD when (rgmii_mode='1' or mii_mode='1') else sop_gen after THOLD;
        eop <= eop_m after THOLD when (rgmii_mode='1' or mii_mode='1') else eop_gen after THOLD;
 
 
 GMII_GEN: ETHGENERATOR   generic map (  THOLD => 0.1 ns )
 
        port map (
 
        reset          => reset,         -- active high
        rx_clk         => gmii_clk,
        enable         => '1',
        rxd            => gmii_d,
        rx_dv          => gmii_en,
        rx_er          => gmii_er,
        sop            => sop_gen,
        eop            => eop_gen,
 
        mac_reverse    => mac_reverse,
        dst            => dst,
        src            => src,
        prmble_len     => prmble_len,
        pquant         => pquant,
        vlan_ctl       => vlan_ctl,
        len            => len,
        frmtype        => frmtype,
        cntstart       => cntstart,
        cntstep        => cntstep,
        ipg_len        => ipg_len,
        payload_err    =>  payload_err,
        prmbl_err      =>  prmbl_err,
        crc_err        =>  crc_err,
        wrong_pause_op => wrong_pause_op ,
        wrong_pause_lgth=>wrong_pause_lgth ,
        vlan_en        =>  vlan_en,
        pause_gen      =>  pause_gen,
        pad_en         =>  pad_en,
        phy_err        =>  phy_err,
        end_err        =>  end_err,
        magic          =>  magic ,
        stack_vlan     =>  stack_vlan,
        data_only      =>  data_only,
        start          =>  start_gen(0),
        done           =>  done_gen  );
 
end behave;
 
 

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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [model/] [ethgen2.vhd] - Blame information for rev 42

Line No.	Rev	Author	Line
1	42	lmaarsen	`-- -------------------------------------------------------------------------`
2			`-- -------------------------------------------------------------------------`
3			`--`
4			`-- Revision Control Information`
5			`--`
6			`-- $RCSfile: ethgen2.vhd,v $`
7			`-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/vhdl/ethernet_model/gen/ethgen2.vhd,v $`
8			`--`
9			`-- $Revision: #1 $`
10			`-- $Date: 2008/08/09 $`
11			`-- Check in by : $Author: sc-build $`
12			`-- Author : SKNg/TTChong`
13			`--`
14			`-- Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`--`
16			`-- Description : (Simulation only)`
17			`--`
18			`-- MII Interface Ethernet Traffic Generator`
19			`--`
20			`-- ALTERA Confidential and Proprietary`
21			`-- Copyright 2006 (c) Altera Corporation`
22			`-- All rights reserved`
23			`--`
24			`-- -------------------------------------------------------------------------`
25			`-- -------------------------------------------------------------------------`
26
27
28
29			`library ieee ;`
30			`use ieee.std_logic_1164.all ;`
31			`use ieee.std_logic_arith.all ;`
32			`use ieee.std_logic_unsigned.all ;`
33
34			`entity ETHGENERATOR2 is`
35
36			`generic ( THOLD : time := 1 ns);`
37
38			`port (`
39
40			`reset : in std_logic ; -- active high`
41
42			`-- GMII receive interface: To be connected to MAC RX`
43
44			`rx_clk : in std_logic ;`
45			`rxd : out std_logic_vector(7 downto 0);`
46			`rx_dv : out std_logic;`
47			`rx_er : out std_logic;`
48
49			`-- Additional FIFO controls for FIFO test scenarios`
50
51			`sop : out std_logic; -- pulse with first character`
52			`eop : out std_logic; -- pulse with last character`
53
54			`-- Mode of Operation`
55			`ethernet_speed: in std_logic;`
56			`mii_mode : in std_logic; -- 4-bit Nibbles (Fast Ethernet)`
57			`rgmii_mode : in std_logic; -- 4-bit DDR (Reduced Gigabit)`
58
59
60			`-- Frame Contents definitions`
61
62			`mac_reverse : in std_logic; -- 1: dst/src are sent MSB first`
63			`dst : in std_logic_vector(47 downto 0); -- destination address`
64			`src : in std_logic_vector(47 downto 0); -- source address`
65
66			`prmble_len : in integer range 0 to 40; -- length of preamble`
67			`pquant : in std_logic_vector(15 downto 0); -- Pause Quanta value`
68			`vlan_ctl : in std_logic_vector(15 downto 0); -- VLAN control info`
69			`len : in std_logic_vector(15 downto 0); -- Length of payload`
70			`frmtype : in std_logic_vector(15 downto 0); -- if non-null: type field instead length`
71
72			`cntstart : in integer range 0 to 255; -- payload data counter start (first byte of payload)`
73			`cntstep : in integer range 0 to 255; -- payload counter step (2nd byte in paylaod)`
74
75			`ipg_len : in integer range 0 to 32768; -- inter packet gap (delay after CRC)`
76			`wrong_pause_op: in std_logic ; -- Generate Pause Frame with Wrong Opcode`
77			`wrong_pause_lgth : in std_logic ; -- Generate Pause Frame with Wrong Opcode`
78
79			`-- Control`
80
81			`payload_err : in std_logic; -- generate payload pattern error (last payload byte is wrong)`
82			`prmbl_err : in std_logic;`
83			`crc_err : in std_logic;`
84			`vlan_en : in std_logic;`
85			`pause_gen : in std_logic;`
86			`pad_en : in std_logic;`
87			`phy_err : in std_logic;`
88			`end_err : in std_logic; -- keep rx_dv high one cycle after end of frame`
89			`magic : in std_logic;`
90			`stack_vlan : in std_logic;`
91
92			`data_only : in std_logic; -- if set omits preamble, padding, CRC`
93
94			`start : in std_logic;`
95			`done : out std_logic );`
96
97			`end ETHGENERATOR2 ;`
98
99			`architecture behave of ETHGENERATOR2 is`
100
101
102			`-- GMII Generator`
103			`-- --------------`
104
105			`component ETHGENERATOR is`
106
107			`generic ( THOLD : time := 0.1 ns);`
108
109			`port (`
110
111			`reset : in std_logic ; -- active high`
112			`rx_clk : in std_logic ;`
113			`enable : in std_logic ;`
114			`rxd : out std_logic_vector(7 downto 0);`
115			`rx_dv : out std_logic;`
116			`rx_er : out std_logic;`
117			`sop : out std_logic; -- pulse with first character`
118			`eop : out std_logic; -- pulse with last character`
119			`mac_reverse : in std_logic; -- 1: dst/src are sent MSB first`
120			`dst : in std_logic_vector(47 downto 0); -- destination address`
121			`src : in std_logic_vector(47 downto 0); -- source address`
122			`prmble_len : in integer range 0 to 40; -- length of preamble`
123			`pquant : in std_logic_vector(15 downto 0); -- Pause Quanta value`
124			`vlan_ctl : in std_logic_vector(15 downto 0); -- VLAN control info`
125			`len : in std_logic_vector(15 downto 0); -- Length of payload`
126			`frmtype : in std_logic_vector(15 downto 0); -- if non-null: type field instead length`
127			`cntstart : in integer range 0 to 255; -- payload data counter start (first byte of payload)`
128			`cntstep : in integer range 0 to 255; -- payload counter step (2nd byte in paylaod)`
129			`ipg_len : in integer range 0 to 32768; -- inter packet gap (delay after CRC)`
130			`payload_err : in std_logic; -- generate payload pattern error (last payload byte is wrong)`
131			`prmbl_err : in std_logic;`
132			`crc_err : in std_logic;`
133			`vlan_en : in std_logic;`
134			`wrong_pause_op: in std_logic ; -- Generate Pause Frame with Wrong Opcode`
135			`wrong_pause_lgth : in std_logic ; -- Generate Pause Frame with Wrong Opcode`
136			`pause_gen : in std_logic;`
137			`pad_en : in std_logic;`
138			`phy_err : in std_logic;`
139			`end_err : in std_logic; -- keep rx_dv high one cycle after end of frame`
140			`magic : in std_logic;`
141			`stack_vlan : in std_logic;`
142			`data_only : in std_logic; -- if set omits preamble, padding, CRC`
143			`start : in std_logic;`
144			`done : out std_logic );`
145
146			`end component ;`
147
148
149			`-- GMII Generator Clock input and Outputs`
150
151			`signal gmii_clk : std_logic ;`
152			`signal gmii_d : std_logic_vector(7 downto 0);`
153			`signal gmii_en : std_logic;`
154			`signal gmii_en_d : std_logic;`
155			`signal gmii_er : std_logic;`
156			`signal sop_gen : std_logic; -- pulse with first character`
157			`signal eop_gen : std_logic; -- pulse with last character`
158			`signal done_gen : std_logic;`
159
160			`signal eop_int : std_logic; -- pulse with last character`
161
162			`signal sop_m : std_logic;`
163			`signal eop_m : std_logic;`
164
165			`signal start_gen : std_logic_vector(1 downto 0);`
166
167			`signal clk_div2 : std_logic;`
168
169			`signal nib1 : std_logic_vector(3 downto 0);`
170
171			`signal rgmii_en_er : std_logic;`
172			`signal rgmii_dat : std_logic_vector(3 downto 0);`
173			`signal rgmii_dat_f : std_logic_vector(3 downto 0); -- save upper nibble for falling edge`
174
175			`signal mii_en : std_logic;`
176			`signal mii_er : std_logic;`
177			`signal mii_dat : std_logic_vector(3 downto 0);`
178
179
180			`signal gmii_err_d : std_logic;`
181			`signal gmii_10_100_en_d : std_logic;`
182			`signal gmii_10_100_err_d : std_logic;`
183			`signal rgmii_10_100_en_er : std_logic;`
184			`signal rgmii_10_100_en_er_d : std_logic;`
185			`signal rgmii_10_100_en_er_d2: std_logic;`
186			`signal rgmii_en_er_f : std_logic;`
187			`signal rgmii_10_100_en_er_f : std_logic;`
188
189
190			`begin`
191
192			`-- divide clock for nibble transfers 8-bit pathes`
193
194			`process(reset, rx_clk)`
195			`begin`
196			`if(reset='1') then`
197
198			`clk_div2 <= '0';`
199			`start_gen <= "00";`
200
201			`elsif( rx_clk'event and rx_clk='1') then`
202
203			`clk_div2 <= not(clk_div2);`
204
205			`if( start='1' ) then`
206
207			`start_gen <= (others => '1');`
208
209			`else`
210
211			`start_gen(1 downto 0) <= '0' & start_gen(1); -- make it longer for MII mode`
212
213			`end if;`
214
215
216			`end if;`
217
218			`end process;`
219
220			`-- multiplex GMII into RGMII/MII`
221
222			`process(reset, gmii_clk)`
223			`begin`
224			`if(reset='1' ) then`
225
226			`rgmii_en_er <= '0';`
227			`rgmii_en_er_f <= '0';`
228			`rgmii_dat <= (others => '0');`
229			`rgmii_dat_f <= (others => '0');`
230
231			`sop_m <= '0';`
232			`eop_m <= '0';`
233			`gmii_en_d <= '0';`
234			`gmii_err_d <= '0';`
235
236			`elsif( gmii_clk'event ) then -- DDR`
237
238			`if( gmii_clk='1') then`
239
240			`gmii_en_d <= gmii_en;`
241			`done <= done_gen and not(gmii_en);`
242
243			`-- FIFO signaling in right clock edge`
244
245			`sop_m <= sop_gen;`
246			`eop_int <= eop_gen;`
247
248			`if( (mii_mode='1' or rgmii_mode = '1') and ethernet_speed ='0') then -- not in MII, then EOP is 1 clock cycle already`
249
250			`eop_m <= '0';`
251
252			`else`
253
254			`eop_m <= eop_gen;`
255
256			`end if;`
257
258			`-- Data and Control`
259
260			`rgmii_en_er <= gmii_en after THOLD;`
261			`rgmii_dat <= gmii_d(3 downto 0) after THOLD;`
262			`rgmii_dat_f <= gmii_d(7 downto 4);`
263
264			`mii_en <= gmii_en after THOLD;`
265			`mii_er <= gmii_er after THOLD;`
266
267			`else`
268			`rgmii_en_er <= (gmii_er xor gmii_en_d) after THOLD;`
269			`rgmii_dat <= rgmii_dat_f after THOLD; -- produce upper nibble`
270
271			`if( (mii_mode='1' or rgmii_mode = '1') and ethernet_speed ='0') then`
272
273			`sop_m <= '0';`
274			`eop_m <= eop_int;`
275
276			`end if;`
277
278
279			`end if;`
280			`end if;`
281
282			`end process;`
283
284			`-- connect clock`
285
286			`-- gmii_clk <= rx_clk when mii_mode='0' else clk_div2;`
287
288			`process (rgmii_mode, mii_mode,ethernet_speed,clk_div2, rx_clk )`
289			`begin`
290
291			`if( ethernet_speed ='0') then`
292			`if (rgmii_mode ='1'or mii_mode ='1') then`
293			`gmii_clk <= clk_div2;`
294			`end if;`
295			`else`
296
297			`gmii_clk <= rx_clk;`
298
299			`end if;`
300
301			`end process;`
302			`-- connect output ports`
303
304			`rxd(7 downto 4) <= "0000" when (rgmii_mode='1' or mii_mode='1' or reset='1') else gmii_d(7 downto 4) after THOLD;`
305			`rxd(3 downto 0) <= rgmii_dat when (rgmii_mode='1' or mii_mode='1' or reset='1') else gmii_d(3 downto 0) after THOLD;`
306
307			`rx_dv <= '0' when reset='1' else`
308			`rgmii_en_er when rgmii_mode='1' else`
309			`mii_en when mii_mode='1' else`
310			`gmii_en after THOLD;`
311
312			`rx_er <= '0' when reset='1' else`
313			`'0' when rgmii_mode='1' else`
314			`mii_er when mii_mode='1' else`
315			`gmii_er after THOLD;`
316
317
318			`sop <= sop_m after THOLD when (rgmii_mode='1' or mii_mode='1') else sop_gen after THOLD;`
319			`eop <= eop_m after THOLD when (rgmii_mode='1' or mii_mode='1') else eop_gen after THOLD;`
320
321
322			`GMII_GEN: ETHGENERATOR generic map ( THOLD => 0.1 ns )`
323
324			`port map (`
325
326			`reset => reset, -- active high`
327			`rx_clk => gmii_clk,`
328			`enable => '1',`
329			`rxd => gmii_d,`
330			`rx_dv => gmii_en,`
331			`rx_er => gmii_er,`
332			`sop => sop_gen,`
333			`eop => eop_gen,`
334
335			`mac_reverse => mac_reverse,`
336			`dst => dst,`
337			`src => src,`
338			`prmble_len => prmble_len,`
339			`pquant => pquant,`
340			`vlan_ctl => vlan_ctl,`
341			`len => len,`
342			`frmtype => frmtype,`
343			`cntstart => cntstart,`
344			`cntstep => cntstep,`
345			`ipg_len => ipg_len,`
346			`payload_err => payload_err,`
347			`prmbl_err => prmbl_err,`
348			`crc_err => crc_err,`
349			`wrong_pause_op => wrong_pause_op ,`
350			`wrong_pause_lgth=>wrong_pause_lgth ,`
351			`vlan_en => vlan_en,`
352			`pause_gen => pause_gen,`
353			`pad_en => pad_en,`
354			`phy_err => phy_err,`
355			`end_err => end_err,`
356			`magic => magic ,`
357			`stack_vlan => stack_vlan,`
358			`data_only => data_only,`
359			`start => start_gen(0),`
360			`done => done_gen );`
361
362			`end behave;`
363
364