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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [model/] [loopback_adapter.vhd] - Blame information for rev 42

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1 42 lmaarsen
-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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--
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-- Revision Control Information
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--
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-- $RCSfile: altera_tse_timing_adapter8.v,v $
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-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/timing_adapter/altera_tse_timing_adapter8.v,v $
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--
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-- $Revision: #1 $
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-- $Date: 2008/08/09 $
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-- Check in by : $Author: sc-build $
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-- Author      : SKNg
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--
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-- Project     : Triple Speed Ethernet - 10/100/1000 MAC
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--
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-- Description : SIMULATION ONLY
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--
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-- AVALON STREAMING TIMING ADAPTER FOR 8BIT IMPLEMENTATION
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-- 
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-- ALTERA Confidential and Proprietary
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-- Copyright 2006 (c) Altera Corporation
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-- All rights reserved
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--
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_arith.all ;
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use ieee.std_logic_unsigned.all ;
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entity loopback_adapter is
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port (
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  -- Interface: clk                     
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  clk                  : in std_logic;
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  reset                : in std_logic;
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  -- Interface: in
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  in_ready              : out std_logic;
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  in_valid              : in  std_logic;
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  in_data               : in  std_logic_vector (7 downto 0);
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  in_startofpacket      : in  std_logic;
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  in_endofpacket        : in  std_logic;
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  in_error              : in  std_logic_vector(4 downto 0);
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  -- Interface: out
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  out_ready             : in std_logic;
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  out_valid             : out std_logic;
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  out_data              : out std_logic_vector (7 downto 0);
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  out_startofpacket     : out std_logic;
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  out_endofpacket       : out std_logic;
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  out_error             : out std_logic
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);
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end loopback_adapter;
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architecture Behav of loopback_adapter is
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   -- Component instantiated by Turbo autoplace on 20/02/2008 at 23:58:54
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   COMPONENT loopback_adapter_fifo
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        generic (
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          DEPTH      : integer := 2048;
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          DATA_WIDTH : integer := 11;
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          ADDR_WIDTH : integer := 11
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        );
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         PORT
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         (
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                 clk            :       IN  STD_LOGIC;
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                 reset          :       IN  STD_LOGIC;
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                 in_valid   :   in  std_logic;
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                 in_data    :   in  std_logic_vector(10 downto 0);
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                 out_ready      :       IN  STD_LOGIC;
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                 in_ready       :       out  STD_LOGIC;
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                 out_valid  :   out  std_logic;
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                 out_data   :   out  std_logic_vector(10 downto 0);
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                 fill_level :   out  std_logic_vector(11 downto 0)
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         );
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   END COMPONENT;
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   -- ---------------------------------------------------------------------
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   --| Signal Declarations
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   -- ---------------------------------------------------------------------
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   signal in_payload    : std_logic_vector(10 downto 0);
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   signal out_payload   : std_logic_vector(10 downto 0);
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   signal in_ready_wire : std_logic;
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   signal out_valid_wire: std_logic;
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   signal fifo_fill     : std_logic_vector(11 downto 0);
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   signal ready         : std_logic;
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   signal in_err        : std_logic;
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begin
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   -- ---------------------------------------------------------------------
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   --| Payload Mapping
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   -- ---------------------------------------------------------------------
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   process (in_data,in_startofpacket,in_endofpacket,in_error,out_payload)
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   begin
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     in_err <= in_error(0) or in_error(1) or in_error(2) or in_error(3) or in_error(4);
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     in_payload <= in_data & in_startofpacket & in_endofpacket & in_err;
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     out_data           <= out_payload(10 downto 3);
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     out_startofpacket  <= out_payload(2);
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     out_endofpacket    <= out_payload(1);
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     out_error          <= out_payload(0);
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   end process;
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   -- ---------------------------------------------------------------------
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   --| FIFO
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   -- ---------------------------------------------------------------------
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   u_loopback_fifo: loopback_adapter_fifo
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   port map
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     (
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       clk       => clk,
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       reset     => reset,
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       in_ready  => open,
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       in_valid  => in_valid,
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       in_data   => in_payload,
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       out_ready => ready,
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       out_valid => out_valid_wire,
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       out_data  => out_payload,
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       fill_level=> fifo_fill
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       );
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   -- ---------------------------------------------------------------------
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   --| Ready & valid signals.
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   -- ---------------------------------------------------------------------
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   process (fifo_fill, out_valid_wire, out_ready)
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    begin
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      if (fifo_fill < 48) then
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        in_ready <= '1';
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      else
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        in_ready <= '0';
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      end if;
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      out_valid <= out_valid_wire;
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      ready <= out_ready;
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   end process;
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end behav;
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