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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [model/] [loopback_adapter_fifo.vhd] - Blame information for rev 56

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Line No. Rev Author Line
1 42 lmaarsen 
-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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--
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-- Revision Control Information
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--
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-- $RCSfile: altera_tse_timing_adapter_fifo8.v,v $
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-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/timing_adapter/altera_tse_timing_adapter_fifo8.v,v $
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--
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-- $Revision: #1 $
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-- $Date: 2008/08/09 $
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-- Check in by : $Author: sc-build $
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-- Author      : SKNg
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--
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-- Project     : Triple Speed Ethernet - 10/100/1000 MAC
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--
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-- Description : SIMULATION ONLY
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--
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-- simple atlantic fifo FOR 8BIT IMPLEMENTATION
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--
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-- ALTERA Confidential and Proprietary
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-- Copyright 2006 (c) Altera Corporation
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-- All rights reserved
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--
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_arith.all ;
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use ieee.std_logic_unsigned.all ;
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 ENTITY  loopback_adapter_fifo is
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     generic (
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       DEPTH      : integer := 2048;
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       DATA_WIDTH : integer := 11;
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       ADDR_WIDTH : integer := 11
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     );
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         PORT
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         (
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                 clk            :       IN  STD_LOGIC;
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                 reset          :       IN  STD_LOGIC;
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                 in_valid   :   in  std_logic;
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                 in_data    :   in  std_logic_vector(10 downto 0);
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                 out_ready      :       IN  STD_LOGIC;
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                 in_ready       :       out  STD_LOGIC;
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                 out_valid  :   out  std_logic;
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                 out_data   :   out  std_logic_vector(10 downto 0);
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                 fill_level :   out  std_logic_vector(11 downto 0)
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         );
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   end loopback_adapter_fifo;
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  architecture behav of loopback_adapter_fifo is
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   -- use array to define the bunch of internal temparary signals
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   type ram_type is array (0 to DEPTH-1) of
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        std_logic_vector(DATA_WIDTH-1 downto 0);
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   signal mem: ram_type;
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   -- ---------------------------------------------------------------------
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   --| Signals
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   -- ---------------------------------------------------------------------
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   signal wr_addr                       : std_logic_vector (ADDR_WIDTH-1 downto 0);
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   signal rd_addr                       : std_logic_vector (ADDR_WIDTH-1 downto 0);
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   signal next_wr_addr          : std_logic_vector (ADDR_WIDTH-1 downto 0);
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   signal next_rd_addr          : std_logic_vector (ADDR_WIDTH-1 downto 0);
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   signal mem_rd_addr           : std_logic_vector (ADDR_WIDTH-1 downto 0);
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   signal empty                 : std_logic;
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   signal full                  : std_logic;
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   signal out_ready_vector      : std_logic;
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   signal j                             : integer;
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   signal enable_reading        : std_logic;
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   signal out_valid_r   : std_logic;
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   signal in_ready_r   : std_logic;
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   begin
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   -- ---------------------------------------------------------------------
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   --| FIFO Status
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   -- ---------------------------------------------------------------------
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   process (out_ready,wr_addr,rd_addr,full)
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   begin
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      out_ready_vector                                  <= out_ready;
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      in_ready_r                                        <= not (full);
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      next_wr_addr                                      <= wr_addr + 1;
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      next_rd_addr                                      <= rd_addr + 1;
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      fill_level(ADDR_WIDTH-1 downto 0) <= wr_addr - rd_addr;
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      fill_level(ADDR_WIDTH)                    <= '0';
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      if (full = '1') then
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           fill_level <= conv_std_logic_vector(DEPTH, 12);
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          end if;
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   end process;
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  -- ---------------------------------------------------------------------
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  --| Manage Pointers
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  -- ---------------------------------------------------------------------
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  process (reset,clk)
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   begin
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     if (reset = '1') then
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            enable_reading <= '0';
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     elsif (rising_edge(clk)) then
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                 if (empty = '1') then
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                        enable_reading <= '0';
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             else
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                  if (in_data(1) = '1' and in_valid = '1') then
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                   enable_reading <= '1';
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                  end if;
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             end if;
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         end if;
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   end process;
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   process (reset,clk)
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   begin
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    if (reset = '1') then
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          wr_addr  <= (others => '0');
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          rd_addr  <= (others => '0');
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          empty    <= '1';
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          rd_addr  <= (others => '0');
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          full     <= '0';
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          out_valid_r <= '0';
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     elsif (rising_edge(clk)) then
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          out_valid_r <= enable_reading;
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          if (in_ready_r = '1' and in_valid = '1') then
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             wr_addr <= next_wr_addr;
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             empty   <= '0';
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          end if;
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          if (next_wr_addr = rd_addr) then
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             full <= '1';
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          end if;
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          if (out_ready_vector ='1' and  out_valid_r = '1') then
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            rd_addr <= next_rd_addr;
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            full    <= '0';
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                if (next_rd_addr = wr_addr) then
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                  empty     <= '1';
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                  out_valid_r <= '0';
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                 end if;
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           end if;
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         if (out_ready_vector = '1' and out_valid_r = '1' and in_ready_r = '1' and in_valid = '1') then
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           full  <= full;
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           empty <= empty;
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          end if;
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      end if;
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   end process;
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   process (rd_addr,out_ready,out_valid_r,next_rd_addr)
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   begin
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      mem_rd_addr <= rd_addr;
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      if (out_ready = '1' and out_valid_r = '1') then
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        mem_rd_addr <= next_rd_addr;
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      end if;
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   end process;
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   --assign output
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   out_valid <= out_valid_r;
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   in_ready <= in_ready_r;
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   -- ---------------------------------------------------------------------
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   --| Infer Memory
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   -- ---------------------------------------------------------------------
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   process (reset,clk)
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   begin
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      if (reset = '1') then
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             for i in 0 to (DEPTH-1) loop
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              mem(conv_integer(i)) <= (others => '0');
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                 end loop;
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      elsif (rising_edge(clk)) then
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         if (in_ready_r = '1' and in_valid = '1')       then
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           mem(conv_integer(wr_addr)) <= in_data;
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                 end if;
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         out_data <= mem(conv_integer(mem_rd_addr));
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      end if;
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   end process;
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   end behav;

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