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-- -------------------------------------------------------------------------
-- -------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $RCSfile: mdio_reg.vhd,v $
-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/vhdl/mdio/mdio_reg.vhd,v $
--
-- $Revision: #1 $
-- $Date: 2008/08/09 $
-- Check in by : $Author: sc-build $
-- Author      : SKNg/TTChong
--
-- Project     : Triple Speed Ethernet - 10/100/1000 MAC
--
-- Description : (Simulation only)
--
-- MDIO Slave's Register Map
-- Instantiated in top_mdio_slave (top_mdio_slave.vhd)
--
-- 
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-- -------------------------------------------------------------------------
-- -------------------------------------------------------------------------
 
 
library ieee ;
use     ieee.std_logic_1164.all ;
use     ieee.std_logic_arith.all ;
use     ieee.std_logic_unsigned.all ;
 
entity mdio_reg_sim is port (
 
        reset           : in std_logic ;
        clk             : in std_logic ;                        -- MDIO 2.5MHz Clock
 
   -- MDIO Controller Interface
   -- -------------------------
 
    reg_addr        : in std_logic_vector(4 downto 0);      -- Address Register
        reg_write       : in std_logic;                         -- Write Register       
        reg_read        : in std_logic;                         -- Read Register        
        reg_dout        : out std_logic_vector(15 downto 0);    -- Data Bus OUT
        reg_din         : in std_logic_vector(15 downto 0) ;    -- Data Bus IN
 
   -- Status
   -- ------
 
        conf_done       : out std_logic) ;                      -- PHY Config Done
 
end mdio_reg_sim ;
 
architecture a of mdio_reg_sim is
 
    signal reg_0            : std_logic_vector(15 downto 0) ;
    signal reg_1            : std_logic_vector(15 downto 0) ;
    signal reg_2            : std_logic_vector(15 downto 0) ;
    signal reg_3            : std_logic_vector(15 downto 0) ;
    signal reg_4            : std_logic_vector(15 downto 0) ;
    signal reg_5            : std_logic_vector(15 downto 0) ;
    signal reg_6            : std_logic_vector(15 downto 0) ;
    signal reg_7            : std_logic_vector(15 downto 0) ;
    signal reg_8            : std_logic_vector(15 downto 0) ;
    signal reg_9            : std_logic_vector(15 downto 0) ;
    signal reg_10           : std_logic_vector(15 downto 0) ;
    signal reg_11           : std_logic_vector(15 downto 0) ;
    signal reg_12           : std_logic_vector(15 downto 0) ;
    signal reg_13           : std_logic_vector(15 downto 0) ;
    signal reg_14           : std_logic_vector(15 downto 0) ;
    signal reg_15           : std_logic_vector(15 downto 0) ;
    signal reg_16           : std_logic_vector(15 downto 0) ;
    signal reg_17           : std_logic_vector(15 downto 0) ;
    signal reg_18           : std_logic_vector(15 downto 0) ;
    signal reg_19           : std_logic_vector(15 downto 0) ;
    signal reg_20           : std_logic_vector(15 downto 0) ;
    signal reg_21           : std_logic_vector(15 downto 0) ;
    signal reg_22           : std_logic_vector(15 downto 0) ;
    signal reg_23           : std_logic_vector(15 downto 0) ;
    signal reg_24           : std_logic_vector(15 downto 0) ;
    signal reg_25           : std_logic_vector(15 downto 0) ;
    signal reg_26           : std_logic_vector(15 downto 0) ;
    signal reg_27           : std_logic_vector(15 downto 0) ;
    signal reg_28           : std_logic_vector(15 downto 0) ;
    signal reg_29           : std_logic_vector(15 downto 0) ;
    signal reg_30           : std_logic_vector(15 downto 0) ;
    signal reg_31           : std_logic_vector(15 downto 0) ;
 
begin
 
   -- MDIO Registers
   -- --------------
 
        process(reset, clk)
        begin
 
                if (reset='1') then
 
                        reg_0  <= (others=>'0') ;
                        reg_1  <= (others=>'0') ;
                        reg_2  <= (others=>'0') ;
                        reg_3  <= (others=>'0') ;
                        reg_4  <= (others=>'0') ;
                        reg_5  <= (others=>'0') ;
                        reg_6  <= (others=>'0') ;
                        reg_7  <= (others=>'0') ;
                        reg_8  <= (others=>'0') ;
                        reg_9  <= (others=>'0') ;
                        reg_10 <= (others=>'0') ;
                        reg_11 <= (others=>'0') ;
                        reg_12 <= (others=>'0') ;
                        reg_13 <= (others=>'0') ;
                        reg_14 <= (others=>'0') ;
                        reg_15 <= (others=>'0') ;
                        reg_16 <= (others=>'0') ;
                        reg_17 <= (others=>'0') ;
                        reg_18 <= (others=>'0') ;
                        reg_19 <= (others=>'0') ;
                        reg_20 <= (others=>'0') ;
                        reg_21 <= (others=>'0') ;
                        reg_22 <= (others=>'0') ;
                        reg_23 <= (others=>'0') ;
                        reg_24 <= (others=>'0') ;
                        reg_25 <= (others=>'0') ;
                        reg_26 <= (others=>'0') ;
                        reg_27 <= (others=>'0') ;
                        reg_28 <= (others=>'0') ;
                        reg_29 <= (others=>'0') ;
                        reg_30 <= (others=>'0') ;
                        reg_31 <= (others=>'0') ;
 
                        conf_done           <= '0' ;
 
                elsif (clk='1') and (clk'event) then
 
                        if (reg_write='1') then
 
                                if (reg_addr="00000") then
 
                                        reg_0     <= reg_din ;
                                        conf_done <= '1' ;
 
                                elsif (reg_addr="00001") then
 
                                        reg_1 <= reg_din ;
 
                                elsif (reg_addr="00010") then
 
                                        reg_2 <= reg_din ;
 
                                elsif (reg_addr="00011") then
 
                                        reg_3 <= reg_din ;
 
                                elsif (reg_addr="00100") then
 
                                        reg_4 <= reg_din ;
 
                                elsif (reg_addr="00101") then
 
                                        reg_5 <= reg_din ;
 
                                elsif (reg_addr="00110") then
 
                                        reg_6 <= reg_din ;
 
                                elsif (reg_addr="00111") then
 
                                        reg_7 <= reg_din ;
 
                                elsif (reg_addr="01000") then
 
                                        reg_8 <= reg_din ;
 
                                elsif (reg_addr="01001") then
 
                                        reg_9 <= reg_din ;
 
                                elsif (reg_addr="01010") then
 
                                        reg_10 <= reg_din ;
 
                                elsif (reg_addr="01011") then
 
                                        reg_11 <= reg_din ;
 
                                elsif (reg_addr="01100") then
 
                                        reg_12 <= reg_din ;
 
                                elsif (reg_addr="01101") then
 
                                        reg_13 <= reg_din ;
 
                                elsif (reg_addr="01110") then
 
                                        reg_14 <= reg_din ;
 
                                elsif (reg_addr="01111") then
 
                                        reg_15 <= reg_din ;
 
                                elsif (reg_addr="10000") then
 
                                        reg_16 <= reg_din ;
 
                                elsif (reg_addr="10001") then
 
                                        reg_17 <= reg_din ;
 
                                elsif (reg_addr="10010") then
 
                                        reg_18 <= reg_din ;
 
                                elsif (reg_addr="10011") then
 
                                        reg_19 <= reg_din ;
 
                                elsif (reg_addr="10100") then
 
                                        reg_20 <= reg_din ;
 
                                elsif (reg_addr="10101") then
 
                                        reg_21 <= reg_din ;
 
                                elsif (reg_addr="10110") then
 
                                        reg_22 <= reg_din ;
 
                                elsif (reg_addr="10111") then
 
                                        reg_23 <= reg_din ;
 
                                elsif (reg_addr="11000") then
 
                                        reg_24 <= reg_din ;
 
                                elsif (reg_addr="11001") then
 
                                        reg_25 <= reg_din ;
 
                                elsif (reg_addr="11010") then
 
                                        reg_26 <= reg_din ;
 
                                elsif (reg_addr="11011") then
 
                                        reg_27 <= reg_din ;
 
                                elsif (reg_addr="11100") then
 
                                        reg_28 <= reg_din ;
 
                                elsif (reg_addr="11101") then
 
                                        reg_29 <= reg_din ;
 
                                elsif (reg_addr="11110") then
 
                                        reg_30 <= reg_din ;
 
                                elsif (reg_addr="11111") then
 
                                        reg_31 <= reg_din ;
 
                                end if ;
 
                        end if ;
 
                end if ;
 
        end process ;
 
   -- Data MUX
   -- --------
 
        process(reg_addr, reg_write)
        begin
 
                if (reg_addr="00000") then
 
                        reg_dout <= reg_0 ;
 
                elsif (reg_addr="00001") then
 
                        reg_dout <= reg_1 ;
 
                elsif (reg_addr="00010") then
 
                        reg_dout <= reg_2 ;
 
                elsif (reg_addr="00011") then
 
                        reg_dout <= reg_3 ;
 
                elsif (reg_addr="00100") then
 
                        reg_dout <= reg_4 ;
 
                elsif (reg_addr="00101") then
 
                        reg_dout <= reg_5 ;
 
                elsif (reg_addr="00110") then
 
                        reg_dout <= reg_6 ;
 
                elsif (reg_addr="00111") then
 
                        reg_dout <= reg_7 ;
 
                elsif (reg_addr="01000") then
 
                        reg_dout <= reg_8 ;
 
                elsif (reg_addr="01001") then
 
                        reg_dout <= reg_9 ;
 
                elsif (reg_addr="01010") then
 
                        reg_dout <= reg_10 ;
 
                elsif (reg_addr="01011") then
 
                        reg_dout <= reg_11 ;
 
                elsif (reg_addr="01100") then
 
                        reg_dout <= reg_12 ;
 
                elsif (reg_addr="01101") then
 
                        reg_dout <= reg_13 ;
 
                elsif (reg_addr="01110") then
 
                        reg_dout <= reg_14 ;
 
                elsif (reg_addr="01111") then
 
                        reg_dout <= reg_15 ;
 
                elsif (reg_addr="10000") then
 
                        reg_dout <= reg_16 ;
 
                elsif (reg_addr="10001") then
 
                        reg_dout <= reg_17 ;
 
                elsif (reg_addr="10010") then
 
                        reg_dout <= reg_18 ;
 
                elsif (reg_addr="10011") then
 
                        reg_dout <= reg_19 ;
 
                elsif (reg_addr="10100") then
 
                        reg_dout <= reg_20 ;
 
                elsif (reg_addr="10101") then
 
                        reg_dout <= reg_21 ;
 
                elsif (reg_addr="10110") then
 
                        reg_dout <= reg_22 ;
 
                elsif (reg_addr="10111") then
 
                        reg_dout <= reg_23 ;
 
                elsif (reg_addr="11000") then
 
                        reg_dout <= reg_24 ;
 
                elsif (reg_addr="11001") then
 
                        reg_dout <= reg_25 ;
 
                elsif (reg_addr="11010") then
 
                        reg_dout <= reg_26 ;
 
                elsif (reg_addr="11011") then
 
                        reg_dout <= reg_27 ;
 
                elsif (reg_addr="11100") then
 
                        reg_dout <= reg_28 ;
 
                elsif (reg_addr="11101") then
 
                        reg_dout <= reg_29 ;
 
                elsif (reg_addr="11110") then
 
                        reg_dout <= reg_30 ;
 
                elsif (reg_addr="11111") then
 
                        reg_dout <= reg_31 ;
 
                end if ;
 
        end process ;
 
end a ;

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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [model/] [mdio_reg.vhd] - Blame information for rev 56

Line No.	Rev	Author	Line
1	42	lmaarsen	`-- -------------------------------------------------------------------------`
2			`-- -------------------------------------------------------------------------`
3			`--`
4			`-- Revision Control Information`
5			`--`
6			`-- $RCSfile: mdio_reg.vhd,v $`
7			`-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/vhdl/mdio/mdio_reg.vhd,v $`
8			`--`
9			`-- $Revision: #1 $`
10			`-- $Date: 2008/08/09 $`
11			`-- Check in by : $Author: sc-build $`
12			`-- Author : SKNg/TTChong`
13			`--`
14			`-- Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`--`
16			`-- Description : (Simulation only)`
17			`--`
18			`-- MDIO Slave's Register Map`
19			`-- Instantiated in top_mdio_slave (top_mdio_slave.vhd)`
20			`--`
21			`--`
22			`-- ALTERA Confidential and Proprietary`
23			`-- Copyright 2006 (c) Altera Corporation`
24			`-- All rights reserved`
25			`--`
26			`-- -------------------------------------------------------------------------`
27			`-- -------------------------------------------------------------------------`
28
29
30			`library ieee ;`
31			`use ieee.std_logic_1164.all ;`
32			`use ieee.std_logic_arith.all ;`
33			`use ieee.std_logic_unsigned.all ;`
34
35			`entity mdio_reg_sim is port (`
36
37			`reset : in std_logic ;`
38			`clk : in std_logic ; -- MDIO 2.5MHz Clock`
39
40			`-- MDIO Controller Interface`
41			`-- -------------------------`
42
43			`reg_addr : in std_logic_vector(4 downto 0); -- Address Register`
44			`reg_write : in std_logic; -- Write Register`
45			`reg_read : in std_logic; -- Read Register`
46			`reg_dout : out std_logic_vector(15 downto 0); -- Data Bus OUT`
47			`reg_din : in std_logic_vector(15 downto 0) ; -- Data Bus IN`
48
49			`-- Status`
50			`-- ------`
51
52			`conf_done : out std_logic) ; -- PHY Config Done`
53
54			`end mdio_reg_sim ;`
55
56			`architecture a of mdio_reg_sim is`
57
58			`signal reg_0 : std_logic_vector(15 downto 0) ;`
59			`signal reg_1 : std_logic_vector(15 downto 0) ;`
60			`signal reg_2 : std_logic_vector(15 downto 0) ;`
61			`signal reg_3 : std_logic_vector(15 downto 0) ;`
62			`signal reg_4 : std_logic_vector(15 downto 0) ;`
63			`signal reg_5 : std_logic_vector(15 downto 0) ;`
64			`signal reg_6 : std_logic_vector(15 downto 0) ;`
65			`signal reg_7 : std_logic_vector(15 downto 0) ;`
66			`signal reg_8 : std_logic_vector(15 downto 0) ;`
67			`signal reg_9 : std_logic_vector(15 downto 0) ;`
68			`signal reg_10 : std_logic_vector(15 downto 0) ;`
69			`signal reg_11 : std_logic_vector(15 downto 0) ;`
70			`signal reg_12 : std_logic_vector(15 downto 0) ;`
71			`signal reg_13 : std_logic_vector(15 downto 0) ;`
72			`signal reg_14 : std_logic_vector(15 downto 0) ;`
73			`signal reg_15 : std_logic_vector(15 downto 0) ;`
74			`signal reg_16 : std_logic_vector(15 downto 0) ;`
75			`signal reg_17 : std_logic_vector(15 downto 0) ;`
76			`signal reg_18 : std_logic_vector(15 downto 0) ;`
77			`signal reg_19 : std_logic_vector(15 downto 0) ;`
78			`signal reg_20 : std_logic_vector(15 downto 0) ;`
79			`signal reg_21 : std_logic_vector(15 downto 0) ;`
80			`signal reg_22 : std_logic_vector(15 downto 0) ;`
81			`signal reg_23 : std_logic_vector(15 downto 0) ;`
82			`signal reg_24 : std_logic_vector(15 downto 0) ;`
83			`signal reg_25 : std_logic_vector(15 downto 0) ;`
84			`signal reg_26 : std_logic_vector(15 downto 0) ;`
85			`signal reg_27 : std_logic_vector(15 downto 0) ;`
86			`signal reg_28 : std_logic_vector(15 downto 0) ;`
87			`signal reg_29 : std_logic_vector(15 downto 0) ;`
88			`signal reg_30 : std_logic_vector(15 downto 0) ;`
89			`signal reg_31 : std_logic_vector(15 downto 0) ;`
90
91			`begin`
92
93			`-- MDIO Registers`
94			`-- --------------`
95
96			`process(reset, clk)`
97			`begin`
98
99			`if (reset='1') then`
100
101			`reg_0 <= (others=>'0') ;`
102			`reg_1 <= (others=>'0') ;`
103			`reg_2 <= (others=>'0') ;`
104			`reg_3 <= (others=>'0') ;`
105			`reg_4 <= (others=>'0') ;`
106			`reg_5 <= (others=>'0') ;`
107			`reg_6 <= (others=>'0') ;`
108			`reg_7 <= (others=>'0') ;`
109			`reg_8 <= (others=>'0') ;`
110			`reg_9 <= (others=>'0') ;`
111			`reg_10 <= (others=>'0') ;`
112			`reg_11 <= (others=>'0') ;`
113			`reg_12 <= (others=>'0') ;`
114			`reg_13 <= (others=>'0') ;`
115			`reg_14 <= (others=>'0') ;`
116			`reg_15 <= (others=>'0') ;`
117			`reg_16 <= (others=>'0') ;`
118			`reg_17 <= (others=>'0') ;`
119			`reg_18 <= (others=>'0') ;`
120			`reg_19 <= (others=>'0') ;`
121			`reg_20 <= (others=>'0') ;`
122			`reg_21 <= (others=>'0') ;`
123			`reg_22 <= (others=>'0') ;`
124			`reg_23 <= (others=>'0') ;`
125			`reg_24 <= (others=>'0') ;`
126			`reg_25 <= (others=>'0') ;`
127			`reg_26 <= (others=>'0') ;`
128			`reg_27 <= (others=>'0') ;`
129			`reg_28 <= (others=>'0') ;`
130			`reg_29 <= (others=>'0') ;`
131			`reg_30 <= (others=>'0') ;`
132			`reg_31 <= (others=>'0') ;`
133
134			`conf_done <= '0' ;`
135
136			`elsif (clk='1') and (clk'event) then`
137
138			`if (reg_write='1') then`
139
140			`if (reg_addr="00000") then`
141
142			`reg_0 <= reg_din ;`
143			`conf_done <= '1' ;`
144
145			`elsif (reg_addr="00001") then`
146
147			`reg_1 <= reg_din ;`
148
149			`elsif (reg_addr="00010") then`
150
151			`reg_2 <= reg_din ;`
152
153			`elsif (reg_addr="00011") then`
154
155			`reg_3 <= reg_din ;`
156
157			`elsif (reg_addr="00100") then`
158
159			`reg_4 <= reg_din ;`
160
161			`elsif (reg_addr="00101") then`
162
163			`reg_5 <= reg_din ;`
164
165			`elsif (reg_addr="00110") then`
166
167			`reg_6 <= reg_din ;`
168
169			`elsif (reg_addr="00111") then`
170
171			`reg_7 <= reg_din ;`
172
173			`elsif (reg_addr="01000") then`
174
175			`reg_8 <= reg_din ;`
176
177			`elsif (reg_addr="01001") then`
178
179			`reg_9 <= reg_din ;`
180
181			`elsif (reg_addr="01010") then`
182
183			`reg_10 <= reg_din ;`
184
185			`elsif (reg_addr="01011") then`
186
187			`reg_11 <= reg_din ;`
188
189			`elsif (reg_addr="01100") then`
190
191			`reg_12 <= reg_din ;`
192
193			`elsif (reg_addr="01101") then`
194
195			`reg_13 <= reg_din ;`
196
197			`elsif (reg_addr="01110") then`
198
199			`reg_14 <= reg_din ;`
200
201			`elsif (reg_addr="01111") then`
202
203			`reg_15 <= reg_din ;`
204
205			`elsif (reg_addr="10000") then`
206
207			`reg_16 <= reg_din ;`
208
209			`elsif (reg_addr="10001") then`
210
211			`reg_17 <= reg_din ;`
212
213			`elsif (reg_addr="10010") then`
214
215			`reg_18 <= reg_din ;`
216
217			`elsif (reg_addr="10011") then`
218
219			`reg_19 <= reg_din ;`
220
221			`elsif (reg_addr="10100") then`
222
223			`reg_20 <= reg_din ;`
224
225			`elsif (reg_addr="10101") then`
226
227			`reg_21 <= reg_din ;`
228
229			`elsif (reg_addr="10110") then`
230
231			`reg_22 <= reg_din ;`
232
233			`elsif (reg_addr="10111") then`
234
235			`reg_23 <= reg_din ;`
236
237			`elsif (reg_addr="11000") then`
238
239			`reg_24 <= reg_din ;`
240
241			`elsif (reg_addr="11001") then`
242
243			`reg_25 <= reg_din ;`
244
245			`elsif (reg_addr="11010") then`
246
247			`reg_26 <= reg_din ;`
248
249			`elsif (reg_addr="11011") then`
250
251			`reg_27 <= reg_din ;`
252
253			`elsif (reg_addr="11100") then`
254
255			`reg_28 <= reg_din ;`
256
257			`elsif (reg_addr="11101") then`
258
259			`reg_29 <= reg_din ;`
260
261			`elsif (reg_addr="11110") then`
262
263			`reg_30 <= reg_din ;`
264
265			`elsif (reg_addr="11111") then`
266
267			`reg_31 <= reg_din ;`
268
269			`end if ;`
270
271			`end if ;`
272
273			`end if ;`
274
275			`end process ;`
276
277			`-- Data MUX`
278			`-- --------`
279
280			`process(reg_addr, reg_write)`
281			`begin`
282
283			`if (reg_addr="00000") then`
284
285			`reg_dout <= reg_0 ;`
286
287			`elsif (reg_addr="00001") then`
288
289			`reg_dout <= reg_1 ;`
290
291			`elsif (reg_addr="00010") then`
292
293			`reg_dout <= reg_2 ;`
294
295			`elsif (reg_addr="00011") then`
296
297			`reg_dout <= reg_3 ;`
298
299			`elsif (reg_addr="00100") then`
300
301			`reg_dout <= reg_4 ;`
302
303			`elsif (reg_addr="00101") then`
304
305			`reg_dout <= reg_5 ;`
306
307			`elsif (reg_addr="00110") then`
308
309			`reg_dout <= reg_6 ;`
310
311			`elsif (reg_addr="00111") then`
312
313			`reg_dout <= reg_7 ;`
314
315			`elsif (reg_addr="01000") then`
316
317			`reg_dout <= reg_8 ;`
318
319			`elsif (reg_addr="01001") then`
320
321			`reg_dout <= reg_9 ;`
322
323			`elsif (reg_addr="01010") then`
324
325			`reg_dout <= reg_10 ;`
326
327			`elsif (reg_addr="01011") then`
328
329			`reg_dout <= reg_11 ;`
330
331			`elsif (reg_addr="01100") then`
332
333			`reg_dout <= reg_12 ;`
334
335			`elsif (reg_addr="01101") then`
336
337			`reg_dout <= reg_13 ;`
338
339			`elsif (reg_addr="01110") then`
340
341			`reg_dout <= reg_14 ;`
342
343			`elsif (reg_addr="01111") then`
344
345			`reg_dout <= reg_15 ;`
346
347			`elsif (reg_addr="10000") then`
348
349			`reg_dout <= reg_16 ;`
350
351			`elsif (reg_addr="10001") then`
352
353			`reg_dout <= reg_17 ;`
354
355			`elsif (reg_addr="10010") then`
356
357			`reg_dout <= reg_18 ;`
358
359			`elsif (reg_addr="10011") then`
360
361			`reg_dout <= reg_19 ;`
362
363			`elsif (reg_addr="10100") then`
364
365			`reg_dout <= reg_20 ;`
366
367			`elsif (reg_addr="10101") then`
368
369			`reg_dout <= reg_21 ;`
370
371			`elsif (reg_addr="10110") then`
372
373			`reg_dout <= reg_22 ;`
374
375			`elsif (reg_addr="10111") then`
376
377			`reg_dout <= reg_23 ;`
378
379			`elsif (reg_addr="11000") then`
380
381			`reg_dout <= reg_24 ;`
382
383			`elsif (reg_addr="11001") then`
384
385			`reg_dout <= reg_25 ;`
386
387			`elsif (reg_addr="11010") then`
388
389			`reg_dout <= reg_26 ;`
390
391			`elsif (reg_addr="11011") then`
392
393			`reg_dout <= reg_27 ;`
394
395			`elsif (reg_addr="11100") then`
396
397			`reg_dout <= reg_28 ;`
398
399			`elsif (reg_addr="11101") then`
400
401			`reg_dout <= reg_29 ;`
402
403			`elsif (reg_addr="11110") then`
404
405			`reg_dout <= reg_30 ;`
406
407			`elsif (reg_addr="11111") then`
408
409			`reg_dout <= reg_31 ;`
410
411			`end if ;`
412
413			`end process ;`
414
415			`end a ;`