<title>Sample Waveforms for esoc_ram_4kx1.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file esoc_ram_4kx1.vhd </CENTER></h2>
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<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design esoc_ram_4kx1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 1, 0, 1, 0, ...). The design esoc_ram_4kx1.vhd has two read/write ports. Read/write port A has 4096 words of 1 bits each and Read/write port B has 4096 words of 1 bits each. The output of the read/write port A is unregistered. The output of the read/write port B is registered by UNREGISTERED. </P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. </P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. During a write cycle on a port (A or B), the new data flows through to the output of the same port. </P>
