<title>Sample Waveforms for esoc_rom_2kx32.vhd </title>
4
</head>
5
<body>
6
<h2><CENTER>Sample behavioral waveforms for design file esoc_rom_2kx32.vhd </CENTER></h2>
7
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design esoc_rom_2kx32.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFFFFFF0, FFFFFFF1, FFFFFFF2, FFFFFFF3, ...). The design esoc_rom_2kx32.vhd has one read/write port. The read/write port has 2048 words of 32 bits each. The output of the read/write port is unregistered. </P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. Read enable port should be enabled for read The clock enable on the read side input registers are disabled. </P>
<P><FONT size=3>The above waveform shows the behavior of the design under read conditions with clears on input and/or output registers. The read happens at the rising edge of the enabled clock cycle. The read cycle is assumed to be from the rising edge of the clock cycle till the next rising clock edge. The clear on the output register is asynchronous. </P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. During a write cycle, the new data flows through to the output. </P>
