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--------------------------------------------------------------------------------
----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc
-- Last modified : Mon Apr 14 12:48:20 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc is
  port(
    esoc_address       : in     std_logic_vector(15 downto 0);
    esoc_areset        : in     std_logic;
    esoc_boot_complete : out    std_logic;
    esoc_clk           : in     std_logic;
    esoc_cs            : in     std_logic;
    esoc_data          : inout  std_logic_vector(31 downto 0);
    esoc_mdc           : out    std_logic_vector(esoc_port_count-1 downto 0);
    esoc_mdio          : inout  std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rd            : in     std_logic;
    esoc_rgmii_rxc     : in     std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_rxctl   : in     std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_rxd     : in     std_logic_vector(3+4*(esoc_port_count-1) downto 0);
    esoc_rgmii_txc     : out    std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_txctl   : out    std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_txd     : out    std_logic_vector(3+4*(esoc_port_count-1) downto 0);
    esoc_wait          : out    std_logic;
    esoc_wr            : in     std_logic);
end entity esoc;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc.structure
-- Last modified : Mon Apr 14 12:48:20 2014.
--------------------------------------------------------------------------------
 
architecture structure of esoc is
 
  signal clk_control         : std_logic;
  signal reset               : std_logic;
  signal clk_search          : STD_LOGIC;
  signal clk_data            : STD_LOGIC;
  signal data_req            : std_logic_vector(esoc_port_count-1 downto 0);
  signal data_gnt_wr         : std_logic_vector(esoc_port_count-1 downto 0);
  signal data_sof            : std_logic;
  signal data_eof            : std_logic;
  signal data                : std_logic_vector(63 downto 0);
  signal clk_rgmii_125m      : STD_LOGIC;
  signal clk_rgmii_25m       : STD_LOGIC;
  signal clk_rgmii_2m5       : STD_LOGIC;
  signal data_gnt_rd         : std_logic_vector(esoc_port_count-1 downto 0);
  signal ctrl_wait           : std_logic;
  signal ctrl_rddata         : std_logic_vector(31 downto 0);
  signal ctrl_rd             : std_logic;
  signal ctrl_wrdata         : std_logic_vector(31 downto 0);
  signal ctrl_wr             : std_logic;
  signal ctrl_address        : std_logic_vector(15 downto 0);
  signal search_req          : std_logic_vector(esoc_port_count-1 downto 0);
  signal search_sof          : std_logic;
  signal search_key          : std_logic_vector(63 downto 0);
  signal search_gnt_wr       : std_logic_vector(esoc_port_count-1 downto 0);
  signal search_eof          : std_logic;
  signal search_result_av    : std_logic;
  signal search_result       : std_logic_vector(esoc_port_count-1 downto 0);
  signal data_port_sel       : std_logic_vector(esoc_port_count-1 downto 0);
  signal search_port_stalled : std_logic_vector(esoc_port_count-1 downto 0);
  signal pll1_locked         : STD_LOGIC;
  signal pll2_locked         : STD_LOGIC;
  signal ctrl_brom_rd        : std_logic;
  signal ctrl_brom_address   : std_logic_vector(10 downto 0);
  signal q                   : STD_LOGIC_VECTOR(31 downto 0);
 
  component esoc_port
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control         : in     std_logic;
      clk_data            : in     std_logic;
      clk_rgmii_125m      : in     STD_LOGIC;
      clk_rgmii_25m       : in     STD_LOGIC;
      clk_rgmii_2m5       : in     STD_LOGIC;
      clk_search          : in     std_logic;
      ctrl_address        : in     std_logic_vector(15 downto 0);
      ctrl_rd             : in     std_logic;
      ctrl_rddata         : out    std_logic_vector(31 downto 0);
      ctrl_wait           : out    std_logic;
      ctrl_wr             : in     std_logic;
      ctrl_wrdata         : in     std_logic_vector(31 downto 0);
      data                : inout  std_logic_vector(63 downto 0);
      data_eof            : inout  std_logic;
      data_gnt_rd         : in     std_logic;
      data_gnt_wr         : in     std_logic;
      data_port_sel       : inout  std_logic_vector(esoc_port_count-1 downto 0);
      data_req            : out    std_logic;
      data_sof            : inout  std_logic;
      mdc                 : out    std_logic;
      mdio                : inout  std_logic;
      reset               : in     std_logic;
      rgmii_rxc           : in     std_logic;
      rgmii_rxctl         : in     std_logic;
      rgmii_rxd           : in     std_logic_vector(3 downto 0);
      rgmii_txc           : out    std_logic;
      rgmii_txctl         : out    std_logic;
      rgmii_txd           : out    std_logic_vector(3 downto 0);
      search_eof          : out    std_logic;
      search_gnt_wr       : in     std_logic;
      search_key          : out    std_logic_vector(63 downto 0);
      search_port_stalled : out    std_logic;
      search_req          : out    std_logic;
      search_result       : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av    : in     std_logic;
      search_sof          : out    std_logic);
  end component esoc_port;
 
  component esoc_control
    port(
      brom_address       : out    std_logic_vector(10 downto 0);
      brom_rd            : out    std_logic;
      brom_rddata        : in     std_logic_vector(31 downto 0);
      clk_control        : in     std_logic;
      ctrl_address       : out    std_logic_vector(15 downto 0);
      ctrl_rd            : out    std_logic;
      ctrl_rddata        : in     std_logic_vector(31 downto 0);
      ctrl_wait          : in     std_logic;
      ctrl_wr            : out    std_logic;
      ctrl_wrdata        : out    std_logic_vector(31 downto 0);
      esoc_address       : in     std_logic_vector(15 downto 0);
      esoc_boot_complete : out    std_logic;
      esoc_cs            : in     std_logic;
      esoc_data          : inout  std_logic_vector(31 downto 0);
      esoc_rd            : in     std_logic;
      esoc_wait          : out    std_logic;
      esoc_wr            : in     std_logic;
      pll1_locked        : in     STD_LOGIC;
      pll2_locked        : in     STD_LOGIC;
      reset              : in     std_logic);
  end component esoc_control;
 
  component esoc_reset
    port(
      clk_control : in     std_logic;
      esoc_areset : in     std_logic;
      pll1_locked : in     STD_LOGIC;
      pll2_locked : in     STD_LOGIC;
      reset       : out    std_logic);
  end component esoc_reset;
 
  component esoc_bus_arbiter
    generic(
      id : integer := 0);
    port(
      bus_eof      : in     std_logic;
      bus_gnt_rd   : out    std_logic_vector(esoc_port_count-1 downto 0);
      bus_gnt_wr   : out    std_logic_vector(esoc_port_count-1 downto 0);
      bus_req      : in     std_logic_vector(esoc_port_count-1 downto 0);
      bus_sof      : in     std_logic;
      clk_bus      : in     std_logic;
      clk_control  : in     std_logic;
      ctrl_address : in     std_logic_vector(15 downto 0);
      ctrl_rd      : in     std_logic;
      ctrl_rddata  : out    std_logic_vector(31 downto 0);
      ctrl_wait    : out    std_logic;
      ctrl_wr      : in     std_logic;
      ctrl_wrdata  : in     std_logic_vector(31 downto 0);
      reset        : in     std_logic);
  end component esoc_bus_arbiter;
 
  component esoc_search_engine
    port(
      clk_control         : in     std_logic;
      clk_search          : in     std_logic;
      ctrl_address        : in     std_logic_vector(15 downto 0);
      ctrl_rd             : in     std_logic;
      ctrl_rddata         : out    std_logic_vector(31 downto 0);
      ctrl_wait           : out    std_logic;
      ctrl_wr             : in     std_logic;
      ctrl_wrdata         : in     std_logic_vector(31 downto 0);
      reset               : in     std_logic;
      search_eof          : in     std_logic;
      search_key          : in     std_logic_vector(63 downto 0);
      search_port_stalled : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result       : out    std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av    : out    std_logic;
      search_sof          : in     std_logic);
  end component esoc_search_engine;
 
  component esoc_pll1_c3
    port(
      inclk0 : in     STD_LOGIC := '0';
      c0     : out    STD_LOGIC;
      c1     : out    STD_LOGIC;
      c2     : out    STD_LOGIC;
      locked : out    STD_LOGIC);
  end component esoc_pll1_c3;
 
  component esoc_pll2_c3
    port(
      inclk0 : in     STD_LOGIC := '0';
      c0     : out    STD_LOGIC;
      locked : out    STD_LOGIC;
      c1     : out    STD_LOGIC;
      c2     : out    STD_LOGIC);
  end component esoc_pll2_c3;
 
  component esoc_rom_2kx32
    port(
      aclr    : in     STD_LOGIC;
      address : in     STD_LOGIC_VECTOR(10 downto 0);
      clock   : in     STD_LOGIC;
      data    : in     STD_LOGIC_VECTOR(31 downto 0);
      rden    : in     STD_LOGIC;
      wren    : in     STD_LOGIC;
      q       : out    STD_LOGIC_VECTOR(31 downto 0));
  end component esoc_rom_2kx32;
 
begin
  --CLK IN: 
  --50MHz
  --CLK OUT:    
  --C0 50MHz
  --C1 100MHz
  --C2 150MHz
  --CLK IN: 
  --50MHz
  --CLK OUT:    
  --C0 125MHz
  --
  --eSoc Clocks and Reset
  --eSoc Host Control Interface
  --eSoc Ethernet ports
  --eSoc Search Engine
  --eSoc Data bus Arbiter
  --eSoc Search bus Arbiter
  --eSoc Boot ROM
  esoc_ports: for esoc_port_nr in esoc_port_count-1 downto 0 generate
  begin
    u0: esoc_port
      generic map(
        esoc_port_nr => esoc_port_nr)
      port map(
        clk_control         => clk_control,
        clk_data            => clk_data,
        clk_rgmii_125m      => clk_rgmii_125m,
        clk_rgmii_25m       => clk_rgmii_25m,
        clk_rgmii_2m5       => clk_rgmii_2m5,
        clk_search          => clk_search,
        ctrl_address        => ctrl_address,
        ctrl_rd             => ctrl_rd,
        ctrl_rddata         => ctrl_rddata,
        ctrl_wait           => ctrl_wait,
        ctrl_wr             => ctrl_wr,
        ctrl_wrdata         => ctrl_wrdata,
        data                => data,
        data_eof            => data_eof,
        data_gnt_rd         => data_gnt_rd(esoc_port_nr),
        data_gnt_wr         => data_gnt_wr(esoc_port_nr),
        data_port_sel       => data_port_sel,
        data_req            => data_req(esoc_port_nr),
        data_sof            => data_sof,
        mdc                 => esoc_mdc(esoc_port_nr),
        mdio                => esoc_mdio(esoc_port_nr),
        reset               => reset,
        rgmii_rxc           => esoc_rgmii_rxc(esoc_port_nr),
        rgmii_rxctl         => esoc_rgmii_rxctl(esoc_port_nr),
        rgmii_rxd           => esoc_rgmii_rxd(3+4*esoc_port_nr downto 4*esoc_port_nr),
        rgmii_txc           => esoc_rgmii_txc(esoc_port_nr),
        rgmii_txctl         => esoc_rgmii_txctl(esoc_port_nr),
        rgmii_txd           => esoc_rgmii_txd(3+4*esoc_port_nr downto 4*esoc_port_nr),
        search_eof          => search_eof,
        search_gnt_wr       => search_gnt_wr(esoc_port_nr),
        search_key          => search_key,
        search_port_stalled => search_port_stalled(esoc_port_nr),
        search_req          => search_req(esoc_port_nr),
        search_result       => search_result,
        search_result_av    => search_result_av,
        search_sof          => search_sof);
 
  end generate esoc_ports;
 
  -- TEST
  u0: esoc_control
    port map(
      brom_address       => ctrl_brom_address,
      brom_rd            => ctrl_brom_rd,
      brom_rddata        => q,
      clk_control        => clk_control,
      ctrl_address       => ctrl_address,
      ctrl_rd            => ctrl_rd,
      ctrl_rddata        => ctrl_rddata,
      ctrl_wait          => ctrl_wait,
      ctrl_wr            => ctrl_wr,
      ctrl_wrdata        => ctrl_wrdata,
      esoc_address       => esoc_address,
      esoc_boot_complete => esoc_boot_complete,
      esoc_cs            => esoc_cs,
      esoc_data          => esoc_data,
      esoc_rd            => esoc_rd,
      esoc_wait          => esoc_wait,
      esoc_wr            => esoc_wr,
      pll1_locked        => pll1_locked,
      pll2_locked        => pll2_locked,
      reset              => reset);
 
  u2: esoc_reset
    port map(
      clk_control => clk_control,
      esoc_areset => esoc_areset,
      pll1_locked => pll1_locked,
      pll2_locked => pll2_locked,
      reset       => reset);
 
  u4: esoc_bus_arbiter
    generic map(
      id => 0)
    port map(
      bus_eof      => data_eof,
      bus_gnt_rd   => data_gnt_rd,
      bus_gnt_wr   => data_gnt_wr,
      bus_req      => data_req,
      bus_sof      => data_sof,
      clk_bus      => clk_data,
      clk_control  => clk_control,
      ctrl_address => ctrl_address,
      ctrl_rd      => ctrl_rd,
      ctrl_rddata  => ctrl_rddata,
      ctrl_wait    => ctrl_wait,
      ctrl_wr      => ctrl_wr,
      ctrl_wrdata  => ctrl_wrdata,
      reset        => reset);
 
  u6: esoc_search_engine
    port map(
      clk_control         => clk_control,
      clk_search          => clk_search,
      ctrl_address        => ctrl_address,
      ctrl_rd             => ctrl_rd,
      ctrl_rddata         => ctrl_rddata,
      ctrl_wait           => ctrl_wait,
      ctrl_wr             => ctrl_wr,
      ctrl_wrdata         => ctrl_wrdata,
      reset               => reset,
      search_eof          => search_eof,
      search_key          => search_key,
      search_port_stalled => search_port_stalled,
      search_result       => search_result,
      search_result_av    => search_result_av,
      search_sof          => search_sof);
 
  u1: esoc_pll1_c3
    port map(
      inclk0 => esoc_clk,
      c0     => clk_control,
      c1     => clk_search,
      c2     => clk_data,
      locked => pll1_locked);
 
  u3: esoc_pll2_c3
    port map(
      inclk0 => esoc_clk,
      c0     => clk_rgmii_125m,
      locked => pll2_locked,
      c1     => clk_rgmii_25m,
      c2     => clk_rgmii_2m5);
 
  u5: esoc_bus_arbiter
    generic map(
      id => 1)
    port map(
      bus_eof      => search_eof,
      bus_gnt_rd   => open,
      bus_gnt_wr   => search_gnt_wr,
      bus_req      => search_req,
      bus_sof      => search_sof,
      clk_bus      => clk_search,
      clk_control  => clk_control,
      ctrl_address => ctrl_address,
      ctrl_rd      => ctrl_rd,
      ctrl_rddata  => ctrl_rddata,
      ctrl_wait    => ctrl_wait,
      ctrl_wr      => ctrl_wr,
      ctrl_wrdata  => ctrl_wrdata,
      reset        => reset);
 
  u7: esoc_rom_2kx32
    port map(
      aclr    => reset,
      address => ctrl_brom_address,
      clock   => clk_control,
      data    => (others => '0'),
      rden    => ctrl_brom_rd,
      wren    => '0',
      q       => q);
 
end architecture structure ; -- of esoc
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc.vhd] - Blame information for rev 42

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- Ethernet Switch on Configurable Logic IP Core ----`
4			`---- ----`
5			`---- This file is part of the ESoCL project ----`
6			`---- http://www.opencores.org/cores/esoc/ ----`
7			`---- ----`
8			`---- Description: see design description ESoCL_dd_71022001.pdf ----`
9			`---- ----`
10			`---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----`
11			`---- and/or release bulleting ESoCL_rb_71022001.pdf ----`
12			`---- ----`
13			`---- Author(s): L.Maarsen ----`
14			`---- Bert Maarsen, lmaarsen@opencores.org ----`
15			`---- ----`
16			`--------------------------------------------------------------------------------`
17			`---- ----`
18			`---- Copyright (C) 2009 Authors and OPENCORES.ORG ----`
19			`---- ----`
20			`---- This source file may be used and distributed without ----`
21			`---- restriction provided that this copyright statement is not ----`
22			`---- removed from the file and that any derivative work contains ----`
23			`---- the original copyright notice and the associated disclaimer. ----`
24			`---- ----`
25			`---- This source file is free software; you can redistribute it ----`
26			`---- and/or modify it under the terms of the GNU Lesser General ----`
27			`---- Public License as published by the Free Software Foundation; ----`
28			`---- either version 2.1 of the License, or (at your option) any ----`
29			`---- later version. ----`
30			`---- ----`
31			`---- This source is distributed in the hope that it will be ----`
32			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
33			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
34			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
35			`---- details. ----`
36			`---- ----`
37			`---- You should have received a copy of the GNU Lesser General ----`
38			`---- Public License along with this source; if not, download it ----`
39			`---- from http://www.opencores.org/lgpl.shtml ----`
40			`---- ----`
41			`--------------------------------------------------------------------------------`
42			`-- Object : Entity work.esoc`
43			`-- Last modified : Mon Apr 14 12:48:20 2014.`
44			`--------------------------------------------------------------------------------`
45
46
47
48			`library ieee, std, work;`
49			`use ieee.std_logic_1164.all;`
50			`use std.textio.all;`
51			`use ieee.numeric_std.all;`
52			`use work.package_esoc_configuration.all;`
53
54			`entity esoc is`
55			`port(`
56			`esoc_address : in std_logic_vector(15 downto 0);`
57			`esoc_areset : in std_logic;`
58			`esoc_boot_complete : out std_logic;`
59			`esoc_clk : in std_logic;`
60			`esoc_cs : in std_logic;`
61			`esoc_data : inout std_logic_vector(31 downto 0);`
62			`esoc_mdc : out std_logic_vector(esoc_port_count-1 downto 0);`
63			`esoc_mdio : inout std_logic_vector(esoc_port_count-1 downto 0);`
64			`esoc_rd : in std_logic;`
65			`esoc_rgmii_rxc : in std_logic_vector(esoc_port_count-1 downto 0);`
66			`esoc_rgmii_rxctl : in std_logic_vector(esoc_port_count-1 downto 0);`
67			`esoc_rgmii_rxd : in std_logic_vector(3+4*(esoc_port_count-1) downto 0);`
68			`esoc_rgmii_txc : out std_logic_vector(esoc_port_count-1 downto 0);`
69			`esoc_rgmii_txctl : out std_logic_vector(esoc_port_count-1 downto 0);`
70			`esoc_rgmii_txd : out std_logic_vector(3+4*(esoc_port_count-1) downto 0);`
71			`esoc_wait : out std_logic;`
72			`esoc_wr : in std_logic);`
73			`end entity esoc;`
74
75			`--------------------------------------------------------------------------------`
76			`-- Object : Architecture work.esoc.structure`
77			`-- Last modified : Mon Apr 14 12:48:20 2014.`
78			`--------------------------------------------------------------------------------`
79
80			`architecture structure of esoc is`
81
82			`signal clk_control : std_logic;`
83			`signal reset : std_logic;`
84			`signal clk_search : STD_LOGIC;`
85			`signal clk_data : STD_LOGIC;`
86			`signal data_req : std_logic_vector(esoc_port_count-1 downto 0);`
87			`signal data_gnt_wr : std_logic_vector(esoc_port_count-1 downto 0);`
88			`signal data_sof : std_logic;`
89			`signal data_eof : std_logic;`
90			`signal data : std_logic_vector(63 downto 0);`
91			`signal clk_rgmii_125m : STD_LOGIC;`
92			`signal clk_rgmii_25m : STD_LOGIC;`
93			`signal clk_rgmii_2m5 : STD_LOGIC;`
94			`signal data_gnt_rd : std_logic_vector(esoc_port_count-1 downto 0);`
95			`signal ctrl_wait : std_logic;`
96			`signal ctrl_rddata : std_logic_vector(31 downto 0);`
97			`signal ctrl_rd : std_logic;`
98			`signal ctrl_wrdata : std_logic_vector(31 downto 0);`
99			`signal ctrl_wr : std_logic;`
100			`signal ctrl_address : std_logic_vector(15 downto 0);`
101			`signal search_req : std_logic_vector(esoc_port_count-1 downto 0);`
102			`signal search_sof : std_logic;`
103			`signal search_key : std_logic_vector(63 downto 0);`
104			`signal search_gnt_wr : std_logic_vector(esoc_port_count-1 downto 0);`
105			`signal search_eof : std_logic;`
106			`signal search_result_av : std_logic;`
107			`signal search_result : std_logic_vector(esoc_port_count-1 downto 0);`
108			`signal data_port_sel : std_logic_vector(esoc_port_count-1 downto 0);`
109			`signal search_port_stalled : std_logic_vector(esoc_port_count-1 downto 0);`
110			`signal pll1_locked : STD_LOGIC;`
111			`signal pll2_locked : STD_LOGIC;`
112			`signal ctrl_brom_rd : std_logic;`
113			`signal ctrl_brom_address : std_logic_vector(10 downto 0);`
114			`signal q : STD_LOGIC_VECTOR(31 downto 0);`
115
116			`component esoc_port`
117			`generic(`
118			`esoc_port_nr : integer := 0);`
119			`port(`
120			`clk_control : in std_logic;`
121			`clk_data : in std_logic;`
122			`clk_rgmii_125m : in STD_LOGIC;`
123			`clk_rgmii_25m : in STD_LOGIC;`
124			`clk_rgmii_2m5 : in STD_LOGIC;`
125			`clk_search : in std_logic;`
126			`ctrl_address : in std_logic_vector(15 downto 0);`
127			`ctrl_rd : in std_logic;`
128			`ctrl_rddata : out std_logic_vector(31 downto 0);`
129			`ctrl_wait : out std_logic;`
130			`ctrl_wr : in std_logic;`
131			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
132			`data : inout std_logic_vector(63 downto 0);`
133			`data_eof : inout std_logic;`
134			`data_gnt_rd : in std_logic;`
135			`data_gnt_wr : in std_logic;`
136			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
137			`data_req : out std_logic;`
138			`data_sof : inout std_logic;`
139			`mdc : out std_logic;`
140			`mdio : inout std_logic;`
141			`reset : in std_logic;`
142			`rgmii_rxc : in std_logic;`
143			`rgmii_rxctl : in std_logic;`
144			`rgmii_rxd : in std_logic_vector(3 downto 0);`
145			`rgmii_txc : out std_logic;`
146			`rgmii_txctl : out std_logic;`
147			`rgmii_txd : out std_logic_vector(3 downto 0);`
148			`search_eof : out std_logic;`
149			`search_gnt_wr : in std_logic;`
150			`search_key : out std_logic_vector(63 downto 0);`
151			`search_port_stalled : out std_logic;`
152			`search_req : out std_logic;`
153			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
154			`search_result_av : in std_logic;`
155			`search_sof : out std_logic);`
156			`end component esoc_port;`
157
158			`component esoc_control`
159			`port(`
160			`brom_address : out std_logic_vector(10 downto 0);`
161			`brom_rd : out std_logic;`
162			`brom_rddata : in std_logic_vector(31 downto 0);`
163			`clk_control : in std_logic;`
164			`ctrl_address : out std_logic_vector(15 downto 0);`
165			`ctrl_rd : out std_logic;`
166			`ctrl_rddata : in std_logic_vector(31 downto 0);`
167			`ctrl_wait : in std_logic;`
168			`ctrl_wr : out std_logic;`
169			`ctrl_wrdata : out std_logic_vector(31 downto 0);`
170			`esoc_address : in std_logic_vector(15 downto 0);`
171			`esoc_boot_complete : out std_logic;`
172			`esoc_cs : in std_logic;`
173			`esoc_data : inout std_logic_vector(31 downto 0);`
174			`esoc_rd : in std_logic;`
175			`esoc_wait : out std_logic;`
176			`esoc_wr : in std_logic;`
177			`pll1_locked : in STD_LOGIC;`
178			`pll2_locked : in STD_LOGIC;`
179			`reset : in std_logic);`
180			`end component esoc_control;`
181
182			`component esoc_reset`
183			`port(`
184			`clk_control : in std_logic;`
185			`esoc_areset : in std_logic;`
186			`pll1_locked : in STD_LOGIC;`
187			`pll2_locked : in STD_LOGIC;`
188			`reset : out std_logic);`
189			`end component esoc_reset;`
190
191			`component esoc_bus_arbiter`
192			`generic(`
193			`id : integer := 0);`
194			`port(`
195			`bus_eof : in std_logic;`
196			`bus_gnt_rd : out std_logic_vector(esoc_port_count-1 downto 0);`
197			`bus_gnt_wr : out std_logic_vector(esoc_port_count-1 downto 0);`
198			`bus_req : in std_logic_vector(esoc_port_count-1 downto 0);`
199			`bus_sof : in std_logic;`
200			`clk_bus : in std_logic;`
201			`clk_control : in std_logic;`
202			`ctrl_address : in std_logic_vector(15 downto 0);`
203			`ctrl_rd : in std_logic;`
204			`ctrl_rddata : out std_logic_vector(31 downto 0);`
205			`ctrl_wait : out std_logic;`
206			`ctrl_wr : in std_logic;`
207			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
208			`reset : in std_logic);`
209			`end component esoc_bus_arbiter;`
210
211			`component esoc_search_engine`
212			`port(`
213			`clk_control : in std_logic;`
214			`clk_search : in std_logic;`
215			`ctrl_address : in std_logic_vector(15 downto 0);`
216			`ctrl_rd : in std_logic;`
217			`ctrl_rddata : out std_logic_vector(31 downto 0);`
218			`ctrl_wait : out std_logic;`
219			`ctrl_wr : in std_logic;`
220			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
221			`reset : in std_logic;`
222			`search_eof : in std_logic;`
223			`search_key : in std_logic_vector(63 downto 0);`
224			`search_port_stalled : in std_logic_vector(esoc_port_count-1 downto 0);`
225			`search_result : out std_logic_vector(esoc_port_count-1 downto 0);`
226			`search_result_av : out std_logic;`
227			`search_sof : in std_logic);`
228			`end component esoc_search_engine;`
229
230			`component esoc_pll1_c3`
231			`port(`
232			`inclk0 : in STD_LOGIC := '0';`
233			`c0 : out STD_LOGIC;`
234			`c1 : out STD_LOGIC;`
235			`c2 : out STD_LOGIC;`
236			`locked : out STD_LOGIC);`
237			`end component esoc_pll1_c3;`
238
239			`component esoc_pll2_c3`
240			`port(`
241			`inclk0 : in STD_LOGIC := '0';`
242			`c0 : out STD_LOGIC;`
243			`locked : out STD_LOGIC;`
244			`c1 : out STD_LOGIC;`
245			`c2 : out STD_LOGIC);`
246			`end component esoc_pll2_c3;`
247
248			`component esoc_rom_2kx32`
249			`port(`
250			`aclr : in STD_LOGIC;`
251			`address : in STD_LOGIC_VECTOR(10 downto 0);`
252			`clock : in STD_LOGIC;`
253			`data : in STD_LOGIC_VECTOR(31 downto 0);`
254			`rden : in STD_LOGIC;`
255			`wren : in STD_LOGIC;`
256			`q : out STD_LOGIC_VECTOR(31 downto 0));`
257			`end component esoc_rom_2kx32;`
258
259			`begin`
260			`--CLK IN:`
261			`--50MHz`
262			`--CLK OUT:`
263			`--C0 50MHz`
264			`--C1 100MHz`
265			`--C2 150MHz`
266			`--CLK IN:`
267			`--50MHz`
268			`--CLK OUT:`
269			`--C0 125MHz`
270			`--`
271			`--eSoc Clocks and Reset`
272			`--eSoc Host Control Interface`
273			`--eSoc Ethernet ports`
274			`--eSoc Search Engine`
275			`--eSoc Data bus Arbiter`
276			`--eSoc Search bus Arbiter`
277			`--eSoc Boot ROM`
278			`esoc_ports: for esoc_port_nr in esoc_port_count-1 downto 0 generate`
279			`begin`
280			`u0: esoc_port`
281			`generic map(`
282			`esoc_port_nr => esoc_port_nr)`
283			`port map(`
284			`clk_control => clk_control,`
285			`clk_data => clk_data,`
286			`clk_rgmii_125m => clk_rgmii_125m,`
287			`clk_rgmii_25m => clk_rgmii_25m,`
288			`clk_rgmii_2m5 => clk_rgmii_2m5,`
289			`clk_search => clk_search,`
290			`ctrl_address => ctrl_address,`
291			`ctrl_rd => ctrl_rd,`
292			`ctrl_rddata => ctrl_rddata,`
293			`ctrl_wait => ctrl_wait,`
294			`ctrl_wr => ctrl_wr,`
295			`ctrl_wrdata => ctrl_wrdata,`
296			`data => data,`
297			`data_eof => data_eof,`
298			`data_gnt_rd => data_gnt_rd(esoc_port_nr),`
299			`data_gnt_wr => data_gnt_wr(esoc_port_nr),`
300			`data_port_sel => data_port_sel,`
301			`data_req => data_req(esoc_port_nr),`
302			`data_sof => data_sof,`
303			`mdc => esoc_mdc(esoc_port_nr),`
304			`mdio => esoc_mdio(esoc_port_nr),`
305			`reset => reset,`
306			`rgmii_rxc => esoc_rgmii_rxc(esoc_port_nr),`
307			`rgmii_rxctl => esoc_rgmii_rxctl(esoc_port_nr),`
308			`rgmii_rxd => esoc_rgmii_rxd(3+4esoc_port_nr downto 4esoc_port_nr),`
309			`rgmii_txc => esoc_rgmii_txc(esoc_port_nr),`
310			`rgmii_txctl => esoc_rgmii_txctl(esoc_port_nr),`
311			`rgmii_txd => esoc_rgmii_txd(3+4esoc_port_nr downto 4esoc_port_nr),`
312			`search_eof => search_eof,`
313			`search_gnt_wr => search_gnt_wr(esoc_port_nr),`
314			`search_key => search_key,`
315			`search_port_stalled => search_port_stalled(esoc_port_nr),`
316			`search_req => search_req(esoc_port_nr),`
317			`search_result => search_result,`
318			`search_result_av => search_result_av,`
319			`search_sof => search_sof);`
320
321			`end generate esoc_ports;`
322
323			`-- TEST`
324			`u0: esoc_control`
325			`port map(`
326			`brom_address => ctrl_brom_address,`
327			`brom_rd => ctrl_brom_rd,`
328			`brom_rddata => q,`
329			`clk_control => clk_control,`
330			`ctrl_address => ctrl_address,`
331			`ctrl_rd => ctrl_rd,`
332			`ctrl_rddata => ctrl_rddata,`
333			`ctrl_wait => ctrl_wait,`
334			`ctrl_wr => ctrl_wr,`
335			`ctrl_wrdata => ctrl_wrdata,`
336			`esoc_address => esoc_address,`
337			`esoc_boot_complete => esoc_boot_complete,`
338			`esoc_cs => esoc_cs,`
339			`esoc_data => esoc_data,`
340			`esoc_rd => esoc_rd,`
341			`esoc_wait => esoc_wait,`
342			`esoc_wr => esoc_wr,`
343			`pll1_locked => pll1_locked,`
344			`pll2_locked => pll2_locked,`
345			`reset => reset);`
346
347			`u2: esoc_reset`
348			`port map(`
349			`clk_control => clk_control,`
350			`esoc_areset => esoc_areset,`
351			`pll1_locked => pll1_locked,`
352			`pll2_locked => pll2_locked,`
353			`reset => reset);`
354
355			`u4: esoc_bus_arbiter`
356			`generic map(`
357			`id => 0)`
358			`port map(`
359			`bus_eof => data_eof,`
360			`bus_gnt_rd => data_gnt_rd,`
361			`bus_gnt_wr => data_gnt_wr,`
362			`bus_req => data_req,`
363			`bus_sof => data_sof,`
364			`clk_bus => clk_data,`
365			`clk_control => clk_control,`
366			`ctrl_address => ctrl_address,`
367			`ctrl_rd => ctrl_rd,`
368			`ctrl_rddata => ctrl_rddata,`
369			`ctrl_wait => ctrl_wait,`
370			`ctrl_wr => ctrl_wr,`
371			`ctrl_wrdata => ctrl_wrdata,`
372			`reset => reset);`
373
374			`u6: esoc_search_engine`
375			`port map(`
376			`clk_control => clk_control,`
377			`clk_search => clk_search,`
378			`ctrl_address => ctrl_address,`
379			`ctrl_rd => ctrl_rd,`
380			`ctrl_rddata => ctrl_rddata,`
381			`ctrl_wait => ctrl_wait,`
382			`ctrl_wr => ctrl_wr,`
383			`ctrl_wrdata => ctrl_wrdata,`
384			`reset => reset,`
385			`search_eof => search_eof,`
386			`search_key => search_key,`
387			`search_port_stalled => search_port_stalled,`
388			`search_result => search_result,`
389			`search_result_av => search_result_av,`
390			`search_sof => search_sof);`
391
392			`u1: esoc_pll1_c3`
393			`port map(`
394			`inclk0 => esoc_clk,`
395			`c0 => clk_control,`
396			`c1 => clk_search,`
397			`c2 => clk_data,`
398			`locked => pll1_locked);`
399
400			`u3: esoc_pll2_c3`
401			`port map(`
402			`inclk0 => esoc_clk,`
403			`c0 => clk_rgmii_125m,`
404			`locked => pll2_locked,`
405			`c1 => clk_rgmii_25m,`
406			`c2 => clk_rgmii_2m5);`
407
408			`u5: esoc_bus_arbiter`
409			`generic map(`
410			`id => 1)`
411			`port map(`
412			`bus_eof => search_eof,`
413			`bus_gnt_rd => open,`
414			`bus_gnt_wr => search_gnt_wr,`
415			`bus_req => search_req,`
416			`bus_sof => search_sof,`
417			`clk_bus => clk_search,`
418			`clk_control => clk_control,`
419			`ctrl_address => ctrl_address,`
420			`ctrl_rd => ctrl_rd,`
421			`ctrl_rddata => ctrl_rddata,`
422			`ctrl_wait => ctrl_wait,`
423			`ctrl_wr => ctrl_wr,`
424			`ctrl_wrdata => ctrl_wrdata,`
425			`reset => reset);`
426
427			`u7: esoc_rom_2kx32`
428			`port map(`
429			`aclr => reset,`
430			`address => ctrl_brom_address,`
431			`clock => clk_control,`
432			`data => (others => '0'),`
433			`rden => ctrl_brom_rd,`
434			`wren => '0',`
435			`q => q);`
436
437			`end architecture structure ; -- of esoc`
438