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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc.vhd] - Blame information for rev 53

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--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : S212065
-- User name     : df768
-- Time stamp    : Tue Aug 19 08:05:18 2014
--
-- Designed by   : L.Maarsen
-- Company       : LogiXA
-- Project info  : eSoC
--
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc
-- Last modified : Mon Apr 14 12:48:20 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc is
  port(
    esoc_address       : in     std_logic_vector(15 downto 0);
    esoc_areset        : in     std_logic;
    esoc_boot_complete : out    std_logic;
    esoc_clk           : in     std_logic;
    esoc_cs            : in     std_logic;
    esoc_data          : inout  std_logic_vector(31 downto 0);
    esoc_mdc           : out    std_logic_vector(esoc_port_count-1 downto 0);
    esoc_mdio          : inout  std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rd            : in     std_logic;
    esoc_rgmii_rxc     : in     std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_rxctl   : in     std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_rxd     : in     std_logic_vector(3+4*(esoc_port_count-1) downto 0);
    esoc_rgmii_txc     : out    std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_txctl   : out    std_logic_vector(esoc_port_count-1 downto 0);
    esoc_rgmii_txd     : out    std_logic_vector(3+4*(esoc_port_count-1) downto 0);
    esoc_wait          : out    std_logic;
    esoc_wr            : in     std_logic);
end entity esoc;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc.structure
-- Last modified : Mon Apr 14 12:48:20 2014.
--------------------------------------------------------------------------------
 
architecture structure of esoc is
 
  signal clk_control         : std_logic;
  signal reset               : std_logic;
  signal clk_search          : STD_LOGIC;
  signal clk_data            : STD_LOGIC;
  signal data_req            : std_logic_vector(esoc_port_count-1 downto 0);
  signal data_gnt_wr         : std_logic_vector(esoc_port_count-1 downto 0);
  signal data_sof            : std_logic;
  signal data_eof            : std_logic;
  signal data                : std_logic_vector(63 downto 0);
  signal clk_rgmii_125m      : STD_LOGIC;
  signal clk_rgmii_25m       : STD_LOGIC;
  signal clk_rgmii_2m5       : STD_LOGIC;
  signal data_gnt_rd         : std_logic_vector(esoc_port_count-1 downto 0);
  signal ctrl_wait           : std_logic;
  signal ctrl_rddata         : std_logic_vector(31 downto 0);
  signal ctrl_rd             : std_logic;
  signal ctrl_wrdata         : std_logic_vector(31 downto 0);
  signal ctrl_wr             : std_logic;
  signal ctrl_address        : std_logic_vector(15 downto 0);
  signal search_req          : std_logic_vector(esoc_port_count-1 downto 0);
  signal search_sof          : std_logic;
  signal search_key          : std_logic_vector(63 downto 0);
  signal search_gnt_wr       : std_logic_vector(esoc_port_count-1 downto 0);
  signal search_eof          : std_logic;
  signal search_result_av    : std_logic;
  signal search_result       : std_logic_vector(esoc_port_count-1 downto 0);
  signal data_port_sel       : std_logic_vector(esoc_port_count-1 downto 0);
  signal search_port_stalled : std_logic_vector(esoc_port_count-1 downto 0);
  signal pll1_locked         : STD_LOGIC;
  signal pll2_locked         : STD_LOGIC;
  signal ctrl_brom_rd        : std_logic;
  signal ctrl_brom_address   : std_logic_vector(10 downto 0);
  signal q                   : STD_LOGIC_VECTOR(31 downto 0);
 
  component esoc_port
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control         : in     std_logic;
      clk_data            : in     std_logic;
      clk_rgmii_125m      : in     STD_LOGIC;
      clk_rgmii_25m       : in     STD_LOGIC;
      clk_rgmii_2m5       : in     STD_LOGIC;
      clk_search          : in     std_logic;
      ctrl_address        : in     std_logic_vector(15 downto 0);
      ctrl_rd             : in     std_logic;
      ctrl_rddata         : out    std_logic_vector(31 downto 0);
      ctrl_wait           : out    std_logic;
      ctrl_wr             : in     std_logic;
      ctrl_wrdata         : in     std_logic_vector(31 downto 0);
      data                : inout  std_logic_vector(63 downto 0);
      data_eof            : inout  std_logic;
      data_gnt_rd         : in     std_logic;
      data_gnt_wr         : in     std_logic;
      data_port_sel       : inout  std_logic_vector(esoc_port_count-1 downto 0);
      data_req            : out    std_logic;
      data_sof            : inout  std_logic;
      mdc                 : out    std_logic;
      mdio                : inout  std_logic;
      reset               : in     std_logic;
      rgmii_rxc           : in     std_logic;
      rgmii_rxctl         : in     std_logic;
      rgmii_rxd           : in     std_logic_vector(3 downto 0);
      rgmii_txc           : out    std_logic;
      rgmii_txctl         : out    std_logic;
      rgmii_txd           : out    std_logic_vector(3 downto 0);
      search_eof          : out    std_logic;
      search_gnt_wr       : in     std_logic;
      search_key          : out    std_logic_vector(63 downto 0);
      search_port_stalled : out    std_logic;
      search_req          : out    std_logic;
      search_result       : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av    : in     std_logic;
      search_sof          : out    std_logic);
  end component esoc_port;
 
  component esoc_control
    port(
      brom_address       : out    std_logic_vector(10 downto 0);
      brom_rd            : out    std_logic;
      brom_rddata        : in     std_logic_vector(31 downto 0);
      clk_control        : in     std_logic;
      ctrl_address       : out    std_logic_vector(15 downto 0);
      ctrl_rd            : out    std_logic;
      ctrl_rddata        : in     std_logic_vector(31 downto 0);
      ctrl_wait          : in     std_logic;
      ctrl_wr            : out    std_logic;
      ctrl_wrdata        : out    std_logic_vector(31 downto 0);
      esoc_address       : in     std_logic_vector(15 downto 0);
      esoc_boot_complete : out    std_logic;
      esoc_cs            : in     std_logic;
      esoc_data          : inout  std_logic_vector(31 downto 0);
      esoc_rd            : in     std_logic;
      esoc_wait          : out    std_logic;
      esoc_wr            : in     std_logic;
      pll1_locked        : in     STD_LOGIC;
      pll2_locked        : in     STD_LOGIC;
      reset              : in     std_logic);
  end component esoc_control;
 
  component esoc_reset
    port(
      clk_control : in     std_logic;
      esoc_areset : in     std_logic;
      pll1_locked : in     STD_LOGIC;
      pll2_locked : in     STD_LOGIC;
      reset       : out    std_logic);
  end component esoc_reset;
 
  component esoc_bus_arbiter
    generic(
      id : integer := 0);
    port(
      bus_eof      : in     std_logic;
      bus_gnt_rd   : out    std_logic_vector(esoc_port_count-1 downto 0);
      bus_gnt_wr   : out    std_logic_vector(esoc_port_count-1 downto 0);
      bus_req      : in     std_logic_vector(esoc_port_count-1 downto 0);
      bus_sof      : in     std_logic;
      clk_bus      : in     std_logic;
      clk_control  : in     std_logic;
      ctrl_address : in     std_logic_vector(15 downto 0);
      ctrl_rd      : in     std_logic;
      ctrl_rddata  : out    std_logic_vector(31 downto 0);
      ctrl_wait    : out    std_logic;
      ctrl_wr      : in     std_logic;
      ctrl_wrdata  : in     std_logic_vector(31 downto 0);
      reset        : in     std_logic);
  end component esoc_bus_arbiter;
 
  component esoc_search_engine
    port(
      clk_control         : in     std_logic;
      clk_search          : in     std_logic;
      ctrl_address        : in     std_logic_vector(15 downto 0);
      ctrl_rd             : in     std_logic;
      ctrl_rddata         : out    std_logic_vector(31 downto 0);
      ctrl_wait           : out    std_logic;
      ctrl_wr             : in     std_logic;
      ctrl_wrdata         : in     std_logic_vector(31 downto 0);
      reset               : in     std_logic;
      search_eof          : in     std_logic;
      search_key          : in     std_logic_vector(63 downto 0);
      search_port_stalled : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result       : out    std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av    : out    std_logic;
      search_sof          : in     std_logic);
  end component esoc_search_engine;
 
  component esoc_pll1_c3
    port(
      inclk0 : in     STD_LOGIC := '0';
      c0     : out    STD_LOGIC;
      c1     : out    STD_LOGIC;
      c2     : out    STD_LOGIC;
      locked : out    STD_LOGIC);
  end component esoc_pll1_c3;
 
  component esoc_pll2_c3
    port(
      inclk0 : in     STD_LOGIC := '0';
      c0     : out    STD_LOGIC;
      locked : out    STD_LOGIC;
      c1     : out    STD_LOGIC;
      c2     : out    STD_LOGIC);
  end component esoc_pll2_c3;
 
  component esoc_rom_2kx32
    port(
      aclr    : in     STD_LOGIC;
      address : in     STD_LOGIC_VECTOR(10 downto 0);
      clock   : in     STD_LOGIC;
      data    : in     STD_LOGIC_VECTOR(31 downto 0);
      rden    : in     STD_LOGIC;
      wren    : in     STD_LOGIC;
      q       : out    STD_LOGIC_VECTOR(31 downto 0));
  end component esoc_rom_2kx32;
 
begin
  --CLK IN: 
  --50MHz
  --CLK OUT:    
  --C0 50MHz
  --C1 100MHz
  --C2 150MHz
  --CLK IN: 
  --50MHz
  --CLK OUT:    
  --C0 125MHz
  --
  --eSoc Clocks and Reset
  --eSoc Host Control Interface
  --eSoc Ethernet ports
  --eSoc Search Engine
  --eSoc Data bus Arbiter
  --eSoc Search bus Arbiter
  --eSoc Boot ROM
  esoc_ports: for esoc_port_nr in esoc_port_count-1 downto 0 generate
  begin
    u0: esoc_port
      generic map(
        esoc_port_nr => esoc_port_nr)
      port map(
        clk_control         => clk_control,
        clk_data            => clk_data,
        clk_rgmii_125m      => clk_rgmii_125m,
        clk_rgmii_25m       => clk_rgmii_25m,
        clk_rgmii_2m5       => clk_rgmii_2m5,
        clk_search          => clk_search,
        ctrl_address        => ctrl_address,
        ctrl_rd             => ctrl_rd,
        ctrl_rddata         => ctrl_rddata,
        ctrl_wait           => ctrl_wait,
        ctrl_wr             => ctrl_wr,
        ctrl_wrdata         => ctrl_wrdata,
        data                => data,
        data_eof            => data_eof,
        data_gnt_rd         => data_gnt_rd(esoc_port_nr),
        data_gnt_wr         => data_gnt_wr(esoc_port_nr),
        data_port_sel       => data_port_sel,
        data_req            => data_req(esoc_port_nr),
        data_sof            => data_sof,
        mdc                 => esoc_mdc(esoc_port_nr),
        mdio                => esoc_mdio(esoc_port_nr),
        reset               => reset,
        rgmii_rxc           => esoc_rgmii_rxc(esoc_port_nr),
        rgmii_rxctl         => esoc_rgmii_rxctl(esoc_port_nr),
        rgmii_rxd           => esoc_rgmii_rxd(3+4*esoc_port_nr downto 4*esoc_port_nr),
        rgmii_txc           => esoc_rgmii_txc(esoc_port_nr),
        rgmii_txctl         => esoc_rgmii_txctl(esoc_port_nr),
        rgmii_txd           => esoc_rgmii_txd(3+4*esoc_port_nr downto 4*esoc_port_nr),
        search_eof          => search_eof,
        search_gnt_wr       => search_gnt_wr(esoc_port_nr),
        search_key          => search_key,
        search_port_stalled => search_port_stalled(esoc_port_nr),
        search_req          => search_req(esoc_port_nr),
        search_result       => search_result,
        search_result_av    => search_result_av,
        search_sof          => search_sof);
 
  end generate esoc_ports;
 
  -- TEST
  u0: esoc_control
    port map(
      brom_address       => ctrl_brom_address,
      brom_rd            => ctrl_brom_rd,
      brom_rddata        => q,
      clk_control        => clk_control,
      ctrl_address       => ctrl_address,
      ctrl_rd            => ctrl_rd,
      ctrl_rddata        => ctrl_rddata,
      ctrl_wait          => ctrl_wait,
      ctrl_wr            => ctrl_wr,
      ctrl_wrdata        => ctrl_wrdata,
      esoc_address       => esoc_address,
      esoc_boot_complete => esoc_boot_complete,
      esoc_cs            => esoc_cs,
      esoc_data          => esoc_data,
      esoc_rd            => esoc_rd,
      esoc_wait          => esoc_wait,
      esoc_wr            => esoc_wr,
      pll1_locked        => pll1_locked,
      pll2_locked        => pll2_locked,
      reset              => reset);
 
  u2: esoc_reset
    port map(
      clk_control => clk_control,
      esoc_areset => esoc_areset,
      pll1_locked => pll1_locked,
      pll2_locked => pll2_locked,
      reset       => reset);
 
  u4: esoc_bus_arbiter
    generic map(
      id => 0)
    port map(
      bus_eof      => data_eof,
      bus_gnt_rd   => data_gnt_rd,
      bus_gnt_wr   => data_gnt_wr,
      bus_req      => data_req,
      bus_sof      => data_sof,
      clk_bus      => clk_data,
      clk_control  => clk_control,
      ctrl_address => ctrl_address,
      ctrl_rd      => ctrl_rd,
      ctrl_rddata  => ctrl_rddata,
      ctrl_wait    => ctrl_wait,
      ctrl_wr      => ctrl_wr,
      ctrl_wrdata  => ctrl_wrdata,
      reset        => reset);
 
  u6: esoc_search_engine
    port map(
      clk_control         => clk_control,
      clk_search          => clk_search,
      ctrl_address        => ctrl_address,
      ctrl_rd             => ctrl_rd,
      ctrl_rddata         => ctrl_rddata,
      ctrl_wait           => ctrl_wait,
      ctrl_wr             => ctrl_wr,
      ctrl_wrdata         => ctrl_wrdata,
      reset               => reset,
      search_eof          => search_eof,
      search_key          => search_key,
      search_port_stalled => search_port_stalled,
      search_result       => search_result,
      search_result_av    => search_result_av,
      search_sof          => search_sof);
 
  u1: esoc_pll1_c3
    port map(
      inclk0 => esoc_clk,
      c0     => clk_control,
      c1     => clk_search,
      c2     => clk_data,
      locked => pll1_locked);
 
  u3: esoc_pll2_c3
    port map(
      inclk0 => esoc_clk,
      c0     => clk_rgmii_125m,
      locked => pll2_locked,
      c1     => clk_rgmii_25m,
      c2     => clk_rgmii_2m5);
 
  u5: esoc_bus_arbiter
    generic map(
      id => 1)
    port map(
      bus_eof      => search_eof,
      bus_gnt_rd   => open,
      bus_gnt_wr   => search_gnt_wr,
      bus_req      => search_req,
      bus_sof      => search_sof,
      clk_bus      => clk_search,
      clk_control  => clk_control,
      ctrl_address => ctrl_address,
      ctrl_rd      => ctrl_rd,
      ctrl_rddata  => ctrl_rddata,
      ctrl_wait    => ctrl_wait,
      ctrl_wr      => ctrl_wr,
      ctrl_wrdata  => ctrl_wrdata,
      reset        => reset);
 
  u7: esoc_rom_2kx32
    port map(
      aclr    => reset,
      address => ctrl_brom_address,
      clock   => clk_control,
      data    => (others => '0'),
      rden    => ctrl_brom_rd,
      wren    => '0',
      q       => q);
 
end architecture structure ; -- of esoc
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc.vhd] - Blame information for rev 53

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2	53	lmaarsen	`--`
3			`-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.`
4			`--`
5			`-- Ease library : work`
6			`-- HDL library : work`
7			`-- Host name : S212065`
8			`-- User name : df768`
9			`-- Time stamp : Tue Aug 19 08:05:18 2014`
10			`--`
11			`-- Designed by : L.Maarsen`
12			`-- Company : LogiXA`
13			`-- Project info : eSoC`
14			`--`
15	42	lmaarsen	`--------------------------------------------------------------------------------`
16	53	lmaarsen
17	42	lmaarsen	`--------------------------------------------------------------------------------`
18			`-- Object : Entity work.esoc`
19			`-- Last modified : Mon Apr 14 12:48:20 2014.`
20			`--------------------------------------------------------------------------------`
21
22
23
24			`library ieee, std, work;`
25			`use ieee.std_logic_1164.all;`
26			`use std.textio.all;`
27			`use ieee.numeric_std.all;`
28			`use work.package_esoc_configuration.all;`
29
30			`entity esoc is`
31			`port(`
32			`esoc_address : in std_logic_vector(15 downto 0);`
33			`esoc_areset : in std_logic;`
34			`esoc_boot_complete : out std_logic;`
35			`esoc_clk : in std_logic;`
36			`esoc_cs : in std_logic;`
37			`esoc_data : inout std_logic_vector(31 downto 0);`
38			`esoc_mdc : out std_logic_vector(esoc_port_count-1 downto 0);`
39			`esoc_mdio : inout std_logic_vector(esoc_port_count-1 downto 0);`
40			`esoc_rd : in std_logic;`
41			`esoc_rgmii_rxc : in std_logic_vector(esoc_port_count-1 downto 0);`
42			`esoc_rgmii_rxctl : in std_logic_vector(esoc_port_count-1 downto 0);`
43			`esoc_rgmii_rxd : in std_logic_vector(3+4*(esoc_port_count-1) downto 0);`
44			`esoc_rgmii_txc : out std_logic_vector(esoc_port_count-1 downto 0);`
45			`esoc_rgmii_txctl : out std_logic_vector(esoc_port_count-1 downto 0);`
46			`esoc_rgmii_txd : out std_logic_vector(3+4*(esoc_port_count-1) downto 0);`
47			`esoc_wait : out std_logic;`
48			`esoc_wr : in std_logic);`
49			`end entity esoc;`
50
51			`--------------------------------------------------------------------------------`
52			`-- Object : Architecture work.esoc.structure`
53			`-- Last modified : Mon Apr 14 12:48:20 2014.`
54			`--------------------------------------------------------------------------------`
55
56			`architecture structure of esoc is`
57
58			`signal clk_control : std_logic;`
59			`signal reset : std_logic;`
60			`signal clk_search : STD_LOGIC;`
61			`signal clk_data : STD_LOGIC;`
62			`signal data_req : std_logic_vector(esoc_port_count-1 downto 0);`
63			`signal data_gnt_wr : std_logic_vector(esoc_port_count-1 downto 0);`
64			`signal data_sof : std_logic;`
65			`signal data_eof : std_logic;`
66			`signal data : std_logic_vector(63 downto 0);`
67			`signal clk_rgmii_125m : STD_LOGIC;`
68			`signal clk_rgmii_25m : STD_LOGIC;`
69			`signal clk_rgmii_2m5 : STD_LOGIC;`
70			`signal data_gnt_rd : std_logic_vector(esoc_port_count-1 downto 0);`
71			`signal ctrl_wait : std_logic;`
72			`signal ctrl_rddata : std_logic_vector(31 downto 0);`
73			`signal ctrl_rd : std_logic;`
74			`signal ctrl_wrdata : std_logic_vector(31 downto 0);`
75			`signal ctrl_wr : std_logic;`
76			`signal ctrl_address : std_logic_vector(15 downto 0);`
77			`signal search_req : std_logic_vector(esoc_port_count-1 downto 0);`
78			`signal search_sof : std_logic;`
79			`signal search_key : std_logic_vector(63 downto 0);`
80			`signal search_gnt_wr : std_logic_vector(esoc_port_count-1 downto 0);`
81			`signal search_eof : std_logic;`
82			`signal search_result_av : std_logic;`
83			`signal search_result : std_logic_vector(esoc_port_count-1 downto 0);`
84			`signal data_port_sel : std_logic_vector(esoc_port_count-1 downto 0);`
85			`signal search_port_stalled : std_logic_vector(esoc_port_count-1 downto 0);`
86			`signal pll1_locked : STD_LOGIC;`
87			`signal pll2_locked : STD_LOGIC;`
88			`signal ctrl_brom_rd : std_logic;`
89			`signal ctrl_brom_address : std_logic_vector(10 downto 0);`
90			`signal q : STD_LOGIC_VECTOR(31 downto 0);`
91
92			`component esoc_port`
93			`generic(`
94			`esoc_port_nr : integer := 0);`
95			`port(`
96			`clk_control : in std_logic;`
97			`clk_data : in std_logic;`
98			`clk_rgmii_125m : in STD_LOGIC;`
99			`clk_rgmii_25m : in STD_LOGIC;`
100			`clk_rgmii_2m5 : in STD_LOGIC;`
101			`clk_search : in std_logic;`
102			`ctrl_address : in std_logic_vector(15 downto 0);`
103			`ctrl_rd : in std_logic;`
104			`ctrl_rddata : out std_logic_vector(31 downto 0);`
105			`ctrl_wait : out std_logic;`
106			`ctrl_wr : in std_logic;`
107			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
108			`data : inout std_logic_vector(63 downto 0);`
109			`data_eof : inout std_logic;`
110			`data_gnt_rd : in std_logic;`
111			`data_gnt_wr : in std_logic;`
112			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
113			`data_req : out std_logic;`
114			`data_sof : inout std_logic;`
115			`mdc : out std_logic;`
116			`mdio : inout std_logic;`
117			`reset : in std_logic;`
118			`rgmii_rxc : in std_logic;`
119			`rgmii_rxctl : in std_logic;`
120			`rgmii_rxd : in std_logic_vector(3 downto 0);`
121			`rgmii_txc : out std_logic;`
122			`rgmii_txctl : out std_logic;`
123			`rgmii_txd : out std_logic_vector(3 downto 0);`
124			`search_eof : out std_logic;`
125			`search_gnt_wr : in std_logic;`
126			`search_key : out std_logic_vector(63 downto 0);`
127			`search_port_stalled : out std_logic;`
128			`search_req : out std_logic;`
129			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
130			`search_result_av : in std_logic;`
131			`search_sof : out std_logic);`
132			`end component esoc_port;`
133
134			`component esoc_control`
135			`port(`
136			`brom_address : out std_logic_vector(10 downto 0);`
137			`brom_rd : out std_logic;`
138			`brom_rddata : in std_logic_vector(31 downto 0);`
139			`clk_control : in std_logic;`
140			`ctrl_address : out std_logic_vector(15 downto 0);`
141			`ctrl_rd : out std_logic;`
142			`ctrl_rddata : in std_logic_vector(31 downto 0);`
143			`ctrl_wait : in std_logic;`
144			`ctrl_wr : out std_logic;`
145			`ctrl_wrdata : out std_logic_vector(31 downto 0);`
146			`esoc_address : in std_logic_vector(15 downto 0);`
147			`esoc_boot_complete : out std_logic;`
148			`esoc_cs : in std_logic;`
149			`esoc_data : inout std_logic_vector(31 downto 0);`
150			`esoc_rd : in std_logic;`
151			`esoc_wait : out std_logic;`
152			`esoc_wr : in std_logic;`
153			`pll1_locked : in STD_LOGIC;`
154			`pll2_locked : in STD_LOGIC;`
155			`reset : in std_logic);`
156			`end component esoc_control;`
157
158			`component esoc_reset`
159			`port(`
160			`clk_control : in std_logic;`
161			`esoc_areset : in std_logic;`
162			`pll1_locked : in STD_LOGIC;`
163			`pll2_locked : in STD_LOGIC;`
164			`reset : out std_logic);`
165			`end component esoc_reset;`
166
167			`component esoc_bus_arbiter`
168			`generic(`
169			`id : integer := 0);`
170			`port(`
171			`bus_eof : in std_logic;`
172			`bus_gnt_rd : out std_logic_vector(esoc_port_count-1 downto 0);`
173			`bus_gnt_wr : out std_logic_vector(esoc_port_count-1 downto 0);`
174			`bus_req : in std_logic_vector(esoc_port_count-1 downto 0);`
175			`bus_sof : in std_logic;`
176			`clk_bus : in std_logic;`
177			`clk_control : in std_logic;`
178			`ctrl_address : in std_logic_vector(15 downto 0);`
179			`ctrl_rd : in std_logic;`
180			`ctrl_rddata : out std_logic_vector(31 downto 0);`
181			`ctrl_wait : out std_logic;`
182			`ctrl_wr : in std_logic;`
183			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
184			`reset : in std_logic);`
185			`end component esoc_bus_arbiter;`
186
187			`component esoc_search_engine`
188			`port(`
189			`clk_control : in std_logic;`
190			`clk_search : in std_logic;`
191			`ctrl_address : in std_logic_vector(15 downto 0);`
192			`ctrl_rd : in std_logic;`
193			`ctrl_rddata : out std_logic_vector(31 downto 0);`
194			`ctrl_wait : out std_logic;`
195			`ctrl_wr : in std_logic;`
196			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
197			`reset : in std_logic;`
198			`search_eof : in std_logic;`
199			`search_key : in std_logic_vector(63 downto 0);`
200			`search_port_stalled : in std_logic_vector(esoc_port_count-1 downto 0);`
201			`search_result : out std_logic_vector(esoc_port_count-1 downto 0);`
202			`search_result_av : out std_logic;`
203			`search_sof : in std_logic);`
204			`end component esoc_search_engine;`
205
206			`component esoc_pll1_c3`
207			`port(`
208			`inclk0 : in STD_LOGIC := '0';`
209			`c0 : out STD_LOGIC;`
210			`c1 : out STD_LOGIC;`
211			`c2 : out STD_LOGIC;`
212			`locked : out STD_LOGIC);`
213			`end component esoc_pll1_c3;`
214
215			`component esoc_pll2_c3`
216			`port(`
217			`inclk0 : in STD_LOGIC := '0';`
218			`c0 : out STD_LOGIC;`
219			`locked : out STD_LOGIC;`
220			`c1 : out STD_LOGIC;`
221			`c2 : out STD_LOGIC);`
222			`end component esoc_pll2_c3;`
223
224			`component esoc_rom_2kx32`
225			`port(`
226			`aclr : in STD_LOGIC;`
227			`address : in STD_LOGIC_VECTOR(10 downto 0);`
228			`clock : in STD_LOGIC;`
229			`data : in STD_LOGIC_VECTOR(31 downto 0);`
230			`rden : in STD_LOGIC;`
231			`wren : in STD_LOGIC;`
232			`q : out STD_LOGIC_VECTOR(31 downto 0));`
233			`end component esoc_rom_2kx32;`
234
235			`begin`
236			`--CLK IN:`
237			`--50MHz`
238			`--CLK OUT:`
239			`--C0 50MHz`
240			`--C1 100MHz`
241			`--C2 150MHz`
242			`--CLK IN:`
243			`--50MHz`
244			`--CLK OUT:`
245			`--C0 125MHz`
246			`--`
247			`--eSoc Clocks and Reset`
248			`--eSoc Host Control Interface`
249			`--eSoc Ethernet ports`
250			`--eSoc Search Engine`
251			`--eSoc Data bus Arbiter`
252			`--eSoc Search bus Arbiter`
253			`--eSoc Boot ROM`
254			`esoc_ports: for esoc_port_nr in esoc_port_count-1 downto 0 generate`
255			`begin`
256			`u0: esoc_port`
257			`generic map(`
258			`esoc_port_nr => esoc_port_nr)`
259			`port map(`
260			`clk_control => clk_control,`
261			`clk_data => clk_data,`
262			`clk_rgmii_125m => clk_rgmii_125m,`
263			`clk_rgmii_25m => clk_rgmii_25m,`
264			`clk_rgmii_2m5 => clk_rgmii_2m5,`
265			`clk_search => clk_search,`
266			`ctrl_address => ctrl_address,`
267			`ctrl_rd => ctrl_rd,`
268			`ctrl_rddata => ctrl_rddata,`
269			`ctrl_wait => ctrl_wait,`
270			`ctrl_wr => ctrl_wr,`
271			`ctrl_wrdata => ctrl_wrdata,`
272			`data => data,`
273			`data_eof => data_eof,`
274			`data_gnt_rd => data_gnt_rd(esoc_port_nr),`
275			`data_gnt_wr => data_gnt_wr(esoc_port_nr),`
276			`data_port_sel => data_port_sel,`
277			`data_req => data_req(esoc_port_nr),`
278			`data_sof => data_sof,`
279			`mdc => esoc_mdc(esoc_port_nr),`
280			`mdio => esoc_mdio(esoc_port_nr),`
281			`reset => reset,`
282			`rgmii_rxc => esoc_rgmii_rxc(esoc_port_nr),`
283			`rgmii_rxctl => esoc_rgmii_rxctl(esoc_port_nr),`
284			`rgmii_rxd => esoc_rgmii_rxd(3+4esoc_port_nr downto 4esoc_port_nr),`
285			`rgmii_txc => esoc_rgmii_txc(esoc_port_nr),`
286			`rgmii_txctl => esoc_rgmii_txctl(esoc_port_nr),`
287			`rgmii_txd => esoc_rgmii_txd(3+4esoc_port_nr downto 4esoc_port_nr),`
288			`search_eof => search_eof,`
289			`search_gnt_wr => search_gnt_wr(esoc_port_nr),`
290			`search_key => search_key,`
291			`search_port_stalled => search_port_stalled(esoc_port_nr),`
292			`search_req => search_req(esoc_port_nr),`
293			`search_result => search_result,`
294			`search_result_av => search_result_av,`
295			`search_sof => search_sof);`
296
297			`end generate esoc_ports;`
298
299			`-- TEST`
300			`u0: esoc_control`
301			`port map(`
302			`brom_address => ctrl_brom_address,`
303			`brom_rd => ctrl_brom_rd,`
304			`brom_rddata => q,`
305			`clk_control => clk_control,`
306			`ctrl_address => ctrl_address,`
307			`ctrl_rd => ctrl_rd,`
308			`ctrl_rddata => ctrl_rddata,`
309			`ctrl_wait => ctrl_wait,`
310			`ctrl_wr => ctrl_wr,`
311			`ctrl_wrdata => ctrl_wrdata,`
312			`esoc_address => esoc_address,`
313			`esoc_boot_complete => esoc_boot_complete,`
314			`esoc_cs => esoc_cs,`
315			`esoc_data => esoc_data,`
316			`esoc_rd => esoc_rd,`
317			`esoc_wait => esoc_wait,`
318			`esoc_wr => esoc_wr,`
319			`pll1_locked => pll1_locked,`
320			`pll2_locked => pll2_locked,`
321			`reset => reset);`
322
323			`u2: esoc_reset`
324			`port map(`
325			`clk_control => clk_control,`
326			`esoc_areset => esoc_areset,`
327			`pll1_locked => pll1_locked,`
328			`pll2_locked => pll2_locked,`
329			`reset => reset);`
330
331			`u4: esoc_bus_arbiter`
332			`generic map(`
333			`id => 0)`
334			`port map(`
335			`bus_eof => data_eof,`
336			`bus_gnt_rd => data_gnt_rd,`
337			`bus_gnt_wr => data_gnt_wr,`
338			`bus_req => data_req,`
339			`bus_sof => data_sof,`
340			`clk_bus => clk_data,`
341			`clk_control => clk_control,`
342			`ctrl_address => ctrl_address,`
343			`ctrl_rd => ctrl_rd,`
344			`ctrl_rddata => ctrl_rddata,`
345			`ctrl_wait => ctrl_wait,`
346			`ctrl_wr => ctrl_wr,`
347			`ctrl_wrdata => ctrl_wrdata,`
348			`reset => reset);`
349
350			`u6: esoc_search_engine`
351			`port map(`
352			`clk_control => clk_control,`
353			`clk_search => clk_search,`
354			`ctrl_address => ctrl_address,`
355			`ctrl_rd => ctrl_rd,`
356			`ctrl_rddata => ctrl_rddata,`
357			`ctrl_wait => ctrl_wait,`
358			`ctrl_wr => ctrl_wr,`
359			`ctrl_wrdata => ctrl_wrdata,`
360			`reset => reset,`
361			`search_eof => search_eof,`
362			`search_key => search_key,`
363			`search_port_stalled => search_port_stalled,`
364			`search_result => search_result,`
365			`search_result_av => search_result_av,`
366			`search_sof => search_sof);`
367
368			`u1: esoc_pll1_c3`
369			`port map(`
370			`inclk0 => esoc_clk,`
371			`c0 => clk_control,`
372			`c1 => clk_search,`
373			`c2 => clk_data,`
374			`locked => pll1_locked);`
375
376			`u3: esoc_pll2_c3`
377			`port map(`
378			`inclk0 => esoc_clk,`
379			`c0 => clk_rgmii_125m,`
380			`locked => pll2_locked,`
381			`c1 => clk_rgmii_25m,`
382			`c2 => clk_rgmii_2m5);`
383
384			`u5: esoc_bus_arbiter`
385			`generic map(`
386			`id => 1)`
387			`port map(`
388			`bus_eof => search_eof,`
389			`bus_gnt_rd => open,`
390			`bus_gnt_wr => search_gnt_wr,`
391			`bus_req => search_req,`
392			`bus_sof => search_sof,`
393			`clk_bus => clk_search,`
394			`clk_control => clk_control,`
395			`ctrl_address => ctrl_address,`
396			`ctrl_rd => ctrl_rd,`
397			`ctrl_rddata => ctrl_rddata,`
398			`ctrl_wait => ctrl_wait,`
399			`ctrl_wr => ctrl_wr,`
400			`ctrl_wrdata => ctrl_wrdata,`
401			`reset => reset);`
402
403			`u7: esoc_rom_2kx32`
404			`port map(`
405			`aclr => reset,`
406			`address => ctrl_brom_address,`
407			`clock => clk_control,`
408			`data => (others => '0'),`
409			`rden => ctrl_brom_rd,`
410			`wren => '0',`
411			`q => q);`
412
413			`end architecture structure ; -- of esoc`
414