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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_bus_arbiter.vhd] - Blame information for rev 46

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1 42 lmaarsen
--------------------------------------------------------------------------------
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----                                                                        ----
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---- Ethernet Switch on Configurable Logic IP Core                          ----
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----                                                                        ----
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---- This file is part of the ESoCL project                                 ----
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---- http://www.opencores.org/cores/esoc/                                   ----
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----                                                                        ----
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---- Description: see design description ESoCL_dd_71022001.pdf              ----
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----                                                                        ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
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----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
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----                                                                        ----
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---- Author(s): L.Maarsen                                                   ----
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---- Bert Maarsen, lmaarsen@opencores.org                                   ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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----                                                                        ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
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----                                                                        ----
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---- This source file may be used and distributed without                   ----
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---- restriction provided that this copyright statement is not              ----
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---- removed from the file and that any derivative work contains            ----
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---- the original copyright notice and the associated disclaimer.           ----
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----                                                                        ----
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---- This source file is free software; you can redistribute it             ----
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---- and/or modify it under the terms of the GNU Lesser General             ----
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---- Public License as published by the Free Software Foundation;           ----
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---- either version 2.1 of the License, or (at your option) any             ----
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---- later version.                                                         ----
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----                                                                        ----
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---- This source is distributed in the hope that it will be                 ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
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---- PURPOSE. See the GNU Lesser General Public License for more            ----
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---- details.                                                               ----
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----                                                                        ----
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---- You should have received a copy of the GNU Lesser General              ----
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---- Public License along with this source; if not, download it             ----
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---- from http://www.opencores.org/lgpl.shtml                               ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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-- Object        : Entity work.esoc_bus_arbiter
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-- Last modified : Mon Apr 14 12:48:27 2014.
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--------------------------------------------------------------------------------
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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entity esoc_bus_arbiter is
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  generic(
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    id : integer := 0);
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  port(
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    bus_eof      : in     std_logic;
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    bus_gnt_rd   : out    std_logic_vector(esoc_port_count-1 downto 0);
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    bus_gnt_wr   : out    std_logic_vector(esoc_port_count-1 downto 0);
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    bus_req      : in     std_logic_vector(esoc_port_count-1 downto 0);
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    bus_sof      : in     std_logic;
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    clk_bus      : in     std_logic;
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    clk_control  : in     std_logic;
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    ctrl_address : in     std_logic_vector(15 downto 0);
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    ctrl_rd      : in     std_logic;
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    ctrl_rddata  : out    std_logic_vector(31 downto 0);
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    ctrl_wait    : out    std_logic;
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    ctrl_wr      : in     std_logic;
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    ctrl_wrdata  : in     std_logic_vector(31 downto 0);
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    reset        : in     std_logic);
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end entity esoc_bus_arbiter;
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--------------------------------------------------------------------------------
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-- Object        : Architecture work.esoc_bus_arbiter.esoc_bus_arbiter
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-- Last modified : Mon Apr 14 12:48:27 2014.
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--------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- architecture and declarations
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---------------------------------------------------------------------------------------------------------------
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architecture esoc_bus_arbiter of esoc_bus_arbiter is
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---------------------------------------------------------------------------------------------------------------
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-- registers
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---------------------------------------------------------------------------------------------------------------
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constant reg_arb_port_disable_add: integer                        := 7;
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signal   reg_arb_port_disable_dat: std_logic_vector(31 downto 0);
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constant reg_arb_port_disable_rst: std_logic_vector(31 downto 0)  := X"00000000";
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constant reg_arb_port_weight_add: integer                         := 0;
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signal   reg_arb_port_weight_dat: std_logic_vector(31 downto 0);
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constant reg_arb_port_weight_rst: std_logic_vector(31 downto 0)   := X"00000000";
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---------------------------------------------------------------------------------------------------------------
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-- signals
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---------------------------------------------------------------------------------------------------------------
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signal port_select: integer range esoc_port_count-1 downto 0;
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signal port_request: std_logic;
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signal port_request_weight: std_logic_vector(1 downto 0);
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type states_data_bus is (idle, wait_sof, wait_eof);
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signal state_data_bus: states_data_bus;
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signal ctrl_rddata_i: std_logic_vector(ctrl_rddata'high downto 0);
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signal ctrl_wait_i: std_logic;
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signal ctrl_bus_enable: std_logic;
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begin
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--=============================================================================================================
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-- Process                : process data bus access request, use weight factor for each port and approve access
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-- Description  : 
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--=============================================================================================================    
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req_scan: process(clk_bus, reset)
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          begin
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            if reset = '1' then
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              port_select <= 0;
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              port_request <= '0';
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              port_request_weight <= (others => '0');
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              bus_gnt_wr <= (others => '0');
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              bus_gnt_rd <= (others => '0');
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              state_data_bus <= idle;
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            elsif clk_bus'event and clk_bus = '1' then
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              -- scan request outputs from all ESOC ports, if asserted wait for free data bus
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              if bus_req(port_select) = '1' and reg_arb_port_disable_dat(port_select) = '0' then
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                port_request <= '1';
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              -- request output deasserted, current weight factor zero? determine next port to check, use weight factor of current port
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              else
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                port_request <= '0';
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                -- check weight of processed port, scan port again or go to next port with appropriate weight?
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                if to_integer(unsigned(port_request_weight)) = 0 then
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                  if port_select = esoc_port_count-1 then
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                    port_select <= 0;
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                    port_request_weight <= reg_arb_port_weight_dat(1) & reg_arb_port_weight_dat(0);
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                  else
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                    port_select <= port_select + 1;
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                    port_request_weight <= reg_arb_port_weight_dat(2*(port_select+1)+1) & reg_arb_port_weight_dat(2*(port_select+1));
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                  end if;
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                -- weight not 0, do not proceed with next port, but decrease weight of actual port
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                else
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                  port_request_weight <= std_logic_vector(to_unsigned(to_integer(unsigned(port_request_weight))-1,2));
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                end if;
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              end if;
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              -- monitor the data bus state and control the scan process
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              case state_data_bus is
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                when idle =>      -- if there is a bus request, give a write grant to selected port, a read grant to all other ports and wait for SOF and EOF
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                                  if port_request = '1' then
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                                    bus_gnt_wr(port_select) <= '1';
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                                    bus_gnt_rd <= (others => '1');
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                                    state_data_bus <= wait_sof;
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                                  end if;
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                when wait_sof =>  -- wait for start of packet, no further actions required yet (future)
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                                  if bus_sof = '1' then
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                                   state_data_bus <= wait_eof;
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                                  end if;
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                 when wait_eof => -- End of packet detect? Terminate and go back to idle.
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                                  if bus_eof = '1' then
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                                    bus_gnt_wr <= (others => '0');
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                                    bus_gnt_rd <= (others => '0');
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                                    state_data_bus <= idle;
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                                  end if;
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                 when others =>   state_data_bus <= idle;
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               end case;
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            end if;
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          end process;
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--=============================================================================================================
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-- Process                : access registers when addressed or provide data from other units to the readdata bus
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-- Description  : 
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--=============================================================================================================    
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registers:  process(clk_control, reset)
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            begin
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              if reset = '1' then
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                -- all ports have weight 1 after reset
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                reg_arb_port_disable_dat  <= reg_arb_port_disable_rst;
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                reg_arb_port_weight_dat   <= reg_arb_port_weight_rst;
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                ctrl_rddata_i             <= (others => '0');
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                ctrl_wait_i               <= '1';
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                ctrl_bus_enable           <= '0';
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              elsif clk_control'event and clk_control = '1' then
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                ctrl_wait_i   <= '1';
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                ctrl_bus_enable <= '0';
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                -- continu if memory space of this entity is addressed
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                if to_integer(unsigned(ctrl_address)) >= (esoc_bus_arbiter_base + (id * esoc_bus_arbiter_size)) and to_integer(unsigned(ctrl_address)) < (esoc_bus_arbiter_base + (id * esoc_bus_arbiter_size) + esoc_bus_arbiter_size) then
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                  ctrl_bus_enable <= '1';
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                        --
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                        -- READ CYCLE started, unit addressed?
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                        --
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                        if ctrl_rd = '1' then
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                                -- Check register address and provide data when addressed
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                          case to_integer(unsigned(ctrl_address))- esoc_bus_arbiter_base - (id * esoc_bus_arbiter_size) is
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                      when reg_arb_port_disable_add  =>    ctrl_rddata_i <= reg_arb_port_disable_dat;
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                                                           ctrl_wait_i <= '0';
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                      when reg_arb_port_weight_add   =>    ctrl_rddata_i <= reg_arb_port_weight_dat;
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                                                           ctrl_wait_i <= '0';
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                      when others                    =>    NULL;
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                    end case;
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                  --
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                  -- WRITE CYCLE started, unit addressed?  
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                  --
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                  elsif ctrl_wr = '1' then
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                        -- Check address and accept data when addressed
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                        case to_integer(unsigned(ctrl_address))- esoc_bus_arbiter_base  - (id * esoc_bus_arbiter_size) is
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                      when reg_arb_port_disable_add  =>  reg_arb_port_disable_dat <= ctrl_wrdata;
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                                                         ctrl_wait_i <= '0';
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                      when reg_arb_port_weight_add   =>  reg_arb_port_weight_dat <= ctrl_wrdata;
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                                                         ctrl_wait_i <= '0';
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                      when others                    =>  NULL;
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                    end case;
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                  end if;
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                end if;
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              end if;
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            end process;
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            -- Create tristate outputs
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            ctrl_wait   <= ctrl_wait_i    when ctrl_bus_enable = '1' else 'Z';
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            ctrl_rddata <= ctrl_rddata_i  when ctrl_bus_enable = '1' else (others => 'Z');
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end architecture esoc_bus_arbiter ; -- of esoc_bus_arbiter

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