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--------------------------------------------------------------------------------
----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_control
-- Last modified : Thu Apr 17 12:55:38 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_control is
  port(
    brom_address       : out    std_logic_vector(10 downto 0);
    brom_rd            : out    std_logic;
    brom_rddata        : in     std_logic_vector(31 downto 0);
    clk_control        : in     std_logic;
    ctrl_address       : out    std_logic_vector(15 downto 0);
    ctrl_rd            : out    std_logic;
    ctrl_rddata        : in     std_logic_vector(31 downto 0);
    ctrl_wait          : in     std_logic;
    ctrl_wr            : out    std_logic;
    ctrl_wrdata        : out    std_logic_vector(31 downto 0);
    esoc_address       : in     std_logic_vector(15 downto 0);
    esoc_boot_complete : out    std_logic;
    esoc_cs            : in     std_logic;
    esoc_data          : inout  std_logic_vector(31 downto 0);
    esoc_rd            : in     std_logic;
    esoc_wait          : out    std_logic;
    esoc_wr            : in     std_logic;
    pll1_locked        : in     STD_LOGIC;
    pll2_locked        : in     STD_LOGIC;
    reset              : in     std_logic);
end entity esoc_control;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_control.esoc_control
-- Last modified : Thu Apr 17 12:55:38 2014.
--------------------------------------------------------------------------------
 
 
---------------------------------------------------------------------------------------------------------------
-- architecture and declarations
---------------------------------------------------------------------------------------------------------------
architecture esoc_control of esoc_control is
 
---------------------------------------------------------------------------------------------------------------
-- registers
---------------------------------------------------------------------------------------------------------------
-- register and bit definitions
constant reg_ctrl_id_add       : integer                         := 0;
 
constant reg_ctrl_version_add  : integer                         := 1;
 
constant reg_ctrl_stat_ctrl_add   : integer                      := 2;
 
constant reg_ctrl_scratch_add  : integer                         := 3;
signal   reg_ctrl_scratch_dat  : std_logic_vector(31 downto 0);
constant reg_ctrl_scratch_rst  : std_logic_vector(31 downto 0)   := X"00000000";
 
---------------------------------------------------------------------------------------------------------------
-- signals
---------------------------------------------------------------------------------------------------------------
type ctrl_bus_states is (boot, boot_wait, boot_rd_add, boot_rd_dat, operational);
signal ctrl_bus_state: ctrl_bus_states;
 
signal esoc_rd_sync: std_logic_vector(2 downto 0);
signal esoc_wr_sync: std_logic_vector(2 downto 0);
 
signal ctrl_rd_i: std_logic;
signal ctrl_wr_i: std_logic;
signal ctrl_rdwr_i: std_logic;
signal ctrl_rddata_i: std_logic_vector(31 downto 0);
signal ctrl_wrdata_i: std_logic_vector(31 downto 0);
signal ctrl_address_i: std_logic_vector(ctrl_address'high downto 0);
signal ctrl_wait_i: std_logic;
 
constant brom_wait_count_init: integer := 31;
signal brom_wait_count: integer range brom_wait_count_init downto 0;
signal brom_address_count: integer range 2**brom_address'length-1 downto 0;
signal brom_error: std_logic;
 
signal pll1_locked_sync: std_logic_vector(esoc_meta_ffs-1 downto 0);
signal pll2_locked_sync: std_logic_vector(esoc_meta_ffs-1 downto 0);
 
begin
 
--=============================================================================================================
-- Process                : synchronise asynchronous control inputs
-- Description  : 
--=============================================================================================================
sync:   process(clk_control, reset)
        begin
          if reset = '1' then
            esoc_rd_sync <= (others => '0');
            esoc_wr_sync <= (others => '0');
 
            pll1_locked_sync <= (others => '0');
            pll2_locked_sync <= (others => '0');
 
          elsif clk_control'event and clk_control = '1' then
            esoc_rd_sync <= (esoc_cs and esoc_rd) & esoc_rd_sync(esoc_rd_sync'high downto 1);
            esoc_wr_sync <= (esoc_cs and esoc_wr) & esoc_wr_sync(esoc_wr_sync'high downto 1);
 
            pll1_locked_sync <= pll1_locked & pll1_locked_sync(pll1_locked_sync'high downto 1);
            pll2_locked_sync <= pll2_locked & pll2_locked_sync(pll2_locked_sync'high downto 1);
          end if;
        end process;
 
--=============================================================================================================
-- Process                : control internal bus with external bus signal
-- Description  : 
--=============================================================================================================       
ctrlbus:  process(clk_control, reset)
          begin
            if reset = '1' then
              ctrl_rd_i          <= '0';
              ctrl_wr_i          <= '0';
              ctrl_rdwr_i        <= '0';
              ctrl_address_i     <= (others => '0');
              ctrl_wrdata_i      <= (others => '0');
              ctrl_bus_state     <= boot;
 
              brom_rd            <= '0';
              brom_address       <= (others => '0');
              brom_address_count <= 0;
              brom_wait_count    <= 0;
 
              brom_error         <= '0';
              esoc_boot_complete <= '0';
 
            elsif clk_control'event and clk_control = '1' then
 
              case ctrl_bus_state is
                when boot         =>  -- boot from rom disabled, start read from boot rom
                                      if esoc_brom_mode = enabled then
                                        brom_rd            <= '1';
                                        brom_address       <= std_logic_vector(to_unsigned(brom_address_count,brom_address'length));
                                        brom_address_count <= brom_address_count + 1;
                                        ctrl_bus_state     <= boot_wait;
 
                                      -- boot from rom disabled, step to operational state immediately
                                      else
                                        esoc_boot_complete <= '1';
                                        ctrl_bus_state     <= operational;
                                      end if;
 
                when boot_wait    =>  -- wait for word from boot rom (the register address), continu read from boot prom
                                      brom_rd             <= '1';
                                      brom_address      <= std_logic_vector(to_unsigned(brom_address_count,brom_address'length));
                                      brom_address_count <= brom_address_count + 1;
                                      ctrl_bus_state      <= boot_rd_add;
 
                when boot_rd_add  =>  -- evaluate word from boot rom (the register address) and wait for word from boot rom (the register content)
                                      brom_rd <= '0';
 
                                      -- stop reading from boot rom if all ones is returned
                                      if brom_rddata = X"FFFFFFFF" then
                                        brom_error         <= '0';
                                        esoc_boot_complete <= '1';
                                        ctrl_bus_state     <= operational;
 
                                      -- prepare write on internal bus by providing the address, init wait counter for dead lock detection
                                      else
                                        brom_wait_count   <= brom_wait_count_init;
                                        ctrl_address_i    <= brom_rddata(ctrl_address_i'high downto 0);
                                        ctrl_bus_state    <= boot_rd_dat;
                                      end if;
 
                when boot_rd_dat  =>  -- word from boot rom (the register content) available, start write cycle on internal bus and wait for ACK
                                      ctrl_wr_i           <= '1';
                                      ctrl_rdwr_i         <= '1';
                                      ctrl_wrdata_i       <= brom_rddata;
 
                                      -- wait for acknowledge, start counter to avoid dead lock due to wrong ROM content
                                      if ctrl_wait = '0' or ctrl_wait_i = '0' then
                                        ctrl_wr_i          <= '0';
                                        ctrl_bus_state     <= boot;
 
                                      -- write cycle time out? Terminate boot initialisation!  
                                      elsif brom_wait_count = 0 then
                                        brom_error         <= '1';
                                        esoc_boot_complete <= '1';
                                        ctrl_wr_i          <= '0';
                                        ctrl_bus_state     <= operational;
 
                                      -- count down  
                                      else
                                        brom_wait_count <= brom_wait_count - 1;
                                      end if;
 
                when operational  =>  -- detect rising edge of synchronized read signal, check address and drive internal signals of control bus
                                      if esoc_rd_sync(esoc_rd_sync'low+1 downto 0) = "10"  and to_integer(unsigned(esoc_address)) >= esoc_base and to_integer(unsigned(esoc_address)) < esoc_base + esoc_size then
                                        ctrl_rd_i <= '1';
                                        ctrl_rdwr_i <= '0';
                                        ctrl_address_i <= esoc_address;
 
                                      -- detect rising edge of synchronized write signal, check address and drive internal signals of control bus
                                      elsif esoc_wr_sync(esoc_wr_sync'low+1 downto 0) = "10" and to_integer(unsigned(esoc_address)) >= esoc_base and to_integer(unsigned(esoc_address)) < esoc_base + esoc_size then
                                        ctrl_wr_i <= '1';
                                        ctrl_rdwr_i <= '1';
                                        ctrl_wrdata_i <= esoc_data;
                                        ctrl_address_i  <= esoc_address;
 
                                      -- reset internal signals read/write after acknowledge from addresses unit (ack = inactive wait)
                                      elsif ctrl_wait = '0' or ctrl_wait_i = '0'  then
                                        ctrl_rd_i <= '0';
                                        ctrl_wr_i <= '0';
                                      end if;
 
                when others =>        ctrl_bus_state <= boot;
              end case;
            end if;
          end process;
 
          -- use eSOC control interface inputs to drive eSOC control bus signals after initialisation by boot rom
          ctrl_rd       <= ctrl_rd_i;
          ctrl_wr       <= ctrl_wr_i;
          ctrl_address  <= ctrl_address_i;
          ctrl_wrdata   <= ctrl_wrdata_i;
 
          -- use eSOC control bus signals to drive eSOC control interface outputs
          esoc_data   <= ctrl_rddata      when ctrl_wait   = '0' and ctrl_rdwr_i = '0'  else
                         ctrl_rddata_i  when ctrl_wait_i = '0' and ctrl_rdwr_i = '0'  else (others => 'Z');
 
          esoc_wait     <= '0'                                     when ctrl_wait   = '0' or  ctrl_wait_i = '0'   else 'Z';
 
 
--=============================================================================================================
-- Process                : access registers of control unit itself
-- Description  : 
--=============================================================================================================    
registers:  process(clk_control, reset)
            begin
              if reset = '1' then
                reg_ctrl_scratch_dat <= reg_ctrl_scratch_rst;
                ctrl_wait_i <= '1';
                ctrl_rddata_i <= (others => '0');
 
              elsif clk_control'event and clk_control = '1' then
                ctrl_wait_i <= '1';
 
                -- continu if memory space of this entity is addressed
                if to_integer(unsigned(ctrl_address_i)) >= esoc_control_base and to_integer(unsigned(ctrl_address_i)) < esoc_control_base + esoc_control_size then
                        --
                        -- READ CYCLE started, unit addressed?
                        --
                        if ctrl_rd_i = '1' then
                                -- Check register address and provide data when addressed
                          case to_integer(unsigned(ctrl_address_i))- esoc_control_base is
                            when reg_ctrl_id_add        =>  ctrl_rddata_i <= esoc_id;
                                                            ctrl_wait_i <= '0';
 
                            when reg_ctrl_version_add   =>  ctrl_rddata_i <= std_logic_vector(to_unsigned(esoc_version,16)) & std_logic_vector(to_unsigned(esoc_release,16));
                                                            ctrl_wait_i <= '0';
 
                            when reg_ctrl_stat_ctrl_add =>  if esoc_brom_mode = enabled then
                                                              ctrl_rddata_i <= pll2_locked_sync(0) & pll1_locked_sync(0) & brom_error & '1' & X"000000" & std_logic_vector(to_unsigned(esoc_port_count,4));
                                                            else
                                                              ctrl_rddata_i <= pll2_locked_sync(0) & pll1_locked_sync(0) & brom_error & '0' & X"000000" & std_logic_vector(to_unsigned(esoc_port_count,4));
                                                            end if;
 
                                                            ctrl_wait_i <= '0';
 
                      when reg_ctrl_scratch_add   =>  ctrl_rddata_i <= reg_ctrl_scratch_dat;
                                                            ctrl_wait_i <= '0';
 
                            when others                 =>  NULL;
                          end case;
 
                        --
                        -- WRITE CYCLE started, unit addressed?  
                        --
                        elsif ctrl_wr_i = '1' then
                                -- Check register address and accept data when addressed
                                case to_integer(unsigned(ctrl_address_i)) - esoc_control_base is
                            when reg_ctrl_scratch_add  =>   reg_ctrl_scratch_dat <= ctrl_wrdata_i;
                                                            ctrl_wait_i <= '0';
                      when others                =>   NULL;
                          end case;
                                                                end if;
                                                  end if;
              end if;
            end process;
end architecture esoc_control ; -- of esoc_control
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_control.vhd] - Blame information for rev 42

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- Ethernet Switch on Configurable Logic IP Core ----`
4			`---- ----`
5			`---- This file is part of the ESoCL project ----`
6			`---- http://www.opencores.org/cores/esoc/ ----`
7			`---- ----`
8			`---- Description: see design description ESoCL_dd_71022001.pdf ----`
9			`---- ----`
10			`---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----`
11			`---- and/or release bulleting ESoCL_rb_71022001.pdf ----`
12			`---- ----`
13			`---- Author(s): L.Maarsen ----`
14			`---- Bert Maarsen, lmaarsen@opencores.org ----`
15			`---- ----`
16			`--------------------------------------------------------------------------------`
17			`---- ----`
18			`---- Copyright (C) 2009 Authors and OPENCORES.ORG ----`
19			`---- ----`
20			`---- This source file may be used and distributed without ----`
21			`---- restriction provided that this copyright statement is not ----`
22			`---- removed from the file and that any derivative work contains ----`
23			`---- the original copyright notice and the associated disclaimer. ----`
24			`---- ----`
25			`---- This source file is free software; you can redistribute it ----`
26			`---- and/or modify it under the terms of the GNU Lesser General ----`
27			`---- Public License as published by the Free Software Foundation; ----`
28			`---- either version 2.1 of the License, or (at your option) any ----`
29			`---- later version. ----`
30			`---- ----`
31			`---- This source is distributed in the hope that it will be ----`
32			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
33			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
34			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
35			`---- details. ----`
36			`---- ----`
37			`---- You should have received a copy of the GNU Lesser General ----`
38			`---- Public License along with this source; if not, download it ----`
39			`---- from http://www.opencores.org/lgpl.shtml ----`
40			`---- ----`
41			`--------------------------------------------------------------------------------`
42			`-- Object : Entity work.esoc_control`
43			`-- Last modified : Thu Apr 17 12:55:38 2014.`
44			`--------------------------------------------------------------------------------`
45
46
47
48			`library ieee, std, work;`
49			`use ieee.std_logic_1164.all;`
50			`use std.textio.all;`
51			`use ieee.numeric_std.all;`
52			`use work.package_esoc_configuration.all;`
53
54			`entity esoc_control is`
55			`port(`
56			`brom_address : out std_logic_vector(10 downto 0);`
57			`brom_rd : out std_logic;`
58			`brom_rddata : in std_logic_vector(31 downto 0);`
59			`clk_control : in std_logic;`
60			`ctrl_address : out std_logic_vector(15 downto 0);`
61			`ctrl_rd : out std_logic;`
62			`ctrl_rddata : in std_logic_vector(31 downto 0);`
63			`ctrl_wait : in std_logic;`
64			`ctrl_wr : out std_logic;`
65			`ctrl_wrdata : out std_logic_vector(31 downto 0);`
66			`esoc_address : in std_logic_vector(15 downto 0);`
67			`esoc_boot_complete : out std_logic;`
68			`esoc_cs : in std_logic;`
69			`esoc_data : inout std_logic_vector(31 downto 0);`
70			`esoc_rd : in std_logic;`
71			`esoc_wait : out std_logic;`
72			`esoc_wr : in std_logic;`
73			`pll1_locked : in STD_LOGIC;`
74			`pll2_locked : in STD_LOGIC;`
75			`reset : in std_logic);`
76			`end entity esoc_control;`
77
78			`--------------------------------------------------------------------------------`
79			`-- Object : Architecture work.esoc_control.esoc_control`
80			`-- Last modified : Thu Apr 17 12:55:38 2014.`
81			`--------------------------------------------------------------------------------`
82
83
84			`---------------------------------------------------------------------------------------------------------------`
85			`-- architecture and declarations`
86			`---------------------------------------------------------------------------------------------------------------`
87			`architecture esoc_control of esoc_control is`
88
89			`---------------------------------------------------------------------------------------------------------------`
90			`-- registers`
91			`---------------------------------------------------------------------------------------------------------------`
92			`-- register and bit definitions`
93			`constant reg_ctrl_id_add : integer := 0;`
94
95			`constant reg_ctrl_version_add : integer := 1;`
96
97			`constant reg_ctrl_stat_ctrl_add : integer := 2;`
98
99			`constant reg_ctrl_scratch_add : integer := 3;`
100			`signal reg_ctrl_scratch_dat : std_logic_vector(31 downto 0);`
101			`constant reg_ctrl_scratch_rst : std_logic_vector(31 downto 0) := X"00000000";`
102
103			`---------------------------------------------------------------------------------------------------------------`
104			`-- signals`
105			`---------------------------------------------------------------------------------------------------------------`
106			`type ctrl_bus_states is (boot, boot_wait, boot_rd_add, boot_rd_dat, operational);`
107			`signal ctrl_bus_state: ctrl_bus_states;`
108
109			`signal esoc_rd_sync: std_logic_vector(2 downto 0);`
110			`signal esoc_wr_sync: std_logic_vector(2 downto 0);`
111
112			`signal ctrl_rd_i: std_logic;`
113			`signal ctrl_wr_i: std_logic;`
114			`signal ctrl_rdwr_i: std_logic;`
115			`signal ctrl_rddata_i: std_logic_vector(31 downto 0);`
116			`signal ctrl_wrdata_i: std_logic_vector(31 downto 0);`
117			`signal ctrl_address_i: std_logic_vector(ctrl_address'high downto 0);`
118			`signal ctrl_wait_i: std_logic;`
119
120			`constant brom_wait_count_init: integer := 31;`
121			`signal brom_wait_count: integer range brom_wait_count_init downto 0;`
122			`signal brom_address_count: integer range 2**brom_address'length-1 downto 0;`
123			`signal brom_error: std_logic;`
124
125			`signal pll1_locked_sync: std_logic_vector(esoc_meta_ffs-1 downto 0);`
126			`signal pll2_locked_sync: std_logic_vector(esoc_meta_ffs-1 downto 0);`
127
128			`begin`
129
130			`--=============================================================================================================`
131			`-- Process : synchronise asynchronous control inputs`
132			`-- Description :`
133			`--=============================================================================================================`
134			`sync: process(clk_control, reset)`
135			`begin`
136			`if reset = '1' then`
137			`esoc_rd_sync <= (others => '0');`
138			`esoc_wr_sync <= (others => '0');`
139
140			`pll1_locked_sync <= (others => '0');`
141			`pll2_locked_sync <= (others => '0');`
142
143			`elsif clk_control'event and clk_control = '1' then`
144			`esoc_rd_sync <= (esoc_cs and esoc_rd) & esoc_rd_sync(esoc_rd_sync'high downto 1);`
145			`esoc_wr_sync <= (esoc_cs and esoc_wr) & esoc_wr_sync(esoc_wr_sync'high downto 1);`
146
147			`pll1_locked_sync <= pll1_locked & pll1_locked_sync(pll1_locked_sync'high downto 1);`
148			`pll2_locked_sync <= pll2_locked & pll2_locked_sync(pll2_locked_sync'high downto 1);`
149			`end if;`
150			`end process;`
151
152			`--=============================================================================================================`
153			`-- Process : control internal bus with external bus signal`
154			`-- Description :`
155			`--=============================================================================================================`
156			`ctrlbus: process(clk_control, reset)`
157			`begin`
158			`if reset = '1' then`
159			`ctrl_rd_i <= '0';`
160			`ctrl_wr_i <= '0';`
161			`ctrl_rdwr_i <= '0';`
162			`ctrl_address_i <= (others => '0');`
163			`ctrl_wrdata_i <= (others => '0');`
164			`ctrl_bus_state <= boot;`
165
166			`brom_rd <= '0';`
167			`brom_address <= (others => '0');`
168			`brom_address_count <= 0;`
169			`brom_wait_count <= 0;`
170
171			`brom_error <= '0';`
172			`esoc_boot_complete <= '0';`
173
174			`elsif clk_control'event and clk_control = '1' then`
175
176			`case ctrl_bus_state is`
177			`when boot => -- boot from rom disabled, start read from boot rom`
178			`if esoc_brom_mode = enabled then`
179			`brom_rd <= '1';`
180			`brom_address <= std_logic_vector(to_unsigned(brom_address_count,brom_address'length));`
181			`brom_address_count <= brom_address_count + 1;`
182			`ctrl_bus_state <= boot_wait;`
183
184			`-- boot from rom disabled, step to operational state immediately`
185			`else`
186			`esoc_boot_complete <= '1';`
187			`ctrl_bus_state <= operational;`
188			`end if;`
189
190			`when boot_wait => -- wait for word from boot rom (the register address), continu read from boot prom`
191			`brom_rd <= '1';`
192			`brom_address <= std_logic_vector(to_unsigned(brom_address_count,brom_address'length));`
193			`brom_address_count <= brom_address_count + 1;`
194			`ctrl_bus_state <= boot_rd_add;`
195
196			`when boot_rd_add => -- evaluate word from boot rom (the register address) and wait for word from boot rom (the register content)`
197			`brom_rd <= '0';`
198
199			`-- stop reading from boot rom if all ones is returned`
200			`if brom_rddata = X"FFFFFFFF" then`
201			`brom_error <= '0';`
202			`esoc_boot_complete <= '1';`
203			`ctrl_bus_state <= operational;`
204
205			`-- prepare write on internal bus by providing the address, init wait counter for dead lock detection`
206			`else`
207			`brom_wait_count <= brom_wait_count_init;`
208			`ctrl_address_i <= brom_rddata(ctrl_address_i'high downto 0);`
209			`ctrl_bus_state <= boot_rd_dat;`
210			`end if;`
211
212			`when boot_rd_dat => -- word from boot rom (the register content) available, start write cycle on internal bus and wait for ACK`
213			`ctrl_wr_i <= '1';`
214			`ctrl_rdwr_i <= '1';`
215			`ctrl_wrdata_i <= brom_rddata;`
216
217			`-- wait for acknowledge, start counter to avoid dead lock due to wrong ROM content`
218			`if ctrl_wait = '0' or ctrl_wait_i = '0' then`
219			`ctrl_wr_i <= '0';`
220			`ctrl_bus_state <= boot;`
221
222			`-- write cycle time out? Terminate boot initialisation!`
223			`elsif brom_wait_count = 0 then`
224			`brom_error <= '1';`
225			`esoc_boot_complete <= '1';`
226			`ctrl_wr_i <= '0';`
227			`ctrl_bus_state <= operational;`
228
229			`-- count down`
230			`else`
231			`brom_wait_count <= brom_wait_count - 1;`
232			`end if;`
233
234			`when operational => -- detect rising edge of synchronized read signal, check address and drive internal signals of control bus`
235			`if esoc_rd_sync(esoc_rd_sync'low+1 downto 0) = "10" and to_integer(unsigned(esoc_address)) >= esoc_base and to_integer(unsigned(esoc_address)) < esoc_base + esoc_size then`
236			`ctrl_rd_i <= '1';`
237			`ctrl_rdwr_i <= '0';`
238			`ctrl_address_i <= esoc_address;`
239
240			`-- detect rising edge of synchronized write signal, check address and drive internal signals of control bus`
241			`elsif esoc_wr_sync(esoc_wr_sync'low+1 downto 0) = "10" and to_integer(unsigned(esoc_address)) >= esoc_base and to_integer(unsigned(esoc_address)) < esoc_base + esoc_size then`
242			`ctrl_wr_i <= '1';`
243			`ctrl_rdwr_i <= '1';`
244			`ctrl_wrdata_i <= esoc_data;`
245			`ctrl_address_i <= esoc_address;`
246
247			`-- reset internal signals read/write after acknowledge from addresses unit (ack = inactive wait)`
248			`elsif ctrl_wait = '0' or ctrl_wait_i = '0' then`
249			`ctrl_rd_i <= '0';`
250			`ctrl_wr_i <= '0';`
251			`end if;`
252
253			`when others => ctrl_bus_state <= boot;`
254			`end case;`
255			`end if;`
256			`end process;`
257
258			`-- use eSOC control interface inputs to drive eSOC control bus signals after initialisation by boot rom`
259			`ctrl_rd <= ctrl_rd_i;`
260			`ctrl_wr <= ctrl_wr_i;`
261			`ctrl_address <= ctrl_address_i;`
262			`ctrl_wrdata <= ctrl_wrdata_i;`
263
264			`-- use eSOC control bus signals to drive eSOC control interface outputs`
265			`esoc_data <= ctrl_rddata when ctrl_wait = '0' and ctrl_rdwr_i = '0' else`
266			`ctrl_rddata_i when ctrl_wait_i = '0' and ctrl_rdwr_i = '0' else (others => 'Z');`
267
268			`esoc_wait <= '0' when ctrl_wait = '0' or ctrl_wait_i = '0' else 'Z';`
269
270
271			`--=============================================================================================================`
272			`-- Process : access registers of control unit itself`
273			`-- Description :`
274			`--=============================================================================================================`
275			`registers: process(clk_control, reset)`
276			`begin`
277			`if reset = '1' then`
278			`reg_ctrl_scratch_dat <= reg_ctrl_scratch_rst;`
279			`ctrl_wait_i <= '1';`
280			`ctrl_rddata_i <= (others => '0');`
281
282			`elsif clk_control'event and clk_control = '1' then`
283			`ctrl_wait_i <= '1';`
284
285			`-- continu if memory space of this entity is addressed`
286			`if to_integer(unsigned(ctrl_address_i)) >= esoc_control_base and to_integer(unsigned(ctrl_address_i)) < esoc_control_base + esoc_control_size then`
287			`--`
288			`-- READ CYCLE started, unit addressed?`
289			`--`
290			`if ctrl_rd_i = '1' then`
291			`-- Check register address and provide data when addressed`
292			`case to_integer(unsigned(ctrl_address_i))- esoc_control_base is`
293			`when reg_ctrl_id_add => ctrl_rddata_i <= esoc_id;`
294			`ctrl_wait_i <= '0';`
295
296			`when reg_ctrl_version_add => ctrl_rddata_i <= std_logic_vector(to_unsigned(esoc_version,16)) & std_logic_vector(to_unsigned(esoc_release,16));`
297			`ctrl_wait_i <= '0';`
298
299			`when reg_ctrl_stat_ctrl_add => if esoc_brom_mode = enabled then`
300			`ctrl_rddata_i <= pll2_locked_sync(0) & pll1_locked_sync(0) & brom_error & '1' & X"000000" & std_logic_vector(to_unsigned(esoc_port_count,4));`
301			`else`
302			`ctrl_rddata_i <= pll2_locked_sync(0) & pll1_locked_sync(0) & brom_error & '0' & X"000000" & std_logic_vector(to_unsigned(esoc_port_count,4));`
303			`end if;`
304
305			`ctrl_wait_i <= '0';`
306
307			`when reg_ctrl_scratch_add => ctrl_rddata_i <= reg_ctrl_scratch_dat;`
308			`ctrl_wait_i <= '0';`
309
310			`when others => NULL;`
311			`end case;`
312
313			`--`
314			`-- WRITE CYCLE started, unit addressed?`
315			`--`
316			`elsif ctrl_wr_i = '1' then`
317			`-- Check register address and accept data when addressed`
318			`case to_integer(unsigned(ctrl_address_i)) - esoc_control_base is`
319			`when reg_ctrl_scratch_add => reg_ctrl_scratch_dat <= ctrl_wrdata_i;`
320			`ctrl_wait_i <= '0';`
321			`when others => NULL;`
322			`end case;`
323			`end if;`
324			`end if;`
325			`end if;`
326			`end process;`
327			`end architecture esoc_control ; -- of esoc_control`
328