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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port.vhd] - Blame information for rev 47

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--------------------------------------------------------------------------------
----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_port
-- Last modified : Mon Apr 14 12:48:46 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_port is
  generic(
    esoc_port_nr : integer := 0);
  port(
    clk_control         : in     std_logic;
    clk_data            : in     std_logic;
    clk_rgmii_125m      : in     STD_LOGIC;
    clk_rgmii_25m       : in     STD_LOGIC;
    clk_rgmii_2m5       : in     STD_LOGIC;
    clk_search          : in     std_logic;
    ctrl_address        : in     std_logic_vector(15 downto 0);
    ctrl_rd             : in     std_logic;
    ctrl_rddata         : out    std_logic_vector(31 downto 0);
    ctrl_wait           : out    std_logic;
    ctrl_wr             : in     std_logic;
    ctrl_wrdata         : in     std_logic_vector(31 downto 0);
    data                : inout  std_logic_vector(63 downto 0);
    data_eof            : inout  std_logic;
    data_gnt_rd         : in     std_logic;
    data_gnt_wr         : in     std_logic;
    data_port_sel       : inout  std_logic_vector(esoc_port_count-1 downto 0);
    data_req            : out    std_logic;
    data_sof            : inout  std_logic;
    mdc                 : out    std_logic;
    mdio                : inout  std_logic;
    reset               : in     std_logic;
    rgmii_rxc           : in     std_logic;
    rgmii_rxctl         : in     std_logic;
    rgmii_rxd           : in     std_logic_vector(3 downto 0);
    rgmii_txc           : out    std_logic;
    rgmii_txctl         : out    std_logic;
    rgmii_txd           : out    std_logic_vector(3 downto 0);
    search_eof          : out    std_logic;
    search_gnt_wr       : in     std_logic;
    search_key          : out    std_logic_vector(63 downto 0);
    search_port_stalled : out    std_logic;
    search_req          : out    std_logic;
    search_result       : in     std_logic_vector(esoc_port_count-1 downto 0);
    search_result_av    : in     std_logic;
    search_sof          : out    std_logic);
end entity esoc_port;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_port.esoc_port
-- Last modified : Mon Apr 14 12:48:46 2014.
--------------------------------------------------------------------------------
 
architecture esoc_port of esoc_port is
 
  signal Net_0                   : std_logic;
  signal Net_1                   : std_logic_vector(31 downto 0);
  signal Net_2                   : std_logic;
  signal Net_3                   : std_logic_vector(31 downto 0);
  signal Net_4                   : std_logic;
  signal Net_5                   : std_logic_vector(111 downto 0);
  signal Net_6                   : std_logic;
  signal Net_7                   : std_logic_vector(31 downto 0);
  signal Net_8                   : std_logic;
  signal Net_9                   : std_logic_vector(15 downto 0);
  signal Net_10                  : std_logic;
  signal Net_11                  : std_logic;
  signal inbound_data_read       : std_logic;
  signal Net_13                  : std_logic;
  signal Net_14                  : std_logic_vector(31 downto 0);
  signal Net_15                  : std_logic;
  signal Net_16                  : std_logic;
  signal Net_17                  : std_logic_vector(111 downto 0);
  signal Net_18                  : std_logic;
  signal Net_19                  : std_logic;
  signal search_port_stalled_net : std_logic;
  signal Net_22                  : std_logic;
  signal outbound_info           : std_logic_vector(15 downto 0);
  signal inbound_proc_data       : std_logic_vector(63 downto 0);
  signal outbound_data           : std_logic_vector(63 downto 0);
  signal inbound_proc_data_full  : std_logic;
 
  component esoc_port_interface
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control          : in     std_logic;
      clk_rgmii_125m       : in     STD_LOGIC;
      clk_rgmii_25m        : in     STD_LOGIC;
      clk_rgmii_2m5        : in     STD_LOGIC;
      ctrl_address         : in     std_logic_vector(15 downto 0);
      ctrl_rd              : in     std_logic := '0';
      ctrl_rddata          : out    std_logic_vector(31 downto 0);
      ctrl_wait            : out    std_logic;
      ctrl_wr              : in     std_logic;
      ctrl_wrdata          : in     std_logic_vector(31 downto 0);
      inbound_data         : out    std_logic_vector(31 downto 0);
      inbound_data_full    : in     std_logic;
      inbound_data_write   : out    std_logic;
      inbound_header       : out    std_logic_vector(111 downto 0);
      inbound_header_write : out    std_logic;
      inbound_info         : out    std_logic_vector(31 downto 0);
      inbound_info_write   : out    std_logic;
      mac_mdc              : out    std_logic;
      mac_mdio             : inout  std_logic;
      outbound_data        : in     std_logic_vector(31 downto 0);
      outbound_data_read   : out    std_logic;
      outbound_info        : in     std_logic_vector(15 downto 0);
      outbound_info_empty  : in     std_logic;
      outbound_info_read   : out    std_logic;
      reset                : in     std_logic;
      rgmii_rxc            : in     std_logic;
      rgmii_rxctl          : in     std_logic;
      rgmii_rxd            : in     std_logic_vector(3 downto 0);
      rgmii_txc            : out    std_logic;
      rgmii_txctl          : out    std_logic;
      rgmii_txd            : out    std_logic_vector(3 downto 0));
  end component esoc_port_interface;
 
  component esoc_port_processor
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control          : in     std_logic;
      clk_data             : in     std_logic;
      clk_search           : in     std_logic;
      ctrl_address         : in     std_logic_vector(15 downto 0);
      ctrl_rd              : in     std_logic;
      ctrl_rddata          : out    std_logic_vector(31 downto 0);
      ctrl_wait            : out    std_logic;
      ctrl_wr              : in     std_logic;
      ctrl_wrdata          : in     std_logic_vector(31 downto 0);
      data                 : inout  std_logic_vector(63 downto 0);
      data_eof             : inout  std_logic;
      data_gnt_rd          : in     std_logic;
      data_gnt_wr          : in     std_logic;
      data_port_sel        : inout  std_logic_vector(esoc_port_count-1 downto 0);
      data_req             : out    std_logic;
      data_sof             : inout  std_logic;
      inbound_data         : in     std_logic_vector(63 downto 0);
      inbound_data_full    : in     std_logic;
      inbound_data_read    : out    std_logic;
      inbound_header       : in     std_logic_vector(111 downto 0);
      inbound_header_empty : in     std_logic;
      inbound_header_read  : out    std_logic;
      inbound_info         : in     std_logic_vector(31 downto 0);
      inbound_info_empty   : in     std_logic;
      inbound_info_read    : out    std_logic;
      outbound_data        : out    std_logic_vector(63 downto 0);
      outbound_data_full   : in     std_logic;
      outbound_data_write  : out    std_logic;
      outbound_info        : out    std_logic_vector(15 downto 0);
      outbound_info_write  : out    std_logic;
      reset                : in     std_logic;
      search_eof           : out    std_logic;
      search_gnt_wr        : in     std_logic;
      search_key           : out    std_logic_vector(63 downto 0);
      search_req           : out    std_logic;
      search_result        : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av     : in     std_logic;
      search_sof           : out    std_logic);
  end component esoc_port_processor;
 
  component esoc_port_storage
    port(
      clk_control               : in     std_logic;
      clk_data                  : in     std_logic;
      clk_search                : in     std_logic;
      inbound_port_data         : in     std_logic_vector(31 downto 0);
      inbound_port_data_full    : out    std_logic;
      inbound_port_data_write   : in     std_logic;
      inbound_port_header       : in     std_logic_vector(111 downto 0);
      inbound_port_header_write : in     std_logic;
      inbound_port_info         : in     std_logic_vector(31 downto 0);
      inbound_port_info_write   : in     std_logic;
      inbound_proc_data         : out    std_logic_vector(63 downto 0);
      inbound_proc_data_full    : out    std_logic;
      inbound_proc_data_read    : in     std_logic;
      inbound_proc_header       : out    std_logic_vector(111 downto 0);
      inbound_proc_header_empty : out    std_logic;
      inbound_proc_header_read  : in     std_logic;
      inbound_proc_info         : out    std_logic_vector(31 downto 0);
      inbound_proc_info_empty   : out    std_logic;
      inbound_proc_info_read    : in     std_logic;
      outbound_port_data        : out    std_logic_vector(31 downto 0);
      outbound_port_data_read   : in     std_logic;
      outbound_port_info        : out    std_logic_vector(15 downto 0);
      outbound_port_info_empty  : out    std_logic;
      outbound_port_info_read   : in     std_logic;
      outbound_proc_data        : in     std_logic_vector(63 downto 0);
      outbound_proc_data_full   : out    std_logic;
      outbound_proc_data_write  : in     std_logic;
      outbound_proc_info        : in     std_logic_vector(15 downto 0);
      outbound_proc_info_write  : in     std_logic;
      reset                     : in     std_logic);
  end component esoc_port_storage;
 
begin
  --External PHY Interface
  --Search engine 
  --interface
  --Port to Port 
  --data interface
  search_port_stalled <= search_port_stalled_net;
  u0: esoc_port_interface
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control          => clk_control,
      clk_rgmii_125m       => clk_rgmii_125m,
      clk_rgmii_25m        => clk_rgmii_25m,
      clk_rgmii_2m5        => clk_rgmii_2m5,
      ctrl_address         => ctrl_address,
      ctrl_rd              => ctrl_rd,
      ctrl_rddata          => ctrl_rddata,
      ctrl_wait            => ctrl_wait,
      ctrl_wr              => ctrl_wr,
      ctrl_wrdata          => ctrl_wrdata,
      inbound_data         => Net_1,
      inbound_data_full    => Net_2,
      inbound_data_write   => Net_0,
      inbound_header       => Net_5,
      inbound_header_write => Net_6,
      inbound_info         => Net_3,
      inbound_info_write   => Net_4,
      mac_mdc              => mdc,
      mac_mdio             => mdio,
      outbound_data        => Net_7,
      outbound_data_read   => Net_8,
      outbound_info        => Net_9,
      outbound_info_empty  => Net_11,
      outbound_info_read   => Net_10,
      reset                => reset,
      rgmii_rxc            => rgmii_rxc,
      rgmii_rxctl          => rgmii_rxctl,
      rgmii_rxd            => rgmii_rxd,
      rgmii_txc            => rgmii_txc,
      rgmii_txctl          => rgmii_txctl,
      rgmii_txd            => rgmii_txd);
 
  u1: esoc_port_processor
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control          => clk_control,
      clk_data             => clk_data,
      clk_search           => clk_search,
      ctrl_address         => ctrl_address,
      ctrl_rd              => ctrl_rd,
      ctrl_rddata          => ctrl_rddata,
      ctrl_wait            => ctrl_wait,
      ctrl_wr              => ctrl_wr,
      ctrl_wrdata          => ctrl_wrdata,
      data                 => data,
      data_eof             => data_eof,
      data_gnt_rd          => data_gnt_rd,
      data_gnt_wr          => data_gnt_wr,
      data_port_sel        => data_port_sel,
      data_req             => data_req,
      data_sof             => data_sof,
      inbound_data         => inbound_proc_data,
      inbound_data_full    => inbound_proc_data_full,
      inbound_data_read    => inbound_data_read,
      inbound_header       => Net_17,
      inbound_header_empty => Net_18,
      inbound_header_read  => Net_16,
      inbound_info         => Net_14,
      inbound_info_empty   => Net_15,
      inbound_info_read    => Net_13,
      outbound_data        => outbound_data,
      outbound_data_full   => search_port_stalled_net,
      outbound_data_write  => Net_19,
      outbound_info        => outbound_info,
      outbound_info_write  => Net_22,
      reset                => reset,
      search_eof           => search_eof,
      search_gnt_wr        => search_gnt_wr,
      search_key           => search_key,
      search_req           => search_req,
      search_result        => search_result,
      search_result_av     => search_result_av,
      search_sof           => search_sof);
 
  u3: esoc_port_storage
    port map(
      clk_control               => clk_control,
      clk_data                  => clk_data,
      clk_search                => clk_search,
      inbound_port_data         => Net_1,
      inbound_port_data_full    => Net_2,
      inbound_port_data_write   => Net_0,
      inbound_port_header       => Net_5,
      inbound_port_header_write => Net_6,
      inbound_port_info         => Net_3,
      inbound_port_info_write   => Net_4,
      inbound_proc_data         => inbound_proc_data,
      inbound_proc_data_full    => inbound_proc_data_full,
      inbound_proc_data_read    => inbound_data_read,
      inbound_proc_header       => Net_17,
      inbound_proc_header_empty => Net_18,
      inbound_proc_header_read  => Net_16,
      inbound_proc_info         => Net_14,
      inbound_proc_info_empty   => Net_15,
      inbound_proc_info_read    => Net_13,
      outbound_port_data        => Net_7,
      outbound_port_data_read   => Net_8,
      outbound_port_info        => Net_9,
      outbound_port_info_empty  => Net_11,
      outbound_port_info_read   => Net_10,
      outbound_proc_data        => outbound_data,
      outbound_proc_data_full   => search_port_stalled_net,
      outbound_proc_data_write  => Net_19,
      outbound_proc_info        => outbound_info,
      outbound_proc_info_write  => Net_22,
      reset                     => reset);
 
end architecture esoc_port ; -- of esoc_port
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port.vhd] - Blame information for rev 47

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- Ethernet Switch on Configurable Logic IP Core ----`
4			`---- ----`
5			`---- This file is part of the ESoCL project ----`
6			`---- http://www.opencores.org/cores/esoc/ ----`
7			`---- ----`
8			`---- Description: see design description ESoCL_dd_71022001.pdf ----`
9			`---- ----`
10			`---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----`
11			`---- and/or release bulleting ESoCL_rb_71022001.pdf ----`
12			`---- ----`
13			`---- Author(s): L.Maarsen ----`
14			`---- Bert Maarsen, lmaarsen@opencores.org ----`
15			`---- ----`
16			`--------------------------------------------------------------------------------`
17			`---- ----`
18			`---- Copyright (C) 2009 Authors and OPENCORES.ORG ----`
19			`---- ----`
20			`---- This source file may be used and distributed without ----`
21			`---- restriction provided that this copyright statement is not ----`
22			`---- removed from the file and that any derivative work contains ----`
23			`---- the original copyright notice and the associated disclaimer. ----`
24			`---- ----`
25			`---- This source file is free software; you can redistribute it ----`
26			`---- and/or modify it under the terms of the GNU Lesser General ----`
27			`---- Public License as published by the Free Software Foundation; ----`
28			`---- either version 2.1 of the License, or (at your option) any ----`
29			`---- later version. ----`
30			`---- ----`
31			`---- This source is distributed in the hope that it will be ----`
32			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
33			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
34			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
35			`---- details. ----`
36			`---- ----`
37			`---- You should have received a copy of the GNU Lesser General ----`
38			`---- Public License along with this source; if not, download it ----`
39			`---- from http://www.opencores.org/lgpl.shtml ----`
40			`---- ----`
41			`--------------------------------------------------------------------------------`
42			`-- Object : Entity work.esoc_port`
43			`-- Last modified : Mon Apr 14 12:48:46 2014.`
44			`--------------------------------------------------------------------------------`
45
46
47
48			`library ieee, std, work;`
49			`use ieee.std_logic_1164.all;`
50			`use std.textio.all;`
51			`use ieee.numeric_std.all;`
52			`use work.package_esoc_configuration.all;`
53
54			`entity esoc_port is`
55			`generic(`
56			`esoc_port_nr : integer := 0);`
57			`port(`
58			`clk_control : in std_logic;`
59			`clk_data : in std_logic;`
60			`clk_rgmii_125m : in STD_LOGIC;`
61			`clk_rgmii_25m : in STD_LOGIC;`
62			`clk_rgmii_2m5 : in STD_LOGIC;`
63			`clk_search : in std_logic;`
64			`ctrl_address : in std_logic_vector(15 downto 0);`
65			`ctrl_rd : in std_logic;`
66			`ctrl_rddata : out std_logic_vector(31 downto 0);`
67			`ctrl_wait : out std_logic;`
68			`ctrl_wr : in std_logic;`
69			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
70			`data : inout std_logic_vector(63 downto 0);`
71			`data_eof : inout std_logic;`
72			`data_gnt_rd : in std_logic;`
73			`data_gnt_wr : in std_logic;`
74			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
75			`data_req : out std_logic;`
76			`data_sof : inout std_logic;`
77			`mdc : out std_logic;`
78			`mdio : inout std_logic;`
79			`reset : in std_logic;`
80			`rgmii_rxc : in std_logic;`
81			`rgmii_rxctl : in std_logic;`
82			`rgmii_rxd : in std_logic_vector(3 downto 0);`
83			`rgmii_txc : out std_logic;`
84			`rgmii_txctl : out std_logic;`
85			`rgmii_txd : out std_logic_vector(3 downto 0);`
86			`search_eof : out std_logic;`
87			`search_gnt_wr : in std_logic;`
88			`search_key : out std_logic_vector(63 downto 0);`
89			`search_port_stalled : out std_logic;`
90			`search_req : out std_logic;`
91			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
92			`search_result_av : in std_logic;`
93			`search_sof : out std_logic);`
94			`end entity esoc_port;`
95
96			`--------------------------------------------------------------------------------`
97			`-- Object : Architecture work.esoc_port.esoc_port`
98			`-- Last modified : Mon Apr 14 12:48:46 2014.`
99			`--------------------------------------------------------------------------------`
100
101			`architecture esoc_port of esoc_port is`
102
103			`signal Net_0 : std_logic;`
104			`signal Net_1 : std_logic_vector(31 downto 0);`
105			`signal Net_2 : std_logic;`
106			`signal Net_3 : std_logic_vector(31 downto 0);`
107			`signal Net_4 : std_logic;`
108			`signal Net_5 : std_logic_vector(111 downto 0);`
109			`signal Net_6 : std_logic;`
110			`signal Net_7 : std_logic_vector(31 downto 0);`
111			`signal Net_8 : std_logic;`
112			`signal Net_9 : std_logic_vector(15 downto 0);`
113			`signal Net_10 : std_logic;`
114			`signal Net_11 : std_logic;`
115			`signal inbound_data_read : std_logic;`
116			`signal Net_13 : std_logic;`
117			`signal Net_14 : std_logic_vector(31 downto 0);`
118			`signal Net_15 : std_logic;`
119			`signal Net_16 : std_logic;`
120			`signal Net_17 : std_logic_vector(111 downto 0);`
121			`signal Net_18 : std_logic;`
122			`signal Net_19 : std_logic;`
123			`signal search_port_stalled_net : std_logic;`
124			`signal Net_22 : std_logic;`
125			`signal outbound_info : std_logic_vector(15 downto 0);`
126			`signal inbound_proc_data : std_logic_vector(63 downto 0);`
127			`signal outbound_data : std_logic_vector(63 downto 0);`
128			`signal inbound_proc_data_full : std_logic;`
129
130			`component esoc_port_interface`
131			`generic(`
132			`esoc_port_nr : integer := 0);`
133			`port(`
134			`clk_control : in std_logic;`
135			`clk_rgmii_125m : in STD_LOGIC;`
136			`clk_rgmii_25m : in STD_LOGIC;`
137			`clk_rgmii_2m5 : in STD_LOGIC;`
138			`ctrl_address : in std_logic_vector(15 downto 0);`
139			`ctrl_rd : in std_logic := '0';`
140			`ctrl_rddata : out std_logic_vector(31 downto 0);`
141			`ctrl_wait : out std_logic;`
142			`ctrl_wr : in std_logic;`
143			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
144			`inbound_data : out std_logic_vector(31 downto 0);`
145			`inbound_data_full : in std_logic;`
146			`inbound_data_write : out std_logic;`
147			`inbound_header : out std_logic_vector(111 downto 0);`
148			`inbound_header_write : out std_logic;`
149			`inbound_info : out std_logic_vector(31 downto 0);`
150			`inbound_info_write : out std_logic;`
151			`mac_mdc : out std_logic;`
152			`mac_mdio : inout std_logic;`
153			`outbound_data : in std_logic_vector(31 downto 0);`
154			`outbound_data_read : out std_logic;`
155			`outbound_info : in std_logic_vector(15 downto 0);`
156			`outbound_info_empty : in std_logic;`
157			`outbound_info_read : out std_logic;`
158			`reset : in std_logic;`
159			`rgmii_rxc : in std_logic;`
160			`rgmii_rxctl : in std_logic;`
161			`rgmii_rxd : in std_logic_vector(3 downto 0);`
162			`rgmii_txc : out std_logic;`
163			`rgmii_txctl : out std_logic;`
164			`rgmii_txd : out std_logic_vector(3 downto 0));`
165			`end component esoc_port_interface;`
166
167			`component esoc_port_processor`
168			`generic(`
169			`esoc_port_nr : integer := 0);`
170			`port(`
171			`clk_control : in std_logic;`
172			`clk_data : in std_logic;`
173			`clk_search : in std_logic;`
174			`ctrl_address : in std_logic_vector(15 downto 0);`
175			`ctrl_rd : in std_logic;`
176			`ctrl_rddata : out std_logic_vector(31 downto 0);`
177			`ctrl_wait : out std_logic;`
178			`ctrl_wr : in std_logic;`
179			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
180			`data : inout std_logic_vector(63 downto 0);`
181			`data_eof : inout std_logic;`
182			`data_gnt_rd : in std_logic;`
183			`data_gnt_wr : in std_logic;`
184			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
185			`data_req : out std_logic;`
186			`data_sof : inout std_logic;`
187			`inbound_data : in std_logic_vector(63 downto 0);`
188			`inbound_data_full : in std_logic;`
189			`inbound_data_read : out std_logic;`
190			`inbound_header : in std_logic_vector(111 downto 0);`
191			`inbound_header_empty : in std_logic;`
192			`inbound_header_read : out std_logic;`
193			`inbound_info : in std_logic_vector(31 downto 0);`
194			`inbound_info_empty : in std_logic;`
195			`inbound_info_read : out std_logic;`
196			`outbound_data : out std_logic_vector(63 downto 0);`
197			`outbound_data_full : in std_logic;`
198			`outbound_data_write : out std_logic;`
199			`outbound_info : out std_logic_vector(15 downto 0);`
200			`outbound_info_write : out std_logic;`
201			`reset : in std_logic;`
202			`search_eof : out std_logic;`
203			`search_gnt_wr : in std_logic;`
204			`search_key : out std_logic_vector(63 downto 0);`
205			`search_req : out std_logic;`
206			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
207			`search_result_av : in std_logic;`
208			`search_sof : out std_logic);`
209			`end component esoc_port_processor;`
210
211			`component esoc_port_storage`
212			`port(`
213			`clk_control : in std_logic;`
214			`clk_data : in std_logic;`
215			`clk_search : in std_logic;`
216			`inbound_port_data : in std_logic_vector(31 downto 0);`
217			`inbound_port_data_full : out std_logic;`
218			`inbound_port_data_write : in std_logic;`
219			`inbound_port_header : in std_logic_vector(111 downto 0);`
220			`inbound_port_header_write : in std_logic;`
221			`inbound_port_info : in std_logic_vector(31 downto 0);`
222			`inbound_port_info_write : in std_logic;`
223			`inbound_proc_data : out std_logic_vector(63 downto 0);`
224			`inbound_proc_data_full : out std_logic;`
225			`inbound_proc_data_read : in std_logic;`
226			`inbound_proc_header : out std_logic_vector(111 downto 0);`
227			`inbound_proc_header_empty : out std_logic;`
228			`inbound_proc_header_read : in std_logic;`
229			`inbound_proc_info : out std_logic_vector(31 downto 0);`
230			`inbound_proc_info_empty : out std_logic;`
231			`inbound_proc_info_read : in std_logic;`
232			`outbound_port_data : out std_logic_vector(31 downto 0);`
233			`outbound_port_data_read : in std_logic;`
234			`outbound_port_info : out std_logic_vector(15 downto 0);`
235			`outbound_port_info_empty : out std_logic;`
236			`outbound_port_info_read : in std_logic;`
237			`outbound_proc_data : in std_logic_vector(63 downto 0);`
238			`outbound_proc_data_full : out std_logic;`
239			`outbound_proc_data_write : in std_logic;`
240			`outbound_proc_info : in std_logic_vector(15 downto 0);`
241			`outbound_proc_info_write : in std_logic;`
242			`reset : in std_logic);`
243			`end component esoc_port_storage;`
244
245			`begin`
246			`--External PHY Interface`
247			`--Search engine`
248			`--interface`
249			`--Port to Port`
250			`--data interface`
251			`search_port_stalled <= search_port_stalled_net;`
252			`u0: esoc_port_interface`
253			`generic map(`
254			`esoc_port_nr => esoc_port_nr)`
255			`port map(`
256			`clk_control => clk_control,`
257			`clk_rgmii_125m => clk_rgmii_125m,`
258			`clk_rgmii_25m => clk_rgmii_25m,`
259			`clk_rgmii_2m5 => clk_rgmii_2m5,`
260			`ctrl_address => ctrl_address,`
261			`ctrl_rd => ctrl_rd,`
262			`ctrl_rddata => ctrl_rddata,`
263			`ctrl_wait => ctrl_wait,`
264			`ctrl_wr => ctrl_wr,`
265			`ctrl_wrdata => ctrl_wrdata,`
266			`inbound_data => Net_1,`
267			`inbound_data_full => Net_2,`
268			`inbound_data_write => Net_0,`
269			`inbound_header => Net_5,`
270			`inbound_header_write => Net_6,`
271			`inbound_info => Net_3,`
272			`inbound_info_write => Net_4,`
273			`mac_mdc => mdc,`
274			`mac_mdio => mdio,`
275			`outbound_data => Net_7,`
276			`outbound_data_read => Net_8,`
277			`outbound_info => Net_9,`
278			`outbound_info_empty => Net_11,`
279			`outbound_info_read => Net_10,`
280			`reset => reset,`
281			`rgmii_rxc => rgmii_rxc,`
282			`rgmii_rxctl => rgmii_rxctl,`
283			`rgmii_rxd => rgmii_rxd,`
284			`rgmii_txc => rgmii_txc,`
285			`rgmii_txctl => rgmii_txctl,`
286			`rgmii_txd => rgmii_txd);`
287
288			`u1: esoc_port_processor`
289			`generic map(`
290			`esoc_port_nr => esoc_port_nr)`
291			`port map(`
292			`clk_control => clk_control,`
293			`clk_data => clk_data,`
294			`clk_search => clk_search,`
295			`ctrl_address => ctrl_address,`
296			`ctrl_rd => ctrl_rd,`
297			`ctrl_rddata => ctrl_rddata,`
298			`ctrl_wait => ctrl_wait,`
299			`ctrl_wr => ctrl_wr,`
300			`ctrl_wrdata => ctrl_wrdata,`
301			`data => data,`
302			`data_eof => data_eof,`
303			`data_gnt_rd => data_gnt_rd,`
304			`data_gnt_wr => data_gnt_wr,`
305			`data_port_sel => data_port_sel,`
306			`data_req => data_req,`
307			`data_sof => data_sof,`
308			`inbound_data => inbound_proc_data,`
309			`inbound_data_full => inbound_proc_data_full,`
310			`inbound_data_read => inbound_data_read,`
311			`inbound_header => Net_17,`
312			`inbound_header_empty => Net_18,`
313			`inbound_header_read => Net_16,`
314			`inbound_info => Net_14,`
315			`inbound_info_empty => Net_15,`
316			`inbound_info_read => Net_13,`
317			`outbound_data => outbound_data,`
318			`outbound_data_full => search_port_stalled_net,`
319			`outbound_data_write => Net_19,`
320			`outbound_info => outbound_info,`
321			`outbound_info_write => Net_22,`
322			`reset => reset,`
323			`search_eof => search_eof,`
324			`search_gnt_wr => search_gnt_wr,`
325			`search_key => search_key,`
326			`search_req => search_req,`
327			`search_result => search_result,`
328			`search_result_av => search_result_av,`
329			`search_sof => search_sof);`
330
331			`u3: esoc_port_storage`
332			`port map(`
333			`clk_control => clk_control,`
334			`clk_data => clk_data,`
335			`clk_search => clk_search,`
336			`inbound_port_data => Net_1,`
337			`inbound_port_data_full => Net_2,`
338			`inbound_port_data_write => Net_0,`
339			`inbound_port_header => Net_5,`
340			`inbound_port_header_write => Net_6,`
341			`inbound_port_info => Net_3,`
342			`inbound_port_info_write => Net_4,`
343			`inbound_proc_data => inbound_proc_data,`
344			`inbound_proc_data_full => inbound_proc_data_full,`
345			`inbound_proc_data_read => inbound_data_read,`
346			`inbound_proc_header => Net_17,`
347			`inbound_proc_header_empty => Net_18,`
348			`inbound_proc_header_read => Net_16,`
349			`inbound_proc_info => Net_14,`
350			`inbound_proc_info_empty => Net_15,`
351			`inbound_proc_info_read => Net_13,`
352			`outbound_port_data => Net_7,`
353			`outbound_port_data_read => Net_8,`
354			`outbound_port_info => Net_9,`
355			`outbound_port_info_empty => Net_11,`
356			`outbound_port_info_read => Net_10,`
357			`outbound_proc_data => outbound_data,`
358			`outbound_proc_data_full => search_port_stalled_net,`
359			`outbound_proc_data_write => Net_19,`
360			`outbound_proc_info => outbound_info,`
361			`outbound_proc_info_write => Net_22,`
362			`reset => reset);`
363
364			`end architecture esoc_port ; -- of esoc_port`
365