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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port.vhd] - Blame information for rev 55

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--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : S212065
-- User name     : df768
-- Time stamp    : Tue Aug 19 08:05:18 2014
--
-- Designed by   : L.Maarsen
-- Company       : LogiXA
-- Project info  : eSoC
--
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_port
-- Last modified : Mon Apr 14 12:48:46 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_port is
  generic(
    esoc_port_nr : integer := 0);
  port(
    clk_control         : in     std_logic;
    clk_data            : in     std_logic;
    clk_rgmii_125m      : in     STD_LOGIC;
    clk_rgmii_25m       : in     STD_LOGIC;
    clk_rgmii_2m5       : in     STD_LOGIC;
    clk_search          : in     std_logic;
    ctrl_address        : in     std_logic_vector(15 downto 0);
    ctrl_rd             : in     std_logic;
    ctrl_rddata         : out    std_logic_vector(31 downto 0);
    ctrl_wait           : out    std_logic;
    ctrl_wr             : in     std_logic;
    ctrl_wrdata         : in     std_logic_vector(31 downto 0);
    data                : inout  std_logic_vector(63 downto 0);
    data_eof            : inout  std_logic;
    data_gnt_rd         : in     std_logic;
    data_gnt_wr         : in     std_logic;
    data_port_sel       : inout  std_logic_vector(esoc_port_count-1 downto 0);
    data_req            : out    std_logic;
    data_sof            : inout  std_logic;
    mdc                 : out    std_logic;
    mdio                : inout  std_logic;
    reset               : in     std_logic;
    rgmii_rxc           : in     std_logic;
    rgmii_rxctl         : in     std_logic;
    rgmii_rxd           : in     std_logic_vector(3 downto 0);
    rgmii_txc           : out    std_logic;
    rgmii_txctl         : out    std_logic;
    rgmii_txd           : out    std_logic_vector(3 downto 0);
    search_eof          : out    std_logic;
    search_gnt_wr       : in     std_logic;
    search_key          : out    std_logic_vector(63 downto 0);
    search_port_stalled : out    std_logic;
    search_req          : out    std_logic;
    search_result       : in     std_logic_vector(esoc_port_count-1 downto 0);
    search_result_av    : in     std_logic;
    search_sof          : out    std_logic);
end entity esoc_port;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_port.esoc_port
-- Last modified : Mon Apr 14 12:48:46 2014.
--------------------------------------------------------------------------------
 
architecture esoc_port of esoc_port is
 
  signal Net_0                   : std_logic;
  signal Net_1                   : std_logic_vector(31 downto 0);
  signal Net_2                   : std_logic;
  signal Net_3                   : std_logic_vector(31 downto 0);
  signal Net_4                   : std_logic;
  signal Net_5                   : std_logic_vector(111 downto 0);
  signal Net_6                   : std_logic;
  signal Net_7                   : std_logic_vector(31 downto 0);
  signal Net_8                   : std_logic;
  signal Net_9                   : std_logic_vector(15 downto 0);
  signal Net_10                  : std_logic;
  signal Net_11                  : std_logic;
  signal inbound_data_read       : std_logic;
  signal Net_13                  : std_logic;
  signal Net_14                  : std_logic_vector(31 downto 0);
  signal Net_15                  : std_logic;
  signal Net_16                  : std_logic;
  signal Net_17                  : std_logic_vector(111 downto 0);
  signal Net_18                  : std_logic;
  signal Net_19                  : std_logic;
  signal search_port_stalled_net : std_logic;
  signal Net_22                  : std_logic;
  signal outbound_info           : std_logic_vector(15 downto 0);
  signal inbound_proc_data       : std_logic_vector(63 downto 0);
  signal outbound_data           : std_logic_vector(63 downto 0);
  signal inbound_proc_data_full  : std_logic;
 
  component esoc_port_interface
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control          : in     std_logic;
      clk_rgmii_125m       : in     STD_LOGIC;
      clk_rgmii_25m        : in     STD_LOGIC;
      clk_rgmii_2m5        : in     STD_LOGIC;
      ctrl_address         : in     std_logic_vector(15 downto 0);
      ctrl_rd              : in     std_logic := '0';
      ctrl_rddata          : out    std_logic_vector(31 downto 0);
      ctrl_wait            : out    std_logic;
      ctrl_wr              : in     std_logic;
      ctrl_wrdata          : in     std_logic_vector(31 downto 0);
      inbound_data         : out    std_logic_vector(31 downto 0);
      inbound_data_full    : in     std_logic;
      inbound_data_write   : out    std_logic;
      inbound_header       : out    std_logic_vector(111 downto 0);
      inbound_header_write : out    std_logic;
      inbound_info         : out    std_logic_vector(31 downto 0);
      inbound_info_write   : out    std_logic;
      mac_mdc              : out    std_logic;
      mac_mdio             : inout  std_logic;
      outbound_data        : in     std_logic_vector(31 downto 0);
      outbound_data_read   : out    std_logic;
      outbound_info        : in     std_logic_vector(15 downto 0);
      outbound_info_empty  : in     std_logic;
      outbound_info_read   : out    std_logic;
      reset                : in     std_logic;
      rgmii_rxc            : in     std_logic;
      rgmii_rxctl          : in     std_logic;
      rgmii_rxd            : in     std_logic_vector(3 downto 0);
      rgmii_txc            : out    std_logic;
      rgmii_txctl          : out    std_logic;
      rgmii_txd            : out    std_logic_vector(3 downto 0));
  end component esoc_port_interface;
 
  component esoc_port_processor
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control          : in     std_logic;
      clk_data             : in     std_logic;
      clk_search           : in     std_logic;
      ctrl_address         : in     std_logic_vector(15 downto 0);
      ctrl_rd              : in     std_logic;
      ctrl_rddata          : out    std_logic_vector(31 downto 0);
      ctrl_wait            : out    std_logic;
      ctrl_wr              : in     std_logic;
      ctrl_wrdata          : in     std_logic_vector(31 downto 0);
      data                 : inout  std_logic_vector(63 downto 0);
      data_eof             : inout  std_logic;
      data_gnt_rd          : in     std_logic;
      data_gnt_wr          : in     std_logic;
      data_port_sel        : inout  std_logic_vector(esoc_port_count-1 downto 0);
      data_req             : out    std_logic;
      data_sof             : inout  std_logic;
      inbound_data         : in     std_logic_vector(63 downto 0);
      inbound_data_full    : in     std_logic;
      inbound_data_read    : out    std_logic;
      inbound_header       : in     std_logic_vector(111 downto 0);
      inbound_header_empty : in     std_logic;
      inbound_header_read  : out    std_logic;
      inbound_info         : in     std_logic_vector(31 downto 0);
      inbound_info_empty   : in     std_logic;
      inbound_info_read    : out    std_logic;
      outbound_data        : out    std_logic_vector(63 downto 0);
      outbound_data_full   : in     std_logic;
      outbound_data_write  : out    std_logic;
      outbound_info        : out    std_logic_vector(15 downto 0);
      outbound_info_write  : out    std_logic;
      reset                : in     std_logic;
      search_eof           : out    std_logic;
      search_gnt_wr        : in     std_logic;
      search_key           : out    std_logic_vector(63 downto 0);
      search_req           : out    std_logic;
      search_result        : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av     : in     std_logic;
      search_sof           : out    std_logic);
  end component esoc_port_processor;
 
  component esoc_port_storage
    port(
      clk_control               : in     std_logic;
      clk_data                  : in     std_logic;
      clk_search                : in     std_logic;
      inbound_port_data         : in     std_logic_vector(31 downto 0);
      inbound_port_data_full    : out    std_logic;
      inbound_port_data_write   : in     std_logic;
      inbound_port_header       : in     std_logic_vector(111 downto 0);
      inbound_port_header_write : in     std_logic;
      inbound_port_info         : in     std_logic_vector(31 downto 0);
      inbound_port_info_write   : in     std_logic;
      inbound_proc_data         : out    std_logic_vector(63 downto 0);
      inbound_proc_data_full    : out    std_logic;
      inbound_proc_data_read    : in     std_logic;
      inbound_proc_header       : out    std_logic_vector(111 downto 0);
      inbound_proc_header_empty : out    std_logic;
      inbound_proc_header_read  : in     std_logic;
      inbound_proc_info         : out    std_logic_vector(31 downto 0);
      inbound_proc_info_empty   : out    std_logic;
      inbound_proc_info_read    : in     std_logic;
      outbound_port_data        : out    std_logic_vector(31 downto 0);
      outbound_port_data_read   : in     std_logic;
      outbound_port_info        : out    std_logic_vector(15 downto 0);
      outbound_port_info_empty  : out    std_logic;
      outbound_port_info_read   : in     std_logic;
      outbound_proc_data        : in     std_logic_vector(63 downto 0);
      outbound_proc_data_full   : out    std_logic;
      outbound_proc_data_write  : in     std_logic;
      outbound_proc_info        : in     std_logic_vector(15 downto 0);
      outbound_proc_info_write  : in     std_logic;
      reset                     : in     std_logic);
  end component esoc_port_storage;
 
begin
  --External PHY Interface
  --Search engine 
  --interface
  --Port to Port 
  --data interface
  search_port_stalled <= search_port_stalled_net;
  u0: esoc_port_interface
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control          => clk_control,
      clk_rgmii_125m       => clk_rgmii_125m,
      clk_rgmii_25m        => clk_rgmii_25m,
      clk_rgmii_2m5        => clk_rgmii_2m5,
      ctrl_address         => ctrl_address,
      ctrl_rd              => ctrl_rd,
      ctrl_rddata          => ctrl_rddata,
      ctrl_wait            => ctrl_wait,
      ctrl_wr              => ctrl_wr,
      ctrl_wrdata          => ctrl_wrdata,
      inbound_data         => Net_1,
      inbound_data_full    => Net_2,
      inbound_data_write   => Net_0,
      inbound_header       => Net_5,
      inbound_header_write => Net_6,
      inbound_info         => Net_3,
      inbound_info_write   => Net_4,
      mac_mdc              => mdc,
      mac_mdio             => mdio,
      outbound_data        => Net_7,
      outbound_data_read   => Net_8,
      outbound_info        => Net_9,
      outbound_info_empty  => Net_11,
      outbound_info_read   => Net_10,
      reset                => reset,
      rgmii_rxc            => rgmii_rxc,
      rgmii_rxctl          => rgmii_rxctl,
      rgmii_rxd            => rgmii_rxd,
      rgmii_txc            => rgmii_txc,
      rgmii_txctl          => rgmii_txctl,
      rgmii_txd            => rgmii_txd);
 
  u1: esoc_port_processor
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control          => clk_control,
      clk_data             => clk_data,
      clk_search           => clk_search,
      ctrl_address         => ctrl_address,
      ctrl_rd              => ctrl_rd,
      ctrl_rddata          => ctrl_rddata,
      ctrl_wait            => ctrl_wait,
      ctrl_wr              => ctrl_wr,
      ctrl_wrdata          => ctrl_wrdata,
      data                 => data,
      data_eof             => data_eof,
      data_gnt_rd          => data_gnt_rd,
      data_gnt_wr          => data_gnt_wr,
      data_port_sel        => data_port_sel,
      data_req             => data_req,
      data_sof             => data_sof,
      inbound_data         => inbound_proc_data,
      inbound_data_full    => inbound_proc_data_full,
      inbound_data_read    => inbound_data_read,
      inbound_header       => Net_17,
      inbound_header_empty => Net_18,
      inbound_header_read  => Net_16,
      inbound_info         => Net_14,
      inbound_info_empty   => Net_15,
      inbound_info_read    => Net_13,
      outbound_data        => outbound_data,
      outbound_data_full   => search_port_stalled_net,
      outbound_data_write  => Net_19,
      outbound_info        => outbound_info,
      outbound_info_write  => Net_22,
      reset                => reset,
      search_eof           => search_eof,
      search_gnt_wr        => search_gnt_wr,
      search_key           => search_key,
      search_req           => search_req,
      search_result        => search_result,
      search_result_av     => search_result_av,
      search_sof           => search_sof);
 
  u3: esoc_port_storage
    port map(
      clk_control               => clk_control,
      clk_data                  => clk_data,
      clk_search                => clk_search,
      inbound_port_data         => Net_1,
      inbound_port_data_full    => Net_2,
      inbound_port_data_write   => Net_0,
      inbound_port_header       => Net_5,
      inbound_port_header_write => Net_6,
      inbound_port_info         => Net_3,
      inbound_port_info_write   => Net_4,
      inbound_proc_data         => inbound_proc_data,
      inbound_proc_data_full    => inbound_proc_data_full,
      inbound_proc_data_read    => inbound_data_read,
      inbound_proc_header       => Net_17,
      inbound_proc_header_empty => Net_18,
      inbound_proc_header_read  => Net_16,
      inbound_proc_info         => Net_14,
      inbound_proc_info_empty   => Net_15,
      inbound_proc_info_read    => Net_13,
      outbound_port_data        => Net_7,
      outbound_port_data_read   => Net_8,
      outbound_port_info        => Net_9,
      outbound_port_info_empty  => Net_11,
      outbound_port_info_read   => Net_10,
      outbound_proc_data        => outbound_data,
      outbound_proc_data_full   => search_port_stalled_net,
      outbound_proc_data_write  => Net_19,
      outbound_proc_info        => outbound_info,
      outbound_proc_info_write  => Net_22,
      reset                     => reset);
 
end architecture esoc_port ; -- of esoc_port
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port.vhd] - Blame information for rev 55

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2	53	lmaarsen	`--`
3			`-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.`
4			`--`
5			`-- Ease library : work`
6			`-- HDL library : work`
7			`-- Host name : S212065`
8			`-- User name : df768`
9			`-- Time stamp : Tue Aug 19 08:05:18 2014`
10			`--`
11			`-- Designed by : L.Maarsen`
12			`-- Company : LogiXA`
13			`-- Project info : eSoC`
14			`--`
15	42	lmaarsen	`--------------------------------------------------------------------------------`
16	53	lmaarsen
17	42	lmaarsen	`--------------------------------------------------------------------------------`
18			`-- Object : Entity work.esoc_port`
19			`-- Last modified : Mon Apr 14 12:48:46 2014.`
20			`--------------------------------------------------------------------------------`
21
22
23
24			`library ieee, std, work;`
25			`use ieee.std_logic_1164.all;`
26			`use std.textio.all;`
27			`use ieee.numeric_std.all;`
28			`use work.package_esoc_configuration.all;`
29
30			`entity esoc_port is`
31			`generic(`
32			`esoc_port_nr : integer := 0);`
33			`port(`
34			`clk_control : in std_logic;`
35			`clk_data : in std_logic;`
36			`clk_rgmii_125m : in STD_LOGIC;`
37			`clk_rgmii_25m : in STD_LOGIC;`
38			`clk_rgmii_2m5 : in STD_LOGIC;`
39			`clk_search : in std_logic;`
40			`ctrl_address : in std_logic_vector(15 downto 0);`
41			`ctrl_rd : in std_logic;`
42			`ctrl_rddata : out std_logic_vector(31 downto 0);`
43			`ctrl_wait : out std_logic;`
44			`ctrl_wr : in std_logic;`
45			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
46			`data : inout std_logic_vector(63 downto 0);`
47			`data_eof : inout std_logic;`
48			`data_gnt_rd : in std_logic;`
49			`data_gnt_wr : in std_logic;`
50			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
51			`data_req : out std_logic;`
52			`data_sof : inout std_logic;`
53			`mdc : out std_logic;`
54			`mdio : inout std_logic;`
55			`reset : in std_logic;`
56			`rgmii_rxc : in std_logic;`
57			`rgmii_rxctl : in std_logic;`
58			`rgmii_rxd : in std_logic_vector(3 downto 0);`
59			`rgmii_txc : out std_logic;`
60			`rgmii_txctl : out std_logic;`
61			`rgmii_txd : out std_logic_vector(3 downto 0);`
62			`search_eof : out std_logic;`
63			`search_gnt_wr : in std_logic;`
64			`search_key : out std_logic_vector(63 downto 0);`
65			`search_port_stalled : out std_logic;`
66			`search_req : out std_logic;`
67			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
68			`search_result_av : in std_logic;`
69			`search_sof : out std_logic);`
70			`end entity esoc_port;`
71
72			`--------------------------------------------------------------------------------`
73			`-- Object : Architecture work.esoc_port.esoc_port`
74			`-- Last modified : Mon Apr 14 12:48:46 2014.`
75			`--------------------------------------------------------------------------------`
76
77			`architecture esoc_port of esoc_port is`
78
79			`signal Net_0 : std_logic;`
80			`signal Net_1 : std_logic_vector(31 downto 0);`
81			`signal Net_2 : std_logic;`
82			`signal Net_3 : std_logic_vector(31 downto 0);`
83			`signal Net_4 : std_logic;`
84			`signal Net_5 : std_logic_vector(111 downto 0);`
85			`signal Net_6 : std_logic;`
86			`signal Net_7 : std_logic_vector(31 downto 0);`
87			`signal Net_8 : std_logic;`
88			`signal Net_9 : std_logic_vector(15 downto 0);`
89			`signal Net_10 : std_logic;`
90			`signal Net_11 : std_logic;`
91			`signal inbound_data_read : std_logic;`
92			`signal Net_13 : std_logic;`
93			`signal Net_14 : std_logic_vector(31 downto 0);`
94			`signal Net_15 : std_logic;`
95			`signal Net_16 : std_logic;`
96			`signal Net_17 : std_logic_vector(111 downto 0);`
97			`signal Net_18 : std_logic;`
98			`signal Net_19 : std_logic;`
99			`signal search_port_stalled_net : std_logic;`
100			`signal Net_22 : std_logic;`
101			`signal outbound_info : std_logic_vector(15 downto 0);`
102			`signal inbound_proc_data : std_logic_vector(63 downto 0);`
103			`signal outbound_data : std_logic_vector(63 downto 0);`
104			`signal inbound_proc_data_full : std_logic;`
105
106			`component esoc_port_interface`
107			`generic(`
108			`esoc_port_nr : integer := 0);`
109			`port(`
110			`clk_control : in std_logic;`
111			`clk_rgmii_125m : in STD_LOGIC;`
112			`clk_rgmii_25m : in STD_LOGIC;`
113			`clk_rgmii_2m5 : in STD_LOGIC;`
114			`ctrl_address : in std_logic_vector(15 downto 0);`
115			`ctrl_rd : in std_logic := '0';`
116			`ctrl_rddata : out std_logic_vector(31 downto 0);`
117			`ctrl_wait : out std_logic;`
118			`ctrl_wr : in std_logic;`
119			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
120			`inbound_data : out std_logic_vector(31 downto 0);`
121			`inbound_data_full : in std_logic;`
122			`inbound_data_write : out std_logic;`
123			`inbound_header : out std_logic_vector(111 downto 0);`
124			`inbound_header_write : out std_logic;`
125			`inbound_info : out std_logic_vector(31 downto 0);`
126			`inbound_info_write : out std_logic;`
127			`mac_mdc : out std_logic;`
128			`mac_mdio : inout std_logic;`
129			`outbound_data : in std_logic_vector(31 downto 0);`
130			`outbound_data_read : out std_logic;`
131			`outbound_info : in std_logic_vector(15 downto 0);`
132			`outbound_info_empty : in std_logic;`
133			`outbound_info_read : out std_logic;`
134			`reset : in std_logic;`
135			`rgmii_rxc : in std_logic;`
136			`rgmii_rxctl : in std_logic;`
137			`rgmii_rxd : in std_logic_vector(3 downto 0);`
138			`rgmii_txc : out std_logic;`
139			`rgmii_txctl : out std_logic;`
140			`rgmii_txd : out std_logic_vector(3 downto 0));`
141			`end component esoc_port_interface;`
142
143			`component esoc_port_processor`
144			`generic(`
145			`esoc_port_nr : integer := 0);`
146			`port(`
147			`clk_control : in std_logic;`
148			`clk_data : in std_logic;`
149			`clk_search : in std_logic;`
150			`ctrl_address : in std_logic_vector(15 downto 0);`
151			`ctrl_rd : in std_logic;`
152			`ctrl_rddata : out std_logic_vector(31 downto 0);`
153			`ctrl_wait : out std_logic;`
154			`ctrl_wr : in std_logic;`
155			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
156			`data : inout std_logic_vector(63 downto 0);`
157			`data_eof : inout std_logic;`
158			`data_gnt_rd : in std_logic;`
159			`data_gnt_wr : in std_logic;`
160			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
161			`data_req : out std_logic;`
162			`data_sof : inout std_logic;`
163			`inbound_data : in std_logic_vector(63 downto 0);`
164			`inbound_data_full : in std_logic;`
165			`inbound_data_read : out std_logic;`
166			`inbound_header : in std_logic_vector(111 downto 0);`
167			`inbound_header_empty : in std_logic;`
168			`inbound_header_read : out std_logic;`
169			`inbound_info : in std_logic_vector(31 downto 0);`
170			`inbound_info_empty : in std_logic;`
171			`inbound_info_read : out std_logic;`
172			`outbound_data : out std_logic_vector(63 downto 0);`
173			`outbound_data_full : in std_logic;`
174			`outbound_data_write : out std_logic;`
175			`outbound_info : out std_logic_vector(15 downto 0);`
176			`outbound_info_write : out std_logic;`
177			`reset : in std_logic;`
178			`search_eof : out std_logic;`
179			`search_gnt_wr : in std_logic;`
180			`search_key : out std_logic_vector(63 downto 0);`
181			`search_req : out std_logic;`
182			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
183			`search_result_av : in std_logic;`
184			`search_sof : out std_logic);`
185			`end component esoc_port_processor;`
186
187			`component esoc_port_storage`
188			`port(`
189			`clk_control : in std_logic;`
190			`clk_data : in std_logic;`
191			`clk_search : in std_logic;`
192			`inbound_port_data : in std_logic_vector(31 downto 0);`
193			`inbound_port_data_full : out std_logic;`
194			`inbound_port_data_write : in std_logic;`
195			`inbound_port_header : in std_logic_vector(111 downto 0);`
196			`inbound_port_header_write : in std_logic;`
197			`inbound_port_info : in std_logic_vector(31 downto 0);`
198			`inbound_port_info_write : in std_logic;`
199			`inbound_proc_data : out std_logic_vector(63 downto 0);`
200			`inbound_proc_data_full : out std_logic;`
201			`inbound_proc_data_read : in std_logic;`
202			`inbound_proc_header : out std_logic_vector(111 downto 0);`
203			`inbound_proc_header_empty : out std_logic;`
204			`inbound_proc_header_read : in std_logic;`
205			`inbound_proc_info : out std_logic_vector(31 downto 0);`
206			`inbound_proc_info_empty : out std_logic;`
207			`inbound_proc_info_read : in std_logic;`
208			`outbound_port_data : out std_logic_vector(31 downto 0);`
209			`outbound_port_data_read : in std_logic;`
210			`outbound_port_info : out std_logic_vector(15 downto 0);`
211			`outbound_port_info_empty : out std_logic;`
212			`outbound_port_info_read : in std_logic;`
213			`outbound_proc_data : in std_logic_vector(63 downto 0);`
214			`outbound_proc_data_full : out std_logic;`
215			`outbound_proc_data_write : in std_logic;`
216			`outbound_proc_info : in std_logic_vector(15 downto 0);`
217			`outbound_proc_info_write : in std_logic;`
218			`reset : in std_logic);`
219			`end component esoc_port_storage;`
220
221			`begin`
222			`--External PHY Interface`
223			`--Search engine`
224			`--interface`
225			`--Port to Port`
226			`--data interface`
227			`search_port_stalled <= search_port_stalled_net;`
228			`u0: esoc_port_interface`
229			`generic map(`
230			`esoc_port_nr => esoc_port_nr)`
231			`port map(`
232			`clk_control => clk_control,`
233			`clk_rgmii_125m => clk_rgmii_125m,`
234			`clk_rgmii_25m => clk_rgmii_25m,`
235			`clk_rgmii_2m5 => clk_rgmii_2m5,`
236			`ctrl_address => ctrl_address,`
237			`ctrl_rd => ctrl_rd,`
238			`ctrl_rddata => ctrl_rddata,`
239			`ctrl_wait => ctrl_wait,`
240			`ctrl_wr => ctrl_wr,`
241			`ctrl_wrdata => ctrl_wrdata,`
242			`inbound_data => Net_1,`
243			`inbound_data_full => Net_2,`
244			`inbound_data_write => Net_0,`
245			`inbound_header => Net_5,`
246			`inbound_header_write => Net_6,`
247			`inbound_info => Net_3,`
248			`inbound_info_write => Net_4,`
249			`mac_mdc => mdc,`
250			`mac_mdio => mdio,`
251			`outbound_data => Net_7,`
252			`outbound_data_read => Net_8,`
253			`outbound_info => Net_9,`
254			`outbound_info_empty => Net_11,`
255			`outbound_info_read => Net_10,`
256			`reset => reset,`
257			`rgmii_rxc => rgmii_rxc,`
258			`rgmii_rxctl => rgmii_rxctl,`
259			`rgmii_rxd => rgmii_rxd,`
260			`rgmii_txc => rgmii_txc,`
261			`rgmii_txctl => rgmii_txctl,`
262			`rgmii_txd => rgmii_txd);`
263
264			`u1: esoc_port_processor`
265			`generic map(`
266			`esoc_port_nr => esoc_port_nr)`
267			`port map(`
268			`clk_control => clk_control,`
269			`clk_data => clk_data,`
270			`clk_search => clk_search,`
271			`ctrl_address => ctrl_address,`
272			`ctrl_rd => ctrl_rd,`
273			`ctrl_rddata => ctrl_rddata,`
274			`ctrl_wait => ctrl_wait,`
275			`ctrl_wr => ctrl_wr,`
276			`ctrl_wrdata => ctrl_wrdata,`
277			`data => data,`
278			`data_eof => data_eof,`
279			`data_gnt_rd => data_gnt_rd,`
280			`data_gnt_wr => data_gnt_wr,`
281			`data_port_sel => data_port_sel,`
282			`data_req => data_req,`
283			`data_sof => data_sof,`
284			`inbound_data => inbound_proc_data,`
285			`inbound_data_full => inbound_proc_data_full,`
286			`inbound_data_read => inbound_data_read,`
287			`inbound_header => Net_17,`
288			`inbound_header_empty => Net_18,`
289			`inbound_header_read => Net_16,`
290			`inbound_info => Net_14,`
291			`inbound_info_empty => Net_15,`
292			`inbound_info_read => Net_13,`
293			`outbound_data => outbound_data,`
294			`outbound_data_full => search_port_stalled_net,`
295			`outbound_data_write => Net_19,`
296			`outbound_info => outbound_info,`
297			`outbound_info_write => Net_22,`
298			`reset => reset,`
299			`search_eof => search_eof,`
300			`search_gnt_wr => search_gnt_wr,`
301			`search_key => search_key,`
302			`search_req => search_req,`
303			`search_result => search_result,`
304			`search_result_av => search_result_av,`
305			`search_sof => search_sof);`
306
307			`u3: esoc_port_storage`
308			`port map(`
309			`clk_control => clk_control,`
310			`clk_data => clk_data,`
311			`clk_search => clk_search,`
312			`inbound_port_data => Net_1,`
313			`inbound_port_data_full => Net_2,`
314			`inbound_port_data_write => Net_0,`
315			`inbound_port_header => Net_5,`
316			`inbound_port_header_write => Net_6,`
317			`inbound_port_info => Net_3,`
318			`inbound_port_info_write => Net_4,`
319			`inbound_proc_data => inbound_proc_data,`
320			`inbound_proc_data_full => inbound_proc_data_full,`
321			`inbound_proc_data_read => inbound_data_read,`
322			`inbound_proc_header => Net_17,`
323			`inbound_proc_header_empty => Net_18,`
324			`inbound_proc_header_read => Net_16,`
325			`inbound_proc_info => Net_14,`
326			`inbound_proc_info_empty => Net_15,`
327			`inbound_proc_info_read => Net_13,`
328			`outbound_port_data => Net_7,`
329			`outbound_port_data_read => Net_8,`
330			`outbound_port_info => Net_9,`
331			`outbound_port_info_empty => Net_11,`
332			`outbound_port_info_read => Net_10,`
333			`outbound_proc_data => outbound_data,`
334			`outbound_proc_data_full => search_port_stalled_net,`
335			`outbound_proc_data_write => Net_19,`
336			`outbound_proc_info => outbound_info,`
337			`outbound_proc_info_write => Net_22,`
338			`reset => reset);`
339
340			`end architecture esoc_port ; -- of esoc_port`
341