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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_interface.vhd] - Blame information for rev 55

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--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : S212065
-- User name     : df768
-- Time stamp    : Tue Aug 19 08:05:18 2014
--
-- Designed by   : L.Maarsen
-- Company       : LogiXA
-- Project info  : eSoC
--
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_port_interface
-- Last modified : Mon Apr 14 12:51:18 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_port_interface is
  generic(
    esoc_port_nr : integer := 0);
  port(
    clk_control          : in     std_logic;
    clk_rgmii_125m       : in     STD_LOGIC;
    clk_rgmii_25m        : in     STD_LOGIC;
    clk_rgmii_2m5        : in     STD_LOGIC;
    ctrl_address         : in     std_logic_vector(15 downto 0);
    ctrl_rd              : in     std_logic := '0';
    ctrl_rddata          : out    std_logic_vector(31 downto 0);
    ctrl_wait            : out    std_logic;
    ctrl_wr              : in     std_logic;
    ctrl_wrdata          : in     std_logic_vector(31 downto 0);
    inbound_data         : out    std_logic_vector(31 downto 0);
    inbound_data_full    : in     std_logic;
    inbound_data_write   : out    std_logic;
    inbound_header       : out    std_logic_vector(111 downto 0);
    inbound_header_write : out    std_logic;
    inbound_info         : out    std_logic_vector(31 downto 0);
    inbound_info_write   : out    std_logic;
    mac_mdc              : out    std_logic;
    mac_mdio             : inout  std_logic;
    outbound_data        : in     std_logic_vector(31 downto 0);
    outbound_data_read   : out    std_logic;
    outbound_info        : in     std_logic_vector(15 downto 0);
    outbound_info_empty  : in     std_logic;
    outbound_info_read   : out    std_logic;
    reset                : in     std_logic;
    rgmii_rxc            : in     std_logic;
    rgmii_rxctl          : in     std_logic;
    rgmii_rxd            : in     std_logic_vector(3 downto 0);
    rgmii_txc            : out    std_logic;
    rgmii_txctl          : out    std_logic;
    rgmii_txd            : out    std_logic_vector(3 downto 0));
end entity esoc_port_interface;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_port_interface.structure
-- Last modified : Mon Apr 14 12:51:18 2014.
--------------------------------------------------------------------------------
 
architecture structure of esoc_port_interface is
 
  signal ctrl_bus_enable : STD_LOGIC;
  signal clk_rgmii       : STD_LOGIC;
  signal mac_rd          : STD_LOGIC;
  signal mac_address     : STD_LOGIC_VECTOR(7 downto 0);
  signal mdc             : STD_LOGIC;
  signal mdio_out        : STD_LOGIC;
  signal mdio_in         : STD_LOGIC;
  signal mdio_oen        : STD_LOGIC;
  signal mac_wait        : STD_LOGIC;
  signal mac_rddata      : STD_LOGIC_VECTOR(31 downto 0);
  signal mac_wrdata      : STD_LOGIC_VECTOR(31 downto 0);
  signal mac_wr          : STD_LOGIC;
  signal xon_gen         : STD_LOGIC;
  signal xoff_gen        : STD_LOGIC;
  signal magic_wakeup    : STD_LOGIC;
  signal magic_sleep_n   : STD_LOGIC := '1';
  signal set_1000        : STD_LOGIC := '0';
  signal set_10          : STD_LOGIC := '0'; -- '0'
  signal eth_mode        : STD_LOGIC;
  signal ena_10          : STD_LOGIC;
  signal ff_tx_sop       : STD_LOGIC;
  signal ff_tx_eop       : STD_LOGIC;
  signal ff_tx_rdy       : STD_LOGIC;
  signal ff_tx_wren      : STD_LOGIC;
  signal ff_tx_data      : STD_LOGIC_VECTOR(31 downto 0);
  signal ff_tx_mod       : STD_LOGIC_VECTOR(1 downto 0);
  signal ff_tx_err       : STD_LOGIC;
  signal ff_tx_crc_fwd   : STD_LOGIC;
  signal tx_ff_uflow     : STD_LOGIC;
  signal ff_tx_a_full    : STD_LOGIC;
  signal ff_tx_a_empty   : STD_LOGIC;
  signal ff_tx_septy     : STD_LOGIC;
  signal ff_rx_sop       : STD_LOGIC;
  signal ff_rx_eop       : STD_LOGIC;
  signal ff_rx_rdy       : STD_LOGIC;
  signal ff_rx_dval      : STD_LOGIC;
  signal ff_rx_data      : STD_LOGIC_VECTOR(31 downto 0);
  signal ff_rx_mod       : STD_LOGIC_VECTOR(1 downto 0);
  signal rx_frm_type     : STD_LOGIC_VECTOR(3 downto 0);
  signal ff_rx_dsav      : STD_LOGIC;
  signal rx_err_stat     : STD_LOGIC_VECTOR(17 downto 0);
  signal ff_rx_a_full    : STD_LOGIC;
  signal ff_rx_a_empty   : STD_LOGIC;
 
  component esoc_port_mal
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control          : in     STD_LOGIC;
      clk_rgmii            : out    std_logic;
      clk_rgmii_125m       : in     std_logic;
      clk_rgmii_25m        : in     std_logic;
      clk_rgmii_2m5        : in     std_logic;
      ctrl_address         : in     std_logic_vector(15 downto 0);
      ctrl_rd              : in     std_logic := '0';
      ctrl_rddata          : out    std_logic_vector(31 downto 0);
      ctrl_wait            : out    std_logic;
      ctrl_wr              : in     std_logic;
      ctrl_wrdata          : in     std_logic_vector(31 downto 0);
      ena_10               : in     STD_LOGIC;
      eth_mode             : in     STD_LOGIC;
      ff_rx_a_empty        : in     STD_LOGIC;
      ff_rx_a_full         : in     STD_LOGIC;
      ff_rx_data           : in     STD_LOGIC_VECTOR(31 downto 0);
      ff_rx_dsav           : in     STD_LOGIC;
      ff_rx_dval           : in     STD_LOGIC;
      ff_rx_eop            : in     STD_LOGIC;
      ff_rx_mod            : in     STD_LOGIC_VECTOR(1 downto 0);
      ff_rx_rdy            : out    STD_LOGIC;
      ff_rx_sop            : in     STD_LOGIC;
      ff_tx_a_empty        : in     STD_LOGIC;
      ff_tx_a_full         : in     STD_LOGIC;
      ff_tx_crc_fwd        : out    STD_LOGIC;
      ff_tx_data           : out    STD_LOGIC_VECTOR(31 downto 0);
      ff_tx_eop            : out    STD_LOGIC;
      ff_tx_err            : out    STD_LOGIC;
      ff_tx_mod            : out    STD_LOGIC_VECTOR(1 downto 0);
      ff_tx_rdy            : in     STD_LOGIC;
      ff_tx_septy          : in     STD_LOGIC;
      ff_tx_sop            : out    STD_LOGIC;
      ff_tx_wren           : out    STD_LOGIC;
      inbound_data         : out    std_logic_vector(31 downto 0);
      inbound_data_full    : in     std_logic;
      inbound_data_write   : out    std_logic;
      inbound_header       : out    std_logic_vector(111 downto 0);
      inbound_header_write : out    std_logic;
      inbound_info         : out    std_logic_vector(31 downto 0);
      inbound_info_write   : out    std_logic;
      magic_sleep_n        : out    STD_LOGIC := '1';
      magic_wakeup         : in     STD_LOGIC;
      outbound_data        : in     std_logic_vector(31 downto 0);
      outbound_data_read   : out    std_logic;
      outbound_info        : in     std_logic_vector(15 downto 0);
      outbound_info_empty  : in     std_logic;
      outbound_info_read   : out    std_logic;
      reset                : in     STD_LOGIC;
      rx_err_stat          : in     STD_LOGIC_VECTOR(17 downto 0);
      rx_frm_type          : in     STD_LOGIC_VECTOR(3 downto 0);
      set_10               : out    STD_LOGIC := '0'; -- '0'
      set_1000             : out    STD_LOGIC := '0';
      tx_ff_uflow          : in     STD_LOGIC;
      xoff_gen             : out    STD_LOGIC;
      xon_gen              : out    STD_LOGIC);
  end component esoc_port_mal;
 
  component esoc_port_mac
    port(
      ff_tx_crc_fwd : in     STD_LOGIC;
      ff_tx_data    : in     STD_LOGIC_VECTOR(31 downto 0);
      ff_tx_eop     : in     STD_LOGIC;
      ff_tx_err     : in     STD_LOGIC;
      ff_tx_mod     : in     STD_LOGIC_VECTOR(1 downto 0);
      ff_tx_sop     : in     STD_LOGIC;
      ff_tx_wren    : in     STD_LOGIC;
      ff_tx_clk     : in     STD_LOGIC;
      ff_rx_rdy     : in     STD_LOGIC;
      ff_rx_clk     : in     STD_LOGIC;
      address       : in     STD_LOGIC_VECTOR(7 downto 0);
      read          : in     STD_LOGIC;
      writedata     : in     STD_LOGIC_VECTOR(31 downto 0);
      write         : in     STD_LOGIC;
      clk           : in     STD_LOGIC;
      reset         : in     STD_LOGIC;
      rgmii_in      : in     STD_LOGIC_VECTOR(3 downto 0);
      rx_control    : in     STD_LOGIC;
      tx_clk        : in     STD_LOGIC;
      rx_clk        : in     STD_LOGIC;
      set_10        : in     STD_LOGIC;
      set_1000      : in     STD_LOGIC;
      xon_gen       : in     STD_LOGIC;
      xoff_gen      : in     STD_LOGIC;
      magic_sleep_n : in     STD_LOGIC;
      mdio_in       : in     STD_LOGIC;
      ff_tx_rdy     : out    STD_LOGIC;
      ff_rx_data    : out    STD_LOGIC_VECTOR(31 downto 0);
      ff_rx_dval    : out    STD_LOGIC;
      ff_rx_eop     : out    STD_LOGIC;
      ff_rx_mod     : out    STD_LOGIC_VECTOR(1 downto 0);
      ff_rx_sop     : out    STD_LOGIC;
      rx_err        : out    STD_LOGIC_VECTOR(5 downto 0);
      rx_err_stat   : out    STD_LOGIC_VECTOR(17 downto 0);
      rx_frm_type   : out    STD_LOGIC_VECTOR(3 downto 0);
      ff_rx_dsav    : out    STD_LOGIC;
      readdata      : out    STD_LOGIC_VECTOR(31 downto 0);
      waitrequest   : out    STD_LOGIC;
      rgmii_out     : out    STD_LOGIC_VECTOR(3 downto 0);
      tx_control    : out    STD_LOGIC;
      ena_10        : out    STD_LOGIC;
      eth_mode      : out    STD_LOGIC;
      ff_tx_septy   : out    STD_LOGIC;
      tx_ff_uflow   : out    STD_LOGIC;
      ff_rx_a_full  : out    STD_LOGIC;
      ff_rx_a_empty : out    STD_LOGIC;
      ff_tx_a_full  : out    STD_LOGIC;
      ff_tx_a_empty : out    STD_LOGIC;
      magic_wakeup  : out    STD_LOGIC;
      mdio_out      : out    STD_LOGIC;
      mdio_oen      : out    STD_LOGIC;
      mdc           : out    STD_LOGIC);
  end component esoc_port_mac;
 
begin
  rgmii_txc <= clk_rgmii;
  u1: esoc_port_mal
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control          => clk_control,
      clk_rgmii            => clk_rgmii,
      clk_rgmii_125m       => clk_rgmii_125m,
      clk_rgmii_25m        => clk_rgmii_25m,
      clk_rgmii_2m5        => clk_rgmii_2m5,
      ctrl_address         => ctrl_address,
      ctrl_rd              => ctrl_rd,
      ctrl_rddata          => ctrl_rddata,
      ctrl_wait            => ctrl_wait,
      ctrl_wr              => ctrl_wr,
      ctrl_wrdata          => ctrl_wrdata,
      ena_10               => ena_10,
      eth_mode             => eth_mode,
      ff_rx_a_empty        => ff_rx_a_empty,
      ff_rx_a_full         => ff_rx_a_full,
      ff_rx_data           => ff_rx_data,
      ff_rx_dsav           => ff_rx_dsav,
      ff_rx_dval           => ff_rx_dval,
      ff_rx_eop            => ff_rx_eop,
      ff_rx_mod            => ff_rx_mod,
      ff_rx_rdy            => ff_rx_rdy,
      ff_rx_sop            => ff_rx_sop,
      ff_tx_a_empty        => ff_tx_a_empty,
      ff_tx_a_full         => ff_tx_a_full,
      ff_tx_crc_fwd        => ff_tx_crc_fwd,
      ff_tx_data           => ff_tx_data,
      ff_tx_eop            => ff_tx_eop,
      ff_tx_err            => ff_tx_err,
      ff_tx_mod            => ff_tx_mod,
      ff_tx_rdy            => ff_tx_rdy,
      ff_tx_septy          => ff_tx_septy,
      ff_tx_sop            => ff_tx_sop,
      ff_tx_wren           => ff_tx_wren,
      inbound_data         => inbound_data,
      inbound_data_full    => inbound_data_full,
      inbound_data_write   => inbound_data_write,
      inbound_header       => inbound_header,
      inbound_header_write => inbound_header_write,
      inbound_info         => inbound_info,
      inbound_info_write   => inbound_info_write,
      magic_sleep_n        => magic_sleep_n,
      magic_wakeup         => magic_wakeup,
      outbound_data        => outbound_data,
      outbound_data_read   => outbound_data_read,
      outbound_info        => outbound_info,
      outbound_info_empty  => outbound_info_empty,
      outbound_info_read   => outbound_info_read,
      reset                => reset,
      rx_err_stat          => rx_err_stat,
      rx_frm_type          => rx_frm_type,
      set_10               => set_10,
      set_1000             => set_1000,
      tx_ff_uflow          => tx_ff_uflow,
      xoff_gen             => xoff_gen,
      xon_gen              => xon_gen);
 
  u0: esoc_port_mac
    port map(
      ff_tx_crc_fwd => ff_tx_crc_fwd,
      ff_tx_data    => ff_tx_data,
      ff_tx_eop     => ff_tx_eop,
      ff_tx_err     => ff_tx_err,
      ff_tx_mod     => ff_tx_mod,
      ff_tx_sop     => ff_tx_sop,
      ff_tx_wren    => ff_tx_wren,
      ff_tx_clk     => clk_control,
      ff_rx_rdy     => ff_rx_rdy,
      ff_rx_clk     => clk_control,
      address       => mac_address,
      read          => mac_rd,
      writedata     => mac_wrdata,
      write         => mac_wr,
      clk           => clk_control,
      reset         => reset,
      rgmii_in      => rgmii_rxd,
      rx_control    => rgmii_rxctl,
      tx_clk        => clk_rgmii,
      rx_clk        => rgmii_rxc,
      set_10        => set_10,
      set_1000      => set_1000,
      xon_gen       => xon_gen,
      xoff_gen      => xoff_gen,
      magic_sleep_n => magic_sleep_n,
      mdio_in       => mdio_in,
      ff_tx_rdy     => ff_tx_rdy,
      ff_rx_data    => ff_rx_data,
      ff_rx_dval    => ff_rx_dval,
      ff_rx_eop     => ff_rx_eop,
      ff_rx_mod     => ff_rx_mod,
      ff_rx_sop     => ff_rx_sop,
      rx_err        => open,
      rx_err_stat   => rx_err_stat,
      rx_frm_type   => rx_frm_type,
      ff_rx_dsav    => ff_rx_dsav,
      readdata      => mac_rddata,
      waitrequest   => mac_wait,
      rgmii_out     => rgmii_txd,
      tx_control    => rgmii_txctl,
      ena_10        => ena_10,
      eth_mode      => eth_mode,
      ff_tx_septy   => ff_tx_septy,
      tx_ff_uflow   => tx_ff_uflow,
      ff_rx_a_full  => ff_rx_a_full,
      ff_rx_a_empty => ff_rx_a_empty,
      ff_tx_a_full  => ff_tx_a_full,
      ff_tx_a_empty => ff_tx_a_empty,
      magic_wakeup  => magic_wakeup,
      mdio_out      => mdio_out,
      mdio_oen      => mdio_oen,
      mdc           => mdc);
 
 
  mac_mdc   <= mdc;
  mac_mdio  <= mdio_out when mdio_oen = '0' else 'Z';
  mdio_in   <= mac_mdio when mdio_oen = '1'  else '0';
 
 
  mac_address   <= ctrl_address(mac_address'high downto 0);
 
  mac_wrdata    <= ctrl_wrdata;
 
  mac_wr        <= ctrl_wr when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and
                                to_integer(unsigned(ctrl_address)) <  esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size
                                else '0';
 
  mac_rd        <= ctrl_rd when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and
                                to_integer(unsigned(ctrl_address)) <  esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size
                                else '0';
 
  ctrl_bus_enable <= '1' when to_integer(unsigned(ctrl_address))   >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and
                                to_integer(unsigned(ctrl_address)) <  esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size
                                else '0';
 
  ctrl_wait     <= mac_wait when ctrl_bus_enable = '1' else 'Z';
 
  ctrl_rddata   <= mac_rddata when ctrl_bus_enable = '1' else (others => 'Z');
end architecture structure ; -- of esoc_port_interface
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_interface.vhd] - Blame information for rev 55

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2	53	lmaarsen	`--`
3			`-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.`
4			`--`
5			`-- Ease library : work`
6			`-- HDL library : work`
7			`-- Host name : S212065`
8			`-- User name : df768`
9			`-- Time stamp : Tue Aug 19 08:05:18 2014`
10			`--`
11			`-- Designed by : L.Maarsen`
12			`-- Company : LogiXA`
13			`-- Project info : eSoC`
14			`--`
15	42	lmaarsen	`--------------------------------------------------------------------------------`
16	53	lmaarsen
17	42	lmaarsen	`--------------------------------------------------------------------------------`
18			`-- Object : Entity work.esoc_port_interface`
19			`-- Last modified : Mon Apr 14 12:51:18 2014.`
20			`--------------------------------------------------------------------------------`
21
22
23
24			`library ieee, std, work;`
25			`use ieee.std_logic_1164.all;`
26			`use std.textio.all;`
27			`use ieee.numeric_std.all;`
28			`use work.package_esoc_configuration.all;`
29
30			`entity esoc_port_interface is`
31			`generic(`
32			`esoc_port_nr : integer := 0);`
33			`port(`
34			`clk_control : in std_logic;`
35			`clk_rgmii_125m : in STD_LOGIC;`
36			`clk_rgmii_25m : in STD_LOGIC;`
37			`clk_rgmii_2m5 : in STD_LOGIC;`
38			`ctrl_address : in std_logic_vector(15 downto 0);`
39			`ctrl_rd : in std_logic := '0';`
40			`ctrl_rddata : out std_logic_vector(31 downto 0);`
41			`ctrl_wait : out std_logic;`
42			`ctrl_wr : in std_logic;`
43			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
44			`inbound_data : out std_logic_vector(31 downto 0);`
45			`inbound_data_full : in std_logic;`
46			`inbound_data_write : out std_logic;`
47			`inbound_header : out std_logic_vector(111 downto 0);`
48			`inbound_header_write : out std_logic;`
49			`inbound_info : out std_logic_vector(31 downto 0);`
50			`inbound_info_write : out std_logic;`
51			`mac_mdc : out std_logic;`
52			`mac_mdio : inout std_logic;`
53			`outbound_data : in std_logic_vector(31 downto 0);`
54			`outbound_data_read : out std_logic;`
55			`outbound_info : in std_logic_vector(15 downto 0);`
56			`outbound_info_empty : in std_logic;`
57			`outbound_info_read : out std_logic;`
58			`reset : in std_logic;`
59			`rgmii_rxc : in std_logic;`
60			`rgmii_rxctl : in std_logic;`
61			`rgmii_rxd : in std_logic_vector(3 downto 0);`
62			`rgmii_txc : out std_logic;`
63			`rgmii_txctl : out std_logic;`
64			`rgmii_txd : out std_logic_vector(3 downto 0));`
65			`end entity esoc_port_interface;`
66
67			`--------------------------------------------------------------------------------`
68			`-- Object : Architecture work.esoc_port_interface.structure`
69			`-- Last modified : Mon Apr 14 12:51:18 2014.`
70			`--------------------------------------------------------------------------------`
71
72			`architecture structure of esoc_port_interface is`
73
74			`signal ctrl_bus_enable : STD_LOGIC;`
75			`signal clk_rgmii : STD_LOGIC;`
76			`signal mac_rd : STD_LOGIC;`
77			`signal mac_address : STD_LOGIC_VECTOR(7 downto 0);`
78			`signal mdc : STD_LOGIC;`
79			`signal mdio_out : STD_LOGIC;`
80			`signal mdio_in : STD_LOGIC;`
81			`signal mdio_oen : STD_LOGIC;`
82			`signal mac_wait : STD_LOGIC;`
83			`signal mac_rddata : STD_LOGIC_VECTOR(31 downto 0);`
84			`signal mac_wrdata : STD_LOGIC_VECTOR(31 downto 0);`
85			`signal mac_wr : STD_LOGIC;`
86			`signal xon_gen : STD_LOGIC;`
87			`signal xoff_gen : STD_LOGIC;`
88			`signal magic_wakeup : STD_LOGIC;`
89			`signal magic_sleep_n : STD_LOGIC := '1';`
90			`signal set_1000 : STD_LOGIC := '0';`
91			`signal set_10 : STD_LOGIC := '0'; -- '0'`
92			`signal eth_mode : STD_LOGIC;`
93			`signal ena_10 : STD_LOGIC;`
94			`signal ff_tx_sop : STD_LOGIC;`
95			`signal ff_tx_eop : STD_LOGIC;`
96			`signal ff_tx_rdy : STD_LOGIC;`
97			`signal ff_tx_wren : STD_LOGIC;`
98			`signal ff_tx_data : STD_LOGIC_VECTOR(31 downto 0);`
99			`signal ff_tx_mod : STD_LOGIC_VECTOR(1 downto 0);`
100			`signal ff_tx_err : STD_LOGIC;`
101			`signal ff_tx_crc_fwd : STD_LOGIC;`
102			`signal tx_ff_uflow : STD_LOGIC;`
103			`signal ff_tx_a_full : STD_LOGIC;`
104			`signal ff_tx_a_empty : STD_LOGIC;`
105			`signal ff_tx_septy : STD_LOGIC;`
106			`signal ff_rx_sop : STD_LOGIC;`
107			`signal ff_rx_eop : STD_LOGIC;`
108			`signal ff_rx_rdy : STD_LOGIC;`
109			`signal ff_rx_dval : STD_LOGIC;`
110			`signal ff_rx_data : STD_LOGIC_VECTOR(31 downto 0);`
111			`signal ff_rx_mod : STD_LOGIC_VECTOR(1 downto 0);`
112			`signal rx_frm_type : STD_LOGIC_VECTOR(3 downto 0);`
113			`signal ff_rx_dsav : STD_LOGIC;`
114			`signal rx_err_stat : STD_LOGIC_VECTOR(17 downto 0);`
115			`signal ff_rx_a_full : STD_LOGIC;`
116			`signal ff_rx_a_empty : STD_LOGIC;`
117
118			`component esoc_port_mal`
119			`generic(`
120			`esoc_port_nr : integer := 0);`
121			`port(`
122			`clk_control : in STD_LOGIC;`
123			`clk_rgmii : out std_logic;`
124			`clk_rgmii_125m : in std_logic;`
125			`clk_rgmii_25m : in std_logic;`
126			`clk_rgmii_2m5 : in std_logic;`
127			`ctrl_address : in std_logic_vector(15 downto 0);`
128			`ctrl_rd : in std_logic := '0';`
129			`ctrl_rddata : out std_logic_vector(31 downto 0);`
130			`ctrl_wait : out std_logic;`
131			`ctrl_wr : in std_logic;`
132			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
133			`ena_10 : in STD_LOGIC;`
134			`eth_mode : in STD_LOGIC;`
135			`ff_rx_a_empty : in STD_LOGIC;`
136			`ff_rx_a_full : in STD_LOGIC;`
137			`ff_rx_data : in STD_LOGIC_VECTOR(31 downto 0);`
138			`ff_rx_dsav : in STD_LOGIC;`
139			`ff_rx_dval : in STD_LOGIC;`
140			`ff_rx_eop : in STD_LOGIC;`
141			`ff_rx_mod : in STD_LOGIC_VECTOR(1 downto 0);`
142			`ff_rx_rdy : out STD_LOGIC;`
143			`ff_rx_sop : in STD_LOGIC;`
144			`ff_tx_a_empty : in STD_LOGIC;`
145			`ff_tx_a_full : in STD_LOGIC;`
146			`ff_tx_crc_fwd : out STD_LOGIC;`
147			`ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);`
148			`ff_tx_eop : out STD_LOGIC;`
149			`ff_tx_err : out STD_LOGIC;`
150			`ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);`
151			`ff_tx_rdy : in STD_LOGIC;`
152			`ff_tx_septy : in STD_LOGIC;`
153			`ff_tx_sop : out STD_LOGIC;`
154			`ff_tx_wren : out STD_LOGIC;`
155			`inbound_data : out std_logic_vector(31 downto 0);`
156			`inbound_data_full : in std_logic;`
157			`inbound_data_write : out std_logic;`
158			`inbound_header : out std_logic_vector(111 downto 0);`
159			`inbound_header_write : out std_logic;`
160			`inbound_info : out std_logic_vector(31 downto 0);`
161			`inbound_info_write : out std_logic;`
162			`magic_sleep_n : out STD_LOGIC := '1';`
163			`magic_wakeup : in STD_LOGIC;`
164			`outbound_data : in std_logic_vector(31 downto 0);`
165			`outbound_data_read : out std_logic;`
166			`outbound_info : in std_logic_vector(15 downto 0);`
167			`outbound_info_empty : in std_logic;`
168			`outbound_info_read : out std_logic;`
169			`reset : in STD_LOGIC;`
170			`rx_err_stat : in STD_LOGIC_VECTOR(17 downto 0);`
171			`rx_frm_type : in STD_LOGIC_VECTOR(3 downto 0);`
172			`set_10 : out STD_LOGIC := '0'; -- '0'`
173			`set_1000 : out STD_LOGIC := '0';`
174			`tx_ff_uflow : in STD_LOGIC;`
175			`xoff_gen : out STD_LOGIC;`
176			`xon_gen : out STD_LOGIC);`
177			`end component esoc_port_mal;`
178
179			`component esoc_port_mac`
180			`port(`
181			`ff_tx_crc_fwd : in STD_LOGIC;`
182			`ff_tx_data : in STD_LOGIC_VECTOR(31 downto 0);`
183			`ff_tx_eop : in STD_LOGIC;`
184			`ff_tx_err : in STD_LOGIC;`
185			`ff_tx_mod : in STD_LOGIC_VECTOR(1 downto 0);`
186			`ff_tx_sop : in STD_LOGIC;`
187			`ff_tx_wren : in STD_LOGIC;`
188			`ff_tx_clk : in STD_LOGIC;`
189			`ff_rx_rdy : in STD_LOGIC;`
190			`ff_rx_clk : in STD_LOGIC;`
191			`address : in STD_LOGIC_VECTOR(7 downto 0);`
192			`read : in STD_LOGIC;`
193			`writedata : in STD_LOGIC_VECTOR(31 downto 0);`
194			`write : in STD_LOGIC;`
195			`clk : in STD_LOGIC;`
196			`reset : in STD_LOGIC;`
197			`rgmii_in : in STD_LOGIC_VECTOR(3 downto 0);`
198			`rx_control : in STD_LOGIC;`
199			`tx_clk : in STD_LOGIC;`
200			`rx_clk : in STD_LOGIC;`
201			`set_10 : in STD_LOGIC;`
202			`set_1000 : in STD_LOGIC;`
203			`xon_gen : in STD_LOGIC;`
204			`xoff_gen : in STD_LOGIC;`
205			`magic_sleep_n : in STD_LOGIC;`
206			`mdio_in : in STD_LOGIC;`
207			`ff_tx_rdy : out STD_LOGIC;`
208			`ff_rx_data : out STD_LOGIC_VECTOR(31 downto 0);`
209			`ff_rx_dval : out STD_LOGIC;`
210			`ff_rx_eop : out STD_LOGIC;`
211			`ff_rx_mod : out STD_LOGIC_VECTOR(1 downto 0);`
212			`ff_rx_sop : out STD_LOGIC;`
213			`rx_err : out STD_LOGIC_VECTOR(5 downto 0);`
214			`rx_err_stat : out STD_LOGIC_VECTOR(17 downto 0);`
215			`rx_frm_type : out STD_LOGIC_VECTOR(3 downto 0);`
216			`ff_rx_dsav : out STD_LOGIC;`
217			`readdata : out STD_LOGIC_VECTOR(31 downto 0);`
218			`waitrequest : out STD_LOGIC;`
219			`rgmii_out : out STD_LOGIC_VECTOR(3 downto 0);`
220			`tx_control : out STD_LOGIC;`
221			`ena_10 : out STD_LOGIC;`
222			`eth_mode : out STD_LOGIC;`
223			`ff_tx_septy : out STD_LOGIC;`
224			`tx_ff_uflow : out STD_LOGIC;`
225			`ff_rx_a_full : out STD_LOGIC;`
226			`ff_rx_a_empty : out STD_LOGIC;`
227			`ff_tx_a_full : out STD_LOGIC;`
228			`ff_tx_a_empty : out STD_LOGIC;`
229			`magic_wakeup : out STD_LOGIC;`
230			`mdio_out : out STD_LOGIC;`
231			`mdio_oen : out STD_LOGIC;`
232			`mdc : out STD_LOGIC);`
233			`end component esoc_port_mac;`
234
235			`begin`
236			`rgmii_txc <= clk_rgmii;`
237			`u1: esoc_port_mal`
238			`generic map(`
239			`esoc_port_nr => esoc_port_nr)`
240			`port map(`
241			`clk_control => clk_control,`
242			`clk_rgmii => clk_rgmii,`
243			`clk_rgmii_125m => clk_rgmii_125m,`
244			`clk_rgmii_25m => clk_rgmii_25m,`
245			`clk_rgmii_2m5 => clk_rgmii_2m5,`
246			`ctrl_address => ctrl_address,`
247			`ctrl_rd => ctrl_rd,`
248			`ctrl_rddata => ctrl_rddata,`
249			`ctrl_wait => ctrl_wait,`
250			`ctrl_wr => ctrl_wr,`
251			`ctrl_wrdata => ctrl_wrdata,`
252			`ena_10 => ena_10,`
253			`eth_mode => eth_mode,`
254			`ff_rx_a_empty => ff_rx_a_empty,`
255			`ff_rx_a_full => ff_rx_a_full,`
256			`ff_rx_data => ff_rx_data,`
257			`ff_rx_dsav => ff_rx_dsav,`
258			`ff_rx_dval => ff_rx_dval,`
259			`ff_rx_eop => ff_rx_eop,`
260			`ff_rx_mod => ff_rx_mod,`
261			`ff_rx_rdy => ff_rx_rdy,`
262			`ff_rx_sop => ff_rx_sop,`
263			`ff_tx_a_empty => ff_tx_a_empty,`
264			`ff_tx_a_full => ff_tx_a_full,`
265			`ff_tx_crc_fwd => ff_tx_crc_fwd,`
266			`ff_tx_data => ff_tx_data,`
267			`ff_tx_eop => ff_tx_eop,`
268			`ff_tx_err => ff_tx_err,`
269			`ff_tx_mod => ff_tx_mod,`
270			`ff_tx_rdy => ff_tx_rdy,`
271			`ff_tx_septy => ff_tx_septy,`
272			`ff_tx_sop => ff_tx_sop,`
273			`ff_tx_wren => ff_tx_wren,`
274			`inbound_data => inbound_data,`
275			`inbound_data_full => inbound_data_full,`
276			`inbound_data_write => inbound_data_write,`
277			`inbound_header => inbound_header,`
278			`inbound_header_write => inbound_header_write,`
279			`inbound_info => inbound_info,`
280			`inbound_info_write => inbound_info_write,`
281			`magic_sleep_n => magic_sleep_n,`
282			`magic_wakeup => magic_wakeup,`
283			`outbound_data => outbound_data,`
284			`outbound_data_read => outbound_data_read,`
285			`outbound_info => outbound_info,`
286			`outbound_info_empty => outbound_info_empty,`
287			`outbound_info_read => outbound_info_read,`
288			`reset => reset,`
289			`rx_err_stat => rx_err_stat,`
290			`rx_frm_type => rx_frm_type,`
291			`set_10 => set_10,`
292			`set_1000 => set_1000,`
293			`tx_ff_uflow => tx_ff_uflow,`
294			`xoff_gen => xoff_gen,`
295			`xon_gen => xon_gen);`
296
297			`u0: esoc_port_mac`
298			`port map(`
299			`ff_tx_crc_fwd => ff_tx_crc_fwd,`
300			`ff_tx_data => ff_tx_data,`
301			`ff_tx_eop => ff_tx_eop,`
302			`ff_tx_err => ff_tx_err,`
303			`ff_tx_mod => ff_tx_mod,`
304			`ff_tx_sop => ff_tx_sop,`
305			`ff_tx_wren => ff_tx_wren,`
306			`ff_tx_clk => clk_control,`
307			`ff_rx_rdy => ff_rx_rdy,`
308			`ff_rx_clk => clk_control,`
309			`address => mac_address,`
310			`read => mac_rd,`
311			`writedata => mac_wrdata,`
312			`write => mac_wr,`
313			`clk => clk_control,`
314			`reset => reset,`
315			`rgmii_in => rgmii_rxd,`
316			`rx_control => rgmii_rxctl,`
317			`tx_clk => clk_rgmii,`
318			`rx_clk => rgmii_rxc,`
319			`set_10 => set_10,`
320			`set_1000 => set_1000,`
321			`xon_gen => xon_gen,`
322			`xoff_gen => xoff_gen,`
323			`magic_sleep_n => magic_sleep_n,`
324			`mdio_in => mdio_in,`
325			`ff_tx_rdy => ff_tx_rdy,`
326			`ff_rx_data => ff_rx_data,`
327			`ff_rx_dval => ff_rx_dval,`
328			`ff_rx_eop => ff_rx_eop,`
329			`ff_rx_mod => ff_rx_mod,`
330			`ff_rx_sop => ff_rx_sop,`
331			`rx_err => open,`
332			`rx_err_stat => rx_err_stat,`
333			`rx_frm_type => rx_frm_type,`
334			`ff_rx_dsav => ff_rx_dsav,`
335			`readdata => mac_rddata,`
336			`waitrequest => mac_wait,`
337			`rgmii_out => rgmii_txd,`
338			`tx_control => rgmii_txctl,`
339			`ena_10 => ena_10,`
340			`eth_mode => eth_mode,`
341			`ff_tx_septy => ff_tx_septy,`
342			`tx_ff_uflow => tx_ff_uflow,`
343			`ff_rx_a_full => ff_rx_a_full,`
344			`ff_rx_a_empty => ff_rx_a_empty,`
345			`ff_tx_a_full => ff_tx_a_full,`
346			`ff_tx_a_empty => ff_tx_a_empty,`
347			`magic_wakeup => magic_wakeup,`
348			`mdio_out => mdio_out,`
349			`mdio_oen => mdio_oen,`
350			`mdc => mdc);`
351
352
353			`mac_mdc <= mdc;`
354			`mac_mdio <= mdio_out when mdio_oen = '0' else 'Z';`
355			`mdio_in <= mac_mdio when mdio_oen = '1' else '0';`
356
357
358			`mac_address <= ctrl_address(mac_address'high downto 0);`
359
360			`mac_wrdata <= ctrl_wrdata;`
361
362			`mac_wr <= ctrl_wr when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and`
363			`to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size`
364			`else '0';`
365
366			`mac_rd <= ctrl_rd when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and`
367			`to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size`
368			`else '0';`
369
370			`ctrl_bus_enable <= '1' when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and`
371			`to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size`
372			`else '0';`
373
374			`ctrl_wait <= mac_wait when ctrl_bus_enable = '1' else 'Z';`
375
376			`ctrl_rddata <= mac_rddata when ctrl_bus_enable = '1' else (others => 'Z');`
377			`end architecture structure ; -- of esoc_port_interface`
378