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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_mal.vhd] - Blame information for rev 42

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--------------------------------------------------------------------------------
----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_port_mal
-- Last modified : Mon Apr 14 12:48:57 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_port_mal is
  generic(
    esoc_port_nr : integer := 0);
  port(
    clk_control          : in     STD_LOGIC;
    clk_rgmii            : out    std_logic;
    clk_rgmii_125m       : in     std_logic;
    clk_rgmii_25m        : in     std_logic;
    clk_rgmii_2m5        : in     std_logic;
    ctrl_address         : in     std_logic_vector(15 downto 0);
    ctrl_rd              : in     std_logic := '0';
    ctrl_rddata          : out    std_logic_vector(31 downto 0);
    ctrl_wait            : out    std_logic;
    ctrl_wr              : in     std_logic;
    ctrl_wrdata          : in     std_logic_vector(31 downto 0);
    ena_10               : in     STD_LOGIC;
    eth_mode             : in     STD_LOGIC;
    ff_rx_a_empty        : in     STD_LOGIC;
    ff_rx_a_full         : in     STD_LOGIC;
    ff_rx_data           : in     STD_LOGIC_VECTOR(31 downto 0);
    ff_rx_dsav           : in     STD_LOGIC;
    ff_rx_dval           : in     STD_LOGIC;
    ff_rx_eop            : in     STD_LOGIC;
    ff_rx_mod            : in     STD_LOGIC_VECTOR(1 downto 0);
    ff_rx_rdy            : out    STD_LOGIC;
    ff_rx_sop            : in     STD_LOGIC;
    ff_tx_a_empty        : in     STD_LOGIC;
    ff_tx_a_full         : in     STD_LOGIC;
    ff_tx_crc_fwd        : out    STD_LOGIC;
    ff_tx_data           : out    STD_LOGIC_VECTOR(31 downto 0);
    ff_tx_eop            : out    STD_LOGIC;
    ff_tx_err            : out    STD_LOGIC;
    ff_tx_mod            : out    STD_LOGIC_VECTOR(1 downto 0);
    ff_tx_rdy            : in     STD_LOGIC;
    ff_tx_septy          : in     STD_LOGIC;
    ff_tx_sop            : out    STD_LOGIC;
    ff_tx_wren           : out    STD_LOGIC;
    inbound_data         : out    std_logic_vector(31 downto 0);
    inbound_data_full    : in     std_logic;
    inbound_data_write   : out    std_logic;
    inbound_header       : out    std_logic_vector(111 downto 0);
    inbound_header_write : out    std_logic;
    inbound_info         : out    std_logic_vector(31 downto 0);
    inbound_info_write   : out    std_logic;
    magic_sleep_n        : out    STD_LOGIC := '1';
    magic_wakeup         : in     STD_LOGIC;
    outbound_data        : in     std_logic_vector(31 downto 0);
    outbound_data_read   : out    std_logic;
    outbound_info        : in     std_logic_vector(15 downto 0);
    outbound_info_empty  : in     std_logic;
    outbound_info_read   : out    std_logic;
    reset                : in     STD_LOGIC;
    rx_err_stat          : in     STD_LOGIC_VECTOR(17 downto 0);
    rx_frm_type          : in     STD_LOGIC_VECTOR(3 downto 0);
    set_10               : out    STD_LOGIC := '0'; -- '0'
    set_1000             : out    STD_LOGIC := '0';
    tx_ff_uflow          : in     STD_LOGIC;
    xoff_gen             : out    STD_LOGIC;
    xon_gen              : out    STD_LOGIC);
end entity esoc_port_mal;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_port_mal.esoc_port_mal
-- Last modified : Mon Apr 14 12:48:57 2014.
--------------------------------------------------------------------------------
 
architecture esoc_port_mal of esoc_port_mal is
 
  signal port_vlan_default      : std_logic_vector(15 downto 0);
  signal force_vlan_default_in  : std_logic;
  signal force_vlan_default_out : std_logic;
 
  component esoc_port_mal_control
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control            : in     STD_LOGIC;
      ctrl_address           : in     std_logic_vector(15 downto 0);
      ctrl_rd                : in     std_logic := '0';
      ctrl_rddata            : out    std_logic_vector(31 downto 0);
      ctrl_wait              : out    STD_LOGIC;
      ctrl_wr                : in     std_logic;
      ctrl_wrdata            : in     std_logic_vector(31 downto 0);
      force_vlan_default_in  : out    std_logic;
      force_vlan_default_out : out    std_logic;
      magic_sleep_n          : out    STD_LOGIC := '1';
      magic_wakeup           : in     STD_LOGIC;
      port_vlan_default      : out    std_logic_vector(15 downto 0);
      reset                  : in     STD_LOGIC;
      xoff_gen               : out    STD_LOGIC;
      xon_gen                : out    STD_LOGIC);
  end component esoc_port_mal_control;
 
  component esoc_port_mal_inbound
    port(
      clk_control           : in     STD_LOGIC;
      ff_rx_a_empty         : in     STD_LOGIC;
      ff_rx_a_full          : in     STD_LOGIC;
      ff_rx_data            : in     STD_LOGIC_VECTOR(31 downto 0);
      ff_rx_dsav            : in     STD_LOGIC;
      ff_rx_dval            : in     STD_LOGIC;
      ff_rx_eop             : in     STD_LOGIC;
      ff_rx_mod             : in     STD_LOGIC_VECTOR(1 downto 0);
      ff_rx_rdy             : out    STD_LOGIC;
      ff_rx_sop             : in     STD_LOGIC;
      force_vlan_default_in : in     std_logic;
      inbound_data          : out    std_logic_vector(31 downto 0);
      inbound_data_full     : in     std_logic;
      inbound_data_write    : out    std_logic;
      inbound_header        : out    std_logic_vector(111 downto 0);
      inbound_header_write  : out    std_logic;
      inbound_info          : out    std_logic_vector(31 downto 0);
      inbound_info_write    : out    std_logic;
      port_vlan_default     : in     std_logic_vector(15 downto 0);
      reset                 : in     STD_LOGIC;
      rx_err_stat           : in     STD_LOGIC_VECTOR(17 downto 0);
      rx_frm_type           : in     STD_LOGIC_VECTOR(3 downto 0));
  end component esoc_port_mal_inbound;
 
  component esoc_port_mal_outbound
    port(
      clk_control            : in     STD_LOGIC;
      ff_tx_a_empty          : in     STD_LOGIC;
      ff_tx_a_full           : in     STD_LOGIC;
      ff_tx_crc_fwd          : out    STD_LOGIC;
      ff_tx_data             : out    STD_LOGIC_VECTOR(31 downto 0);
      ff_tx_eop              : out    STD_LOGIC;
      ff_tx_err              : out    STD_LOGIC;
      ff_tx_mod              : out    STD_LOGIC_VECTOR(1 downto 0);
      ff_tx_rdy              : in     STD_LOGIC;
      ff_tx_septy            : in     STD_LOGIC;
      ff_tx_sop              : out    STD_LOGIC;
      ff_tx_wren             : out    STD_LOGIC;
      force_vlan_default_out : in     std_logic;
      outbound_data          : in     std_logic_vector(31 downto 0);
      outbound_data_read     : out    std_logic;
      outbound_info          : in     std_logic_vector(15 downto 0);
      outbound_info_empty    : in     std_logic;
      outbound_info_read     : out    std_logic;
      port_vlan_default      : in     std_logic_vector(15 downto 0);
      reset                  : in     STD_LOGIC;
      tx_ff_uflow            : in     STD_LOGIC);
  end component esoc_port_mal_outbound;
 
  component esoc_port_mal_clock
    port(
      clk_control    : in     STD_LOGIC;
      clk_rgmii      : out    std_logic;
      clk_rgmii_125m : in     std_logic;
      clk_rgmii_25m  : in     std_logic;
      clk_rgmii_2m5  : in     std_logic;
      ena_10         : in     STD_LOGIC;
      eth_mode       : in     STD_LOGIC;
      reset          : in     STD_LOGIC;
      set_10         : out    STD_LOGIC := '0'; -- '0'
      set_1000       : out    STD_LOGIC := '0');
  end component esoc_port_mal_clock;
 
begin
  u3: esoc_port_mal_control
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control            => clk_control,
      ctrl_address           => ctrl_address,
      ctrl_rd                => ctrl_rd,
      ctrl_rddata            => ctrl_rddata,
      ctrl_wait              => ctrl_wait,
      ctrl_wr                => ctrl_wr,
      ctrl_wrdata            => ctrl_wrdata,
      force_vlan_default_in  => force_vlan_default_in,
      force_vlan_default_out => force_vlan_default_out,
      magic_sleep_n          => magic_sleep_n,
      magic_wakeup           => magic_wakeup,
      port_vlan_default      => port_vlan_default,
      reset                  => reset,
      xoff_gen               => xoff_gen,
      xon_gen                => xon_gen);
 
  u0: esoc_port_mal_inbound
    port map(
      clk_control           => clk_control,
      ff_rx_a_empty         => ff_rx_a_empty,
      ff_rx_a_full          => ff_rx_a_full,
      ff_rx_data            => ff_rx_data,
      ff_rx_dsav            => ff_rx_dsav,
      ff_rx_dval            => ff_rx_dval,
      ff_rx_eop             => ff_rx_eop,
      ff_rx_mod             => ff_rx_mod,
      ff_rx_rdy             => ff_rx_rdy,
      ff_rx_sop             => ff_rx_sop,
      force_vlan_default_in => force_vlan_default_in,
      inbound_data          => inbound_data,
      inbound_data_full     => inbound_data_full,
      inbound_data_write    => inbound_data_write,
      inbound_header        => inbound_header,
      inbound_header_write  => inbound_header_write,
      inbound_info          => inbound_info,
      inbound_info_write    => inbound_info_write,
      port_vlan_default     => port_vlan_default,
      reset                 => reset,
      rx_err_stat           => rx_err_stat,
      rx_frm_type           => rx_frm_type);
 
  u1: esoc_port_mal_outbound
    port map(
      clk_control            => clk_control,
      ff_tx_a_empty          => ff_tx_a_empty,
      ff_tx_a_full           => ff_tx_a_full,
      ff_tx_crc_fwd          => ff_tx_crc_fwd,
      ff_tx_data             => ff_tx_data,
      ff_tx_eop              => ff_tx_eop,
      ff_tx_err              => ff_tx_err,
      ff_tx_mod              => ff_tx_mod,
      ff_tx_rdy              => ff_tx_rdy,
      ff_tx_septy            => ff_tx_septy,
      ff_tx_sop              => ff_tx_sop,
      ff_tx_wren             => ff_tx_wren,
      force_vlan_default_out => force_vlan_default_out,
      outbound_data          => outbound_data,
      outbound_data_read     => outbound_data_read,
      outbound_info          => outbound_info,
      outbound_info_empty    => outbound_info_empty,
      outbound_info_read     => outbound_info_read,
      port_vlan_default      => port_vlan_default,
      reset                  => reset,
      tx_ff_uflow            => tx_ff_uflow);
 
  u2: esoc_port_mal_clock
    port map(
      clk_control    => clk_control,
      clk_rgmii      => clk_rgmii,
      clk_rgmii_125m => clk_rgmii_125m,
      clk_rgmii_25m  => clk_rgmii_25m,
      clk_rgmii_2m5  => clk_rgmii_2m5,
      ena_10         => ena_10,
      eth_mode       => eth_mode,
      reset          => reset,
      set_10         => set_10,
      set_1000       => set_1000);
 
end architecture esoc_port_mal ; -- of esoc_port_mal
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_mal.vhd] - Blame information for rev 42

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- Ethernet Switch on Configurable Logic IP Core ----`
4			`---- ----`
5			`---- This file is part of the ESoCL project ----`
6			`---- http://www.opencores.org/cores/esoc/ ----`
7			`---- ----`
8			`---- Description: see design description ESoCL_dd_71022001.pdf ----`
9			`---- ----`
10			`---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----`
11			`---- and/or release bulleting ESoCL_rb_71022001.pdf ----`
12			`---- ----`
13			`---- Author(s): L.Maarsen ----`
14			`---- Bert Maarsen, lmaarsen@opencores.org ----`
15			`---- ----`
16			`--------------------------------------------------------------------------------`
17			`---- ----`
18			`---- Copyright (C) 2009 Authors and OPENCORES.ORG ----`
19			`---- ----`
20			`---- This source file may be used and distributed without ----`
21			`---- restriction provided that this copyright statement is not ----`
22			`---- removed from the file and that any derivative work contains ----`
23			`---- the original copyright notice and the associated disclaimer. ----`
24			`---- ----`
25			`---- This source file is free software; you can redistribute it ----`
26			`---- and/or modify it under the terms of the GNU Lesser General ----`
27			`---- Public License as published by the Free Software Foundation; ----`
28			`---- either version 2.1 of the License, or (at your option) any ----`
29			`---- later version. ----`
30			`---- ----`
31			`---- This source is distributed in the hope that it will be ----`
32			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
33			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
34			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
35			`---- details. ----`
36			`---- ----`
37			`---- You should have received a copy of the GNU Lesser General ----`
38			`---- Public License along with this source; if not, download it ----`
39			`---- from http://www.opencores.org/lgpl.shtml ----`
40			`---- ----`
41			`--------------------------------------------------------------------------------`
42			`-- Object : Entity work.esoc_port_mal`
43			`-- Last modified : Mon Apr 14 12:48:57 2014.`
44			`--------------------------------------------------------------------------------`
45
46
47
48			`library ieee, std, work;`
49			`use ieee.std_logic_1164.all;`
50			`use std.textio.all;`
51			`use ieee.numeric_std.all;`
52			`use work.package_esoc_configuration.all;`
53
54			`entity esoc_port_mal is`
55			`generic(`
56			`esoc_port_nr : integer := 0);`
57			`port(`
58			`clk_control : in STD_LOGIC;`
59			`clk_rgmii : out std_logic;`
60			`clk_rgmii_125m : in std_logic;`
61			`clk_rgmii_25m : in std_logic;`
62			`clk_rgmii_2m5 : in std_logic;`
63			`ctrl_address : in std_logic_vector(15 downto 0);`
64			`ctrl_rd : in std_logic := '0';`
65			`ctrl_rddata : out std_logic_vector(31 downto 0);`
66			`ctrl_wait : out std_logic;`
67			`ctrl_wr : in std_logic;`
68			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
69			`ena_10 : in STD_LOGIC;`
70			`eth_mode : in STD_LOGIC;`
71			`ff_rx_a_empty : in STD_LOGIC;`
72			`ff_rx_a_full : in STD_LOGIC;`
73			`ff_rx_data : in STD_LOGIC_VECTOR(31 downto 0);`
74			`ff_rx_dsav : in STD_LOGIC;`
75			`ff_rx_dval : in STD_LOGIC;`
76			`ff_rx_eop : in STD_LOGIC;`
77			`ff_rx_mod : in STD_LOGIC_VECTOR(1 downto 0);`
78			`ff_rx_rdy : out STD_LOGIC;`
79			`ff_rx_sop : in STD_LOGIC;`
80			`ff_tx_a_empty : in STD_LOGIC;`
81			`ff_tx_a_full : in STD_LOGIC;`
82			`ff_tx_crc_fwd : out STD_LOGIC;`
83			`ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);`
84			`ff_tx_eop : out STD_LOGIC;`
85			`ff_tx_err : out STD_LOGIC;`
86			`ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);`
87			`ff_tx_rdy : in STD_LOGIC;`
88			`ff_tx_septy : in STD_LOGIC;`
89			`ff_tx_sop : out STD_LOGIC;`
90			`ff_tx_wren : out STD_LOGIC;`
91			`inbound_data : out std_logic_vector(31 downto 0);`
92			`inbound_data_full : in std_logic;`
93			`inbound_data_write : out std_logic;`
94			`inbound_header : out std_logic_vector(111 downto 0);`
95			`inbound_header_write : out std_logic;`
96			`inbound_info : out std_logic_vector(31 downto 0);`
97			`inbound_info_write : out std_logic;`
98			`magic_sleep_n : out STD_LOGIC := '1';`
99			`magic_wakeup : in STD_LOGIC;`
100			`outbound_data : in std_logic_vector(31 downto 0);`
101			`outbound_data_read : out std_logic;`
102			`outbound_info : in std_logic_vector(15 downto 0);`
103			`outbound_info_empty : in std_logic;`
104			`outbound_info_read : out std_logic;`
105			`reset : in STD_LOGIC;`
106			`rx_err_stat : in STD_LOGIC_VECTOR(17 downto 0);`
107			`rx_frm_type : in STD_LOGIC_VECTOR(3 downto 0);`
108			`set_10 : out STD_LOGIC := '0'; -- '0'`
109			`set_1000 : out STD_LOGIC := '0';`
110			`tx_ff_uflow : in STD_LOGIC;`
111			`xoff_gen : out STD_LOGIC;`
112			`xon_gen : out STD_LOGIC);`
113			`end entity esoc_port_mal;`
114
115			`--------------------------------------------------------------------------------`
116			`-- Object : Architecture work.esoc_port_mal.esoc_port_mal`
117			`-- Last modified : Mon Apr 14 12:48:57 2014.`
118			`--------------------------------------------------------------------------------`
119
120			`architecture esoc_port_mal of esoc_port_mal is`
121
122			`signal port_vlan_default : std_logic_vector(15 downto 0);`
123			`signal force_vlan_default_in : std_logic;`
124			`signal force_vlan_default_out : std_logic;`
125
126			`component esoc_port_mal_control`
127			`generic(`
128			`esoc_port_nr : integer := 0);`
129			`port(`
130			`clk_control : in STD_LOGIC;`
131			`ctrl_address : in std_logic_vector(15 downto 0);`
132			`ctrl_rd : in std_logic := '0';`
133			`ctrl_rddata : out std_logic_vector(31 downto 0);`
134			`ctrl_wait : out STD_LOGIC;`
135			`ctrl_wr : in std_logic;`
136			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
137			`force_vlan_default_in : out std_logic;`
138			`force_vlan_default_out : out std_logic;`
139			`magic_sleep_n : out STD_LOGIC := '1';`
140			`magic_wakeup : in STD_LOGIC;`
141			`port_vlan_default : out std_logic_vector(15 downto 0);`
142			`reset : in STD_LOGIC;`
143			`xoff_gen : out STD_LOGIC;`
144			`xon_gen : out STD_LOGIC);`
145			`end component esoc_port_mal_control;`
146
147			`component esoc_port_mal_inbound`
148			`port(`
149			`clk_control : in STD_LOGIC;`
150			`ff_rx_a_empty : in STD_LOGIC;`
151			`ff_rx_a_full : in STD_LOGIC;`
152			`ff_rx_data : in STD_LOGIC_VECTOR(31 downto 0);`
153			`ff_rx_dsav : in STD_LOGIC;`
154			`ff_rx_dval : in STD_LOGIC;`
155			`ff_rx_eop : in STD_LOGIC;`
156			`ff_rx_mod : in STD_LOGIC_VECTOR(1 downto 0);`
157			`ff_rx_rdy : out STD_LOGIC;`
158			`ff_rx_sop : in STD_LOGIC;`
159			`force_vlan_default_in : in std_logic;`
160			`inbound_data : out std_logic_vector(31 downto 0);`
161			`inbound_data_full : in std_logic;`
162			`inbound_data_write : out std_logic;`
163			`inbound_header : out std_logic_vector(111 downto 0);`
164			`inbound_header_write : out std_logic;`
165			`inbound_info : out std_logic_vector(31 downto 0);`
166			`inbound_info_write : out std_logic;`
167			`port_vlan_default : in std_logic_vector(15 downto 0);`
168			`reset : in STD_LOGIC;`
169			`rx_err_stat : in STD_LOGIC_VECTOR(17 downto 0);`
170			`rx_frm_type : in STD_LOGIC_VECTOR(3 downto 0));`
171			`end component esoc_port_mal_inbound;`
172
173			`component esoc_port_mal_outbound`
174			`port(`
175			`clk_control : in STD_LOGIC;`
176			`ff_tx_a_empty : in STD_LOGIC;`
177			`ff_tx_a_full : in STD_LOGIC;`
178			`ff_tx_crc_fwd : out STD_LOGIC;`
179			`ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);`
180			`ff_tx_eop : out STD_LOGIC;`
181			`ff_tx_err : out STD_LOGIC;`
182			`ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);`
183			`ff_tx_rdy : in STD_LOGIC;`
184			`ff_tx_septy : in STD_LOGIC;`
185			`ff_tx_sop : out STD_LOGIC;`
186			`ff_tx_wren : out STD_LOGIC;`
187			`force_vlan_default_out : in std_logic;`
188			`outbound_data : in std_logic_vector(31 downto 0);`
189			`outbound_data_read : out std_logic;`
190			`outbound_info : in std_logic_vector(15 downto 0);`
191			`outbound_info_empty : in std_logic;`
192			`outbound_info_read : out std_logic;`
193			`port_vlan_default : in std_logic_vector(15 downto 0);`
194			`reset : in STD_LOGIC;`
195			`tx_ff_uflow : in STD_LOGIC);`
196			`end component esoc_port_mal_outbound;`
197
198			`component esoc_port_mal_clock`
199			`port(`
200			`clk_control : in STD_LOGIC;`
201			`clk_rgmii : out std_logic;`
202			`clk_rgmii_125m : in std_logic;`
203			`clk_rgmii_25m : in std_logic;`
204			`clk_rgmii_2m5 : in std_logic;`
205			`ena_10 : in STD_LOGIC;`
206			`eth_mode : in STD_LOGIC;`
207			`reset : in STD_LOGIC;`
208			`set_10 : out STD_LOGIC := '0'; -- '0'`
209			`set_1000 : out STD_LOGIC := '0');`
210			`end component esoc_port_mal_clock;`
211
212			`begin`
213			`u3: esoc_port_mal_control`
214			`generic map(`
215			`esoc_port_nr => esoc_port_nr)`
216			`port map(`
217			`clk_control => clk_control,`
218			`ctrl_address => ctrl_address,`
219			`ctrl_rd => ctrl_rd,`
220			`ctrl_rddata => ctrl_rddata,`
221			`ctrl_wait => ctrl_wait,`
222			`ctrl_wr => ctrl_wr,`
223			`ctrl_wrdata => ctrl_wrdata,`
224			`force_vlan_default_in => force_vlan_default_in,`
225			`force_vlan_default_out => force_vlan_default_out,`
226			`magic_sleep_n => magic_sleep_n,`
227			`magic_wakeup => magic_wakeup,`
228			`port_vlan_default => port_vlan_default,`
229			`reset => reset,`
230			`xoff_gen => xoff_gen,`
231			`xon_gen => xon_gen);`
232
233			`u0: esoc_port_mal_inbound`
234			`port map(`
235			`clk_control => clk_control,`
236			`ff_rx_a_empty => ff_rx_a_empty,`
237			`ff_rx_a_full => ff_rx_a_full,`
238			`ff_rx_data => ff_rx_data,`
239			`ff_rx_dsav => ff_rx_dsav,`
240			`ff_rx_dval => ff_rx_dval,`
241			`ff_rx_eop => ff_rx_eop,`
242			`ff_rx_mod => ff_rx_mod,`
243			`ff_rx_rdy => ff_rx_rdy,`
244			`ff_rx_sop => ff_rx_sop,`
245			`force_vlan_default_in => force_vlan_default_in,`
246			`inbound_data => inbound_data,`
247			`inbound_data_full => inbound_data_full,`
248			`inbound_data_write => inbound_data_write,`
249			`inbound_header => inbound_header,`
250			`inbound_header_write => inbound_header_write,`
251			`inbound_info => inbound_info,`
252			`inbound_info_write => inbound_info_write,`
253			`port_vlan_default => port_vlan_default,`
254			`reset => reset,`
255			`rx_err_stat => rx_err_stat,`
256			`rx_frm_type => rx_frm_type);`
257
258			`u1: esoc_port_mal_outbound`
259			`port map(`
260			`clk_control => clk_control,`
261			`ff_tx_a_empty => ff_tx_a_empty,`
262			`ff_tx_a_full => ff_tx_a_full,`
263			`ff_tx_crc_fwd => ff_tx_crc_fwd,`
264			`ff_tx_data => ff_tx_data,`
265			`ff_tx_eop => ff_tx_eop,`
266			`ff_tx_err => ff_tx_err,`
267			`ff_tx_mod => ff_tx_mod,`
268			`ff_tx_rdy => ff_tx_rdy,`
269			`ff_tx_septy => ff_tx_septy,`
270			`ff_tx_sop => ff_tx_sop,`
271			`ff_tx_wren => ff_tx_wren,`
272			`force_vlan_default_out => force_vlan_default_out,`
273			`outbound_data => outbound_data,`
274			`outbound_data_read => outbound_data_read,`
275			`outbound_info => outbound_info,`
276			`outbound_info_empty => outbound_info_empty,`
277			`outbound_info_read => outbound_info_read,`
278			`port_vlan_default => port_vlan_default,`
279			`reset => reset,`
280			`tx_ff_uflow => tx_ff_uflow);`
281
282			`u2: esoc_port_mal_clock`
283			`port map(`
284			`clk_control => clk_control,`
285			`clk_rgmii => clk_rgmii,`
286			`clk_rgmii_125m => clk_rgmii_125m,`
287			`clk_rgmii_25m => clk_rgmii_25m,`
288			`clk_rgmii_2m5 => clk_rgmii_2m5,`
289			`ena_10 => ena_10,`
290			`eth_mode => eth_mode,`
291			`reset => reset,`
292			`set_10 => set_10,`
293			`set_1000 => set_1000);`
294
295			`end architecture esoc_port_mal ; -- of esoc_port_mal`
296