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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_processor.vhd] - Blame information for rev 46

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1 42 lmaarsen
--------------------------------------------------------------------------------
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----                                                                        ----
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---- Ethernet Switch on Configurable Logic IP Core                          ----
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----                                                                        ----
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---- This file is part of the ESoCL project                                 ----
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---- http://www.opencores.org/cores/esoc/                                   ----
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----                                                                        ----
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---- Description: see design description ESoCL_dd_71022001.pdf              ----
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----                                                                        ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
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----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
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----                                                                        ----
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---- Author(s): L.Maarsen                                                   ----
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---- Bert Maarsen, lmaarsen@opencores.org                                   ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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----                                                                        ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
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----                                                                        ----
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---- This source file may be used and distributed without                   ----
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---- restriction provided that this copyright statement is not              ----
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---- removed from the file and that any derivative work contains            ----
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---- the original copyright notice and the associated disclaimer.           ----
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----                                                                        ----
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---- This source file is free software; you can redistribute it             ----
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---- and/or modify it under the terms of the GNU Lesser General             ----
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---- Public License as published by the Free Software Foundation;           ----
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---- either version 2.1 of the License, or (at your option) any             ----
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---- later version.                                                         ----
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----                                                                        ----
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---- This source is distributed in the hope that it will be                 ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
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---- PURPOSE. See the GNU Lesser General Public License for more            ----
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---- details.                                                               ----
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----                                                                        ----
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---- You should have received a copy of the GNU Lesser General              ----
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---- Public License along with this source; if not, download it             ----
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---- from http://www.opencores.org/lgpl.shtml                               ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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-- Object        : Entity work.esoc_port_processor
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-- Last modified : Mon Apr 14 12:49:21 2014.
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--------------------------------------------------------------------------------
45
 
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48
library ieee, std, work;
49
use ieee.std_logic_1164.all;
50
use std.textio.all;
51
use ieee.numeric_std.all;
52
use work.package_esoc_configuration.all;
53
 
54
entity esoc_port_processor is
55
  generic(
56
    esoc_port_nr : integer := 0);
57
  port(
58
    clk_control          : in     std_logic;
59
    clk_data             : in     std_logic;
60
    clk_search           : in     std_logic;
61
    ctrl_address         : in     std_logic_vector(15 downto 0);
62
    ctrl_rd              : in     std_logic;
63
    ctrl_rddata          : out    std_logic_vector(31 downto 0);
64
    ctrl_wait            : out    std_logic;
65
    ctrl_wr              : in     std_logic;
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    ctrl_wrdata          : in     std_logic_vector(31 downto 0);
67
    data                 : inout  std_logic_vector(63 downto 0);
68
    data_eof             : inout  std_logic;
69
    data_gnt_rd          : in     std_logic;
70
    data_gnt_wr          : in     std_logic;
71
    data_port_sel        : inout  std_logic_vector(esoc_port_count-1 downto 0);
72
    data_req             : out    std_logic;
73
    data_sof             : inout  std_logic;
74
    inbound_data         : in     std_logic_vector(63 downto 0);
75
    inbound_data_full    : in     std_logic;
76
    inbound_data_read    : out    std_logic;
77
    inbound_header       : in     std_logic_vector(111 downto 0);
78
    inbound_header_empty : in     std_logic;
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    inbound_header_read  : out    std_logic;
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    inbound_info         : in     std_logic_vector(31 downto 0);
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    inbound_info_empty   : in     std_logic;
82
    inbound_info_read    : out    std_logic;
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    outbound_data        : out    std_logic_vector(63 downto 0);
84
    outbound_data_full   : in     std_logic;
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    outbound_data_write  : out    std_logic;
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    outbound_info        : out    std_logic_vector(15 downto 0);
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    outbound_info_write  : out    std_logic;
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    reset                : in     std_logic;
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    search_eof           : out    std_logic;
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    search_gnt_wr        : in     std_logic;
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    search_key           : out    std_logic_vector(63 downto 0);
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    search_req           : out    std_logic;
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    search_result        : in     std_logic_vector(esoc_port_count-1 downto 0);
94
    search_result_av     : in     std_logic;
95
    search_sof           : out    std_logic);
96
end entity esoc_port_processor;
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98
--------------------------------------------------------------------------------
99
-- Object        : Architecture work.esoc_port_processor.structure
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-- Last modified : Mon Apr 14 12:49:21 2014.
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--------------------------------------------------------------------------------
102
 
103
architecture structure of esoc_port_processor is
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105
  signal Net_0               : STD_LOGIC;
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  signal Net_1               : STD_LOGIC_VECTOR(15 downto 0);
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  signal rdempty             : STD_LOGIC;
108
  signal Net_2               : STD_LOGIC;
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  signal q_a                 : STD_LOGIC_VECTOR(0 downto 0);
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  signal outbound_drop_cnt   : std_logic;
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  signal outbound_done_cnt   : std_logic;
112
  signal search_done_cnt     : std_logic;
113
  signal inbound_done_cnt    : std_logic;
114
  signal inbound_drop_cnt    : std_logic;
115
  signal ctrl_vlan_id        : std_logic_vector(11 downto 0);
116
  signal ctrl_vlan_id_member : std_logic_vector(0 downto 0);
117
  signal outbound_vlan_id    : STD_LOGIC_VECTOR(11 downto 0);
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  signal ctrl_vlan_id_wr     : std_logic;
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  signal q_b                 : STD_LOGIC_VECTOR(0 downto 0);
120
  signal search_data         : STD_LOGIC_VECTOR(15 downto 0);
121
  signal u4_q_b              : STD_LOGIC_VECTOR(0 downto 0);
122
  signal search_drop_cnt     : std_logic;
123
 
124
  component esoc_port_processor_search
125
    generic(
126
      esoc_port_nr : integer := 0);
127
    port(
128
      clk_search           : in     std_logic;
129
      inbound_header       : in     std_logic_vector(111 downto 0);
130
      inbound_header_empty : in     std_logic;
131
      inbound_header_read  : out    std_logic;
132
      inbound_vlan_member  : in     STD_LOGIC_VECTOR(0 downto 0);
133
      reset                : in     std_logic;
134
      search_data          : out    STD_LOGIC_VECTOR(15 downto 0);
135
      search_done_cnt      : out    std_logic;
136
      search_drop_cnt      : out    std_logic;
137
      search_eof           : out    std_logic;
138
      search_gnt_wr        : in     std_logic;
139
      search_key           : out    std_logic_vector(63 downto 0);
140
      search_req           : out    std_logic;
141
      search_result        : in     std_logic_vector(esoc_port_count-1 downto 0);
142
      search_result_av     : in     std_logic;
143
      search_sof           : out    std_logic;
144
      search_write         : out    STD_LOGIC);
145
  end component esoc_port_processor_search;
146
 
147
  component esoc_port_processor_inbound
148
    generic(
149
      esoc_port_nr : integer := 0);
150
    port(
151
      clk_data           : in     std_logic;
152
      data               : inout  std_logic_vector(63 downto 0);
153
      data_eof           : inout  std_logic;
154
      data_gnt_wr        : in     std_logic;
155
      data_port_sel      : inout  std_logic_vector(esoc_port_count-1 downto 0);
156
      data_req           : out    std_logic;
157
      data_sof           : inout  std_logic;
158
      inbound_data       : in     std_logic_vector(63 downto 0);
159
      inbound_data_full  : in     std_logic;
160
      inbound_data_read  : out    std_logic;
161
      inbound_done_cnt   : out    std_logic;
162
      inbound_drop_cnt   : out    std_logic;
163
      inbound_info       : in     std_logic_vector(31 downto 0);
164
      inbound_info_empty : in     std_logic;
165
      inbound_info_read  : out    std_logic;
166
      reset              : in     std_logic;
167
      search_data        : in     STD_LOGIC_VECTOR(15 downto 0);
168
      search_empty       : in     STD_LOGIC;
169
      search_read        : out    STD_LOGIC);
170
  end component esoc_port_processor_inbound;
171
 
172
  component esoc_port_processor_outbound
173
    generic(
174
      esoc_port_nr : integer := 0);
175
    port(
176
      clk_data             : in     std_logic;
177
      data                 : in     std_logic_vector(63 downto 0);
178
      data_eof             : in     std_logic;
179
      data_gnt_rd          : in     std_logic;
180
      data_port_sel        : in     std_logic_vector(esoc_port_count-1 downto 0);
181
      data_sof             : in     std_logic;
182
      outbound_data        : out    std_logic_vector(63 downto 0);
183
      outbound_data_full   : in     std_logic;
184
      outbound_data_write  : out    std_logic;
185
      outbound_done_cnt    : out    std_logic;
186
      outbound_drop_cnt    : out    std_logic;
187
      outbound_info        : out    std_logic_vector(15 downto 0);
188
      outbound_info_write  : out    std_logic;
189
      outbound_vlan_id     : out    STD_LOGIC_VECTOR(11 downto 0);
190
      outbound_vlan_member : in     STD_LOGIC_VECTOR(0 downto 0);
191
      reset                : in     std_logic);
192
  end component esoc_port_processor_outbound;
193
 
194
  component esoc_port_processor_control
195
    generic(
196
      esoc_port_nr : integer := 0);
197
    port(
198
      clk_control             : in     std_logic;
199
      clk_data                : in     std_logic;
200
      clk_search              : in     std_logic;
201
      ctrl_address            : in     std_logic_vector(15 downto 0);
202
      ctrl_rd                 : in     std_logic;
203
      ctrl_rddata             : out    std_logic_vector(31 downto 0);
204
      ctrl_vlan_id            : out    std_logic_vector(11 downto 0);
205
      ctrl_vlan_id_member_in  : in     std_logic_vector(0 downto 0);
206
      ctrl_vlan_id_member_out : out    std_logic_vector(0 downto 0);
207
      ctrl_vlan_id_wr         : out    std_logic;
208
      ctrl_wait               : out    std_logic;
209
      ctrl_wr                 : in     std_logic;
210
      ctrl_wrdata             : in     std_logic_vector(31 downto 0);
211
      inbound_done_cnt        : in     std_logic;
212
      inbound_drop_cnt        : in     std_logic;
213
      outbound_done_cnt       : in     std_logic;
214
      outbound_drop_cnt       : in     std_logic;
215
      reset                   : in     STD_LOGIC := '0';
216
      search_done_cnt         : in     std_logic;
217
      search_drop_cnt         : in     std_logic);
218
  end component esoc_port_processor_control;
219
 
220
  component esoc_fifo_256x16
221
    port(
222
      aclr    : in     STD_LOGIC := '0';
223
      data    : in     STD_LOGIC_VECTOR(15 downto 0);
224
      rdclk   : in     STD_LOGIC;
225
      rdreq   : in     STD_LOGIC;
226
      wrclk   : in     STD_LOGIC;
227
      wrreq   : in     STD_LOGIC;
228
      q       : out    STD_LOGIC_VECTOR(15 downto 0);
229
      rdempty : out    STD_LOGIC;
230
      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);
231
      wrfull  : out    STD_LOGIC;
232
      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));
233
  end component esoc_fifo_256x16;
234
 
235
  component esoc_ram_4kx1
236
    port(
237
      address_a : in     STD_LOGIC_VECTOR(11 downto 0);
238
      address_b : in     STD_LOGIC_VECTOR(11 downto 0);
239
      clock_a   : in     STD_LOGIC := '1';
240
      clock_b   : in     STD_LOGIC;
241
      data_a    : in     STD_LOGIC_VECTOR(0 downto 0);
242
      data_b    : in     STD_LOGIC_VECTOR(0 downto 0);
243
      wren_a    : in     STD_LOGIC := '0';
244
      wren_b    : in     STD_LOGIC := '0';
245
      q_a       : out    STD_LOGIC_VECTOR(0 downto 0);
246
      q_b       : out    STD_LOGIC_VECTOR(0 downto 0);
247
      rden_a    : in     STD_LOGIC := '1';
248
      rden_b    : in     STD_LOGIC := '1');
249
  end component esoc_ram_4kx1;
250
 
251
begin
252
  --Search Engine Control
253
  --Inbound Control - port to switch core
254
  --Outbound Control - port to switch core
255
  --Search Result FIFO
256
  --VLAN Member Table
257
  --Port Processor Control
258
  --VLAN Member Table
259
  u0: esoc_port_processor_search
260
    generic map(
261
      esoc_port_nr => esoc_port_nr)
262
    port map(
263
      clk_search           => clk_search,
264
      inbound_header       => inbound_header,
265
      inbound_header_empty => inbound_header_empty,
266
      inbound_header_read  => inbound_header_read,
267
      inbound_vlan_member  => q_a,
268
      reset                => reset,
269
      search_data          => search_data,
270
      search_done_cnt      => search_done_cnt,
271
      search_drop_cnt      => search_drop_cnt,
272
      search_eof           => search_eof,
273
      search_gnt_wr        => search_gnt_wr,
274
      search_key           => search_key,
275
      search_req           => search_req,
276
      search_result        => search_result,
277
      search_result_av     => search_result_av,
278
      search_sof           => search_sof,
279
      search_write         => Net_2);
280
 
281
  u1: esoc_port_processor_inbound
282
    generic map(
283
      esoc_port_nr => esoc_port_nr)
284
    port map(
285
      clk_data           => clk_data,
286
      data               => data,
287
      data_eof           => data_eof,
288
      data_gnt_wr        => data_gnt_wr,
289
      data_port_sel      => data_port_sel,
290
      data_req           => data_req,
291
      data_sof           => data_sof,
292
      inbound_data       => inbound_data,
293
      inbound_data_full  => inbound_data_full,
294
      inbound_data_read  => inbound_data_read,
295
      inbound_done_cnt   => inbound_done_cnt,
296
      inbound_drop_cnt   => inbound_drop_cnt,
297
      inbound_info       => inbound_info,
298
      inbound_info_empty => inbound_info_empty,
299
      inbound_info_read  => inbound_info_read,
300
      reset              => reset,
301
      search_data        => Net_1,
302
      search_empty       => rdempty,
303
      search_read        => Net_0);
304
 
305
  u2: esoc_port_processor_outbound
306
    generic map(
307
      esoc_port_nr => esoc_port_nr)
308
    port map(
309
      clk_data             => clk_data,
310
      data                 => data,
311
      data_eof             => data_eof,
312
      data_gnt_rd          => data_gnt_rd,
313
      data_port_sel        => data_port_sel,
314
      data_sof             => data_sof,
315
      outbound_data        => outbound_data,
316
      outbound_data_full   => outbound_data_full,
317
      outbound_data_write  => outbound_data_write,
318
      outbound_done_cnt    => outbound_done_cnt,
319
      outbound_drop_cnt    => outbound_drop_cnt,
320
      outbound_info        => outbound_info,
321
      outbound_info_write  => outbound_info_write,
322
      outbound_vlan_id     => outbound_vlan_id,
323
      outbound_vlan_member => u4_q_b,
324
      reset                => reset);
325
 
326
  u3: esoc_port_processor_control
327
    generic map(
328
      esoc_port_nr => esoc_port_nr)
329
    port map(
330
      clk_control             => clk_control,
331
      clk_data                => clk_data,
332
      clk_search              => clk_search,
333
      ctrl_address            => ctrl_address,
334
      ctrl_rd                 => ctrl_rd,
335
      ctrl_rddata             => ctrl_rddata,
336
      ctrl_vlan_id            => ctrl_vlan_id,
337
      ctrl_vlan_id_member_in  => q_b,
338
      ctrl_vlan_id_member_out => ctrl_vlan_id_member,
339
      ctrl_vlan_id_wr         => ctrl_vlan_id_wr,
340
      ctrl_wait               => ctrl_wait,
341
      ctrl_wr                 => ctrl_wr,
342
      ctrl_wrdata             => ctrl_wrdata,
343
      inbound_done_cnt        => inbound_done_cnt,
344
      inbound_drop_cnt        => inbound_drop_cnt,
345
      outbound_done_cnt       => outbound_done_cnt,
346
      outbound_drop_cnt       => outbound_drop_cnt,
347
      reset                   => reset,
348
      search_done_cnt         => search_done_cnt,
349
      search_drop_cnt         => search_drop_cnt);
350
 
351
  u5: esoc_fifo_256x16
352
    port map(
353
      aclr    => reset,
354
      data    => search_data,
355
      rdclk   => clk_data,
356
      rdreq   => Net_0,
357
      wrclk   => clk_search,
358
      wrreq   => Net_2,
359
      q       => Net_1,
360
      rdempty => rdempty,
361
      rdusedw => open,
362
      wrfull  => open,
363
      wrusedw => open);
364
 
365
  u6: esoc_ram_4kx1
366
    port map(
367
      address_a => inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan),
368
      address_b => ctrl_vlan_id,
369
      clock_a   => clk_search,
370
      clock_b   => clk_control,
371
      data_a    => (others => '0'),
372
      data_b    => ctrl_vlan_id_member,
373
      wren_a    => '0',
374
      wren_b    => ctrl_vlan_id_wr,
375
      q_a       => q_a,
376
      q_b       => q_b,
377
      rden_a    => '1',
378
      rden_b    => '1');
379
 
380
  u4: esoc_ram_4kx1
381
    port map(
382
      address_a => ctrl_vlan_id,
383
      address_b => outbound_vlan_id,
384
      clock_a   => clk_control,
385
      clock_b   => clk_data,
386
      data_a    => ctrl_vlan_id_member,
387
      data_b    => (others => '0'),
388
      wren_a    => ctrl_vlan_id_wr,
389
      wren_b    => '0',
390
      q_a       => open,
391
      q_b       => u4_q_b,
392
      rden_a    => '1',
393
      rden_b    => '1');
394
 
395
end architecture structure ; -- of esoc_port_processor
396
 

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