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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_processor.vhd] - Blame information for rev 56

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--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : S212065
-- User name     : df768
-- Time stamp    : Tue Aug 19 08:05:18 2014
--
-- Designed by   : L.Maarsen
-- Company       : LogiXA
-- Project info  : eSoC
--
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_port_processor
-- Last modified : Mon Apr 14 12:49:21 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_port_processor is
  generic(
    esoc_port_nr : integer := 0);
  port(
    clk_control          : in     std_logic;
    clk_data             : in     std_logic;
    clk_search           : in     std_logic;
    ctrl_address         : in     std_logic_vector(15 downto 0);
    ctrl_rd              : in     std_logic;
    ctrl_rddata          : out    std_logic_vector(31 downto 0);
    ctrl_wait            : out    std_logic;
    ctrl_wr              : in     std_logic;
    ctrl_wrdata          : in     std_logic_vector(31 downto 0);
    data                 : inout  std_logic_vector(63 downto 0);
    data_eof             : inout  std_logic;
    data_gnt_rd          : in     std_logic;
    data_gnt_wr          : in     std_logic;
    data_port_sel        : inout  std_logic_vector(esoc_port_count-1 downto 0);
    data_req             : out    std_logic;
    data_sof             : inout  std_logic;
    inbound_data         : in     std_logic_vector(63 downto 0);
    inbound_data_full    : in     std_logic;
    inbound_data_read    : out    std_logic;
    inbound_header       : in     std_logic_vector(111 downto 0);
    inbound_header_empty : in     std_logic;
    inbound_header_read  : out    std_logic;
    inbound_info         : in     std_logic_vector(31 downto 0);
    inbound_info_empty   : in     std_logic;
    inbound_info_read    : out    std_logic;
    outbound_data        : out    std_logic_vector(63 downto 0);
    outbound_data_full   : in     std_logic;
    outbound_data_write  : out    std_logic;
    outbound_info        : out    std_logic_vector(15 downto 0);
    outbound_info_write  : out    std_logic;
    reset                : in     std_logic;
    search_eof           : out    std_logic;
    search_gnt_wr        : in     std_logic;
    search_key           : out    std_logic_vector(63 downto 0);
    search_req           : out    std_logic;
    search_result        : in     std_logic_vector(esoc_port_count-1 downto 0);
    search_result_av     : in     std_logic;
    search_sof           : out    std_logic);
end entity esoc_port_processor;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_port_processor.structure
-- Last modified : Mon Apr 14 12:49:21 2014.
--------------------------------------------------------------------------------
 
architecture structure of esoc_port_processor is
 
  signal Net_0               : STD_LOGIC;
  signal Net_1               : STD_LOGIC_VECTOR(15 downto 0);
  signal rdempty             : STD_LOGIC;
  signal Net_2               : STD_LOGIC;
  signal q_a                 : STD_LOGIC_VECTOR(0 downto 0);
  signal outbound_drop_cnt   : std_logic;
  signal outbound_done_cnt   : std_logic;
  signal search_done_cnt     : std_logic;
  signal inbound_done_cnt    : std_logic;
  signal inbound_drop_cnt    : std_logic;
  signal ctrl_vlan_id        : std_logic_vector(11 downto 0);
  signal ctrl_vlan_id_member : std_logic_vector(0 downto 0);
  signal outbound_vlan_id    : STD_LOGIC_VECTOR(11 downto 0);
  signal ctrl_vlan_id_wr     : std_logic;
  signal q_b                 : STD_LOGIC_VECTOR(0 downto 0);
  signal search_data         : STD_LOGIC_VECTOR(15 downto 0);
  signal u4_q_b              : STD_LOGIC_VECTOR(0 downto 0);
  signal search_drop_cnt     : std_logic;
 
  component esoc_port_processor_search
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_search           : in     std_logic;
      inbound_header       : in     std_logic_vector(111 downto 0);
      inbound_header_empty : in     std_logic;
      inbound_header_read  : out    std_logic;
      inbound_vlan_member  : in     STD_LOGIC_VECTOR(0 downto 0);
      reset                : in     std_logic;
      search_data          : out    STD_LOGIC_VECTOR(15 downto 0);
      search_done_cnt      : out    std_logic;
      search_drop_cnt      : out    std_logic;
      search_eof           : out    std_logic;
      search_gnt_wr        : in     std_logic;
      search_key           : out    std_logic_vector(63 downto 0);
      search_req           : out    std_logic;
      search_result        : in     std_logic_vector(esoc_port_count-1 downto 0);
      search_result_av     : in     std_logic;
      search_sof           : out    std_logic;
      search_write         : out    STD_LOGIC);
  end component esoc_port_processor_search;
 
  component esoc_port_processor_inbound
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_data           : in     std_logic;
      data               : inout  std_logic_vector(63 downto 0);
      data_eof           : inout  std_logic;
      data_gnt_wr        : in     std_logic;
      data_port_sel      : inout  std_logic_vector(esoc_port_count-1 downto 0);
      data_req           : out    std_logic;
      data_sof           : inout  std_logic;
      inbound_data       : in     std_logic_vector(63 downto 0);
      inbound_data_full  : in     std_logic;
      inbound_data_read  : out    std_logic;
      inbound_done_cnt   : out    std_logic;
      inbound_drop_cnt   : out    std_logic;
      inbound_info       : in     std_logic_vector(31 downto 0);
      inbound_info_empty : in     std_logic;
      inbound_info_read  : out    std_logic;
      reset              : in     std_logic;
      search_data        : in     STD_LOGIC_VECTOR(15 downto 0);
      search_empty       : in     STD_LOGIC;
      search_read        : out    STD_LOGIC);
  end component esoc_port_processor_inbound;
 
  component esoc_port_processor_outbound
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_data             : in     std_logic;
      data                 : in     std_logic_vector(63 downto 0);
      data_eof             : in     std_logic;
      data_gnt_rd          : in     std_logic;
      data_port_sel        : in     std_logic_vector(esoc_port_count-1 downto 0);
      data_sof             : in     std_logic;
      outbound_data        : out    std_logic_vector(63 downto 0);
      outbound_data_full   : in     std_logic;
      outbound_data_write  : out    std_logic;
      outbound_done_cnt    : out    std_logic;
      outbound_drop_cnt    : out    std_logic;
      outbound_info        : out    std_logic_vector(15 downto 0);
      outbound_info_write  : out    std_logic;
      outbound_vlan_id     : out    STD_LOGIC_VECTOR(11 downto 0);
      outbound_vlan_member : in     STD_LOGIC_VECTOR(0 downto 0);
      reset                : in     std_logic);
  end component esoc_port_processor_outbound;
 
  component esoc_port_processor_control
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control             : in     std_logic;
      clk_data                : in     std_logic;
      clk_search              : in     std_logic;
      ctrl_address            : in     std_logic_vector(15 downto 0);
      ctrl_rd                 : in     std_logic;
      ctrl_rddata             : out    std_logic_vector(31 downto 0);
      ctrl_vlan_id            : out    std_logic_vector(11 downto 0);
      ctrl_vlan_id_member_in  : in     std_logic_vector(0 downto 0);
      ctrl_vlan_id_member_out : out    std_logic_vector(0 downto 0);
      ctrl_vlan_id_wr         : out    std_logic;
      ctrl_wait               : out    std_logic;
      ctrl_wr                 : in     std_logic;
      ctrl_wrdata             : in     std_logic_vector(31 downto 0);
      inbound_done_cnt        : in     std_logic;
      inbound_drop_cnt        : in     std_logic;
      outbound_done_cnt       : in     std_logic;
      outbound_drop_cnt       : in     std_logic;
      reset                   : in     STD_LOGIC := '0';
      search_done_cnt         : in     std_logic;
      search_drop_cnt         : in     std_logic);
  end component esoc_port_processor_control;
 
  component esoc_fifo_256x16
    port(
      aclr    : in     STD_LOGIC := '0';
      data    : in     STD_LOGIC_VECTOR(15 downto 0);
      rdclk   : in     STD_LOGIC;
      rdreq   : in     STD_LOGIC;
      wrclk   : in     STD_LOGIC;
      wrreq   : in     STD_LOGIC;
      q       : out    STD_LOGIC_VECTOR(15 downto 0);
      rdempty : out    STD_LOGIC;
      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);
      wrfull  : out    STD_LOGIC;
      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));
  end component esoc_fifo_256x16;
 
  component esoc_ram_4kx1
    port(
      address_a : in     STD_LOGIC_VECTOR(11 downto 0);
      address_b : in     STD_LOGIC_VECTOR(11 downto 0);
      clock_a   : in     STD_LOGIC := '1';
      clock_b   : in     STD_LOGIC;
      data_a    : in     STD_LOGIC_VECTOR(0 downto 0);
      data_b    : in     STD_LOGIC_VECTOR(0 downto 0);
      wren_a    : in     STD_LOGIC := '0';
      wren_b    : in     STD_LOGIC := '0';
      q_a       : out    STD_LOGIC_VECTOR(0 downto 0);
      q_b       : out    STD_LOGIC_VECTOR(0 downto 0);
      rden_a    : in     STD_LOGIC := '1';
      rden_b    : in     STD_LOGIC := '1');
  end component esoc_ram_4kx1;
 
begin
  --Search Engine Control
  --Inbound Control - port to switch core
  --Outbound Control - port to switch core
  --Search Result FIFO
  --VLAN Member Table
  --Port Processor Control
  --VLAN Member Table
  u0: esoc_port_processor_search
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_search           => clk_search,
      inbound_header       => inbound_header,
      inbound_header_empty => inbound_header_empty,
      inbound_header_read  => inbound_header_read,
      inbound_vlan_member  => q_a,
      reset                => reset,
      search_data          => search_data,
      search_done_cnt      => search_done_cnt,
      search_drop_cnt      => search_drop_cnt,
      search_eof           => search_eof,
      search_gnt_wr        => search_gnt_wr,
      search_key           => search_key,
      search_req           => search_req,
      search_result        => search_result,
      search_result_av     => search_result_av,
      search_sof           => search_sof,
      search_write         => Net_2);
 
  u1: esoc_port_processor_inbound
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_data           => clk_data,
      data               => data,
      data_eof           => data_eof,
      data_gnt_wr        => data_gnt_wr,
      data_port_sel      => data_port_sel,
      data_req           => data_req,
      data_sof           => data_sof,
      inbound_data       => inbound_data,
      inbound_data_full  => inbound_data_full,
      inbound_data_read  => inbound_data_read,
      inbound_done_cnt   => inbound_done_cnt,
      inbound_drop_cnt   => inbound_drop_cnt,
      inbound_info       => inbound_info,
      inbound_info_empty => inbound_info_empty,
      inbound_info_read  => inbound_info_read,
      reset              => reset,
      search_data        => Net_1,
      search_empty       => rdempty,
      search_read        => Net_0);
 
  u2: esoc_port_processor_outbound
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_data             => clk_data,
      data                 => data,
      data_eof             => data_eof,
      data_gnt_rd          => data_gnt_rd,
      data_port_sel        => data_port_sel,
      data_sof             => data_sof,
      outbound_data        => outbound_data,
      outbound_data_full   => outbound_data_full,
      outbound_data_write  => outbound_data_write,
      outbound_done_cnt    => outbound_done_cnt,
      outbound_drop_cnt    => outbound_drop_cnt,
      outbound_info        => outbound_info,
      outbound_info_write  => outbound_info_write,
      outbound_vlan_id     => outbound_vlan_id,
      outbound_vlan_member => u4_q_b,
      reset                => reset);
 
  u3: esoc_port_processor_control
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control             => clk_control,
      clk_data                => clk_data,
      clk_search              => clk_search,
      ctrl_address            => ctrl_address,
      ctrl_rd                 => ctrl_rd,
      ctrl_rddata             => ctrl_rddata,
      ctrl_vlan_id            => ctrl_vlan_id,
      ctrl_vlan_id_member_in  => q_b,
      ctrl_vlan_id_member_out => ctrl_vlan_id_member,
      ctrl_vlan_id_wr         => ctrl_vlan_id_wr,
      ctrl_wait               => ctrl_wait,
      ctrl_wr                 => ctrl_wr,
      ctrl_wrdata             => ctrl_wrdata,
      inbound_done_cnt        => inbound_done_cnt,
      inbound_drop_cnt        => inbound_drop_cnt,
      outbound_done_cnt       => outbound_done_cnt,
      outbound_drop_cnt       => outbound_drop_cnt,
      reset                   => reset,
      search_done_cnt         => search_done_cnt,
      search_drop_cnt         => search_drop_cnt);
 
  u5: esoc_fifo_256x16
    port map(
      aclr    => reset,
      data    => search_data,
      rdclk   => clk_data,
      rdreq   => Net_0,
      wrclk   => clk_search,
      wrreq   => Net_2,
      q       => Net_1,
      rdempty => rdempty,
      rdusedw => open,
      wrfull  => open,
      wrusedw => open);
 
  u6: esoc_ram_4kx1
    port map(
      address_a => inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan),
      address_b => ctrl_vlan_id,
      clock_a   => clk_search,
      clock_b   => clk_control,
      data_a    => (others => '0'),
      data_b    => ctrl_vlan_id_member,
      wren_a    => '0',
      wren_b    => ctrl_vlan_id_wr,
      q_a       => q_a,
      q_b       => q_b,
      rden_a    => '1',
      rden_b    => '1');
 
  u4: esoc_ram_4kx1
    port map(
      address_a => ctrl_vlan_id,
      address_b => outbound_vlan_id,
      clock_a   => clk_control,
      clock_b   => clk_data,
      data_a    => ctrl_vlan_id_member,
      data_b    => (others => '0'),
      wren_a    => ctrl_vlan_id_wr,
      wren_b    => '0',
      q_a       => open,
      q_b       => u4_q_b,
      rden_a    => '1',
      rden_b    => '1');
 
end architecture structure ; -- of esoc_port_processor
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_processor.vhd] - Blame information for rev 56

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2	53	lmaarsen	`--`
3			`-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.`
4			`--`
5			`-- Ease library : work`
6			`-- HDL library : work`
7			`-- Host name : S212065`
8			`-- User name : df768`
9			`-- Time stamp : Tue Aug 19 08:05:18 2014`
10			`--`
11			`-- Designed by : L.Maarsen`
12			`-- Company : LogiXA`
13			`-- Project info : eSoC`
14			`--`
15	42	lmaarsen	`--------------------------------------------------------------------------------`
16	53	lmaarsen
17	42	lmaarsen	`--------------------------------------------------------------------------------`
18			`-- Object : Entity work.esoc_port_processor`
19			`-- Last modified : Mon Apr 14 12:49:21 2014.`
20			`--------------------------------------------------------------------------------`
21
22
23
24			`library ieee, std, work;`
25			`use ieee.std_logic_1164.all;`
26			`use std.textio.all;`
27			`use ieee.numeric_std.all;`
28			`use work.package_esoc_configuration.all;`
29
30			`entity esoc_port_processor is`
31			`generic(`
32			`esoc_port_nr : integer := 0);`
33			`port(`
34			`clk_control : in std_logic;`
35			`clk_data : in std_logic;`
36			`clk_search : in std_logic;`
37			`ctrl_address : in std_logic_vector(15 downto 0);`
38			`ctrl_rd : in std_logic;`
39			`ctrl_rddata : out std_logic_vector(31 downto 0);`
40			`ctrl_wait : out std_logic;`
41			`ctrl_wr : in std_logic;`
42			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
43			`data : inout std_logic_vector(63 downto 0);`
44			`data_eof : inout std_logic;`
45			`data_gnt_rd : in std_logic;`
46			`data_gnt_wr : in std_logic;`
47			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
48			`data_req : out std_logic;`
49			`data_sof : inout std_logic;`
50			`inbound_data : in std_logic_vector(63 downto 0);`
51			`inbound_data_full : in std_logic;`
52			`inbound_data_read : out std_logic;`
53			`inbound_header : in std_logic_vector(111 downto 0);`
54			`inbound_header_empty : in std_logic;`
55			`inbound_header_read : out std_logic;`
56			`inbound_info : in std_logic_vector(31 downto 0);`
57			`inbound_info_empty : in std_logic;`
58			`inbound_info_read : out std_logic;`
59			`outbound_data : out std_logic_vector(63 downto 0);`
60			`outbound_data_full : in std_logic;`
61			`outbound_data_write : out std_logic;`
62			`outbound_info : out std_logic_vector(15 downto 0);`
63			`outbound_info_write : out std_logic;`
64			`reset : in std_logic;`
65			`search_eof : out std_logic;`
66			`search_gnt_wr : in std_logic;`
67			`search_key : out std_logic_vector(63 downto 0);`
68			`search_req : out std_logic;`
69			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
70			`search_result_av : in std_logic;`
71			`search_sof : out std_logic);`
72			`end entity esoc_port_processor;`
73
74			`--------------------------------------------------------------------------------`
75			`-- Object : Architecture work.esoc_port_processor.structure`
76			`-- Last modified : Mon Apr 14 12:49:21 2014.`
77			`--------------------------------------------------------------------------------`
78
79			`architecture structure of esoc_port_processor is`
80
81			`signal Net_0 : STD_LOGIC;`
82			`signal Net_1 : STD_LOGIC_VECTOR(15 downto 0);`
83			`signal rdempty : STD_LOGIC;`
84			`signal Net_2 : STD_LOGIC;`
85			`signal q_a : STD_LOGIC_VECTOR(0 downto 0);`
86			`signal outbound_drop_cnt : std_logic;`
87			`signal outbound_done_cnt : std_logic;`
88			`signal search_done_cnt : std_logic;`
89			`signal inbound_done_cnt : std_logic;`
90			`signal inbound_drop_cnt : std_logic;`
91			`signal ctrl_vlan_id : std_logic_vector(11 downto 0);`
92			`signal ctrl_vlan_id_member : std_logic_vector(0 downto 0);`
93			`signal outbound_vlan_id : STD_LOGIC_VECTOR(11 downto 0);`
94			`signal ctrl_vlan_id_wr : std_logic;`
95			`signal q_b : STD_LOGIC_VECTOR(0 downto 0);`
96			`signal search_data : STD_LOGIC_VECTOR(15 downto 0);`
97			`signal u4_q_b : STD_LOGIC_VECTOR(0 downto 0);`
98			`signal search_drop_cnt : std_logic;`
99
100			`component esoc_port_processor_search`
101			`generic(`
102			`esoc_port_nr : integer := 0);`
103			`port(`
104			`clk_search : in std_logic;`
105			`inbound_header : in std_logic_vector(111 downto 0);`
106			`inbound_header_empty : in std_logic;`
107			`inbound_header_read : out std_logic;`
108			`inbound_vlan_member : in STD_LOGIC_VECTOR(0 downto 0);`
109			`reset : in std_logic;`
110			`search_data : out STD_LOGIC_VECTOR(15 downto 0);`
111			`search_done_cnt : out std_logic;`
112			`search_drop_cnt : out std_logic;`
113			`search_eof : out std_logic;`
114			`search_gnt_wr : in std_logic;`
115			`search_key : out std_logic_vector(63 downto 0);`
116			`search_req : out std_logic;`
117			`search_result : in std_logic_vector(esoc_port_count-1 downto 0);`
118			`search_result_av : in std_logic;`
119			`search_sof : out std_logic;`
120			`search_write : out STD_LOGIC);`
121			`end component esoc_port_processor_search;`
122
123			`component esoc_port_processor_inbound`
124			`generic(`
125			`esoc_port_nr : integer := 0);`
126			`port(`
127			`clk_data : in std_logic;`
128			`data : inout std_logic_vector(63 downto 0);`
129			`data_eof : inout std_logic;`
130			`data_gnt_wr : in std_logic;`
131			`data_port_sel : inout std_logic_vector(esoc_port_count-1 downto 0);`
132			`data_req : out std_logic;`
133			`data_sof : inout std_logic;`
134			`inbound_data : in std_logic_vector(63 downto 0);`
135			`inbound_data_full : in std_logic;`
136			`inbound_data_read : out std_logic;`
137			`inbound_done_cnt : out std_logic;`
138			`inbound_drop_cnt : out std_logic;`
139			`inbound_info : in std_logic_vector(31 downto 0);`
140			`inbound_info_empty : in std_logic;`
141			`inbound_info_read : out std_logic;`
142			`reset : in std_logic;`
143			`search_data : in STD_LOGIC_VECTOR(15 downto 0);`
144			`search_empty : in STD_LOGIC;`
145			`search_read : out STD_LOGIC);`
146			`end component esoc_port_processor_inbound;`
147
148			`component esoc_port_processor_outbound`
149			`generic(`
150			`esoc_port_nr : integer := 0);`
151			`port(`
152			`clk_data : in std_logic;`
153			`data : in std_logic_vector(63 downto 0);`
154			`data_eof : in std_logic;`
155			`data_gnt_rd : in std_logic;`
156			`data_port_sel : in std_logic_vector(esoc_port_count-1 downto 0);`
157			`data_sof : in std_logic;`
158			`outbound_data : out std_logic_vector(63 downto 0);`
159			`outbound_data_full : in std_logic;`
160			`outbound_data_write : out std_logic;`
161			`outbound_done_cnt : out std_logic;`
162			`outbound_drop_cnt : out std_logic;`
163			`outbound_info : out std_logic_vector(15 downto 0);`
164			`outbound_info_write : out std_logic;`
165			`outbound_vlan_id : out STD_LOGIC_VECTOR(11 downto 0);`
166			`outbound_vlan_member : in STD_LOGIC_VECTOR(0 downto 0);`
167			`reset : in std_logic);`
168			`end component esoc_port_processor_outbound;`
169
170			`component esoc_port_processor_control`
171			`generic(`
172			`esoc_port_nr : integer := 0);`
173			`port(`
174			`clk_control : in std_logic;`
175			`clk_data : in std_logic;`
176			`clk_search : in std_logic;`
177			`ctrl_address : in std_logic_vector(15 downto 0);`
178			`ctrl_rd : in std_logic;`
179			`ctrl_rddata : out std_logic_vector(31 downto 0);`
180			`ctrl_vlan_id : out std_logic_vector(11 downto 0);`
181			`ctrl_vlan_id_member_in : in std_logic_vector(0 downto 0);`
182			`ctrl_vlan_id_member_out : out std_logic_vector(0 downto 0);`
183			`ctrl_vlan_id_wr : out std_logic;`
184			`ctrl_wait : out std_logic;`
185			`ctrl_wr : in std_logic;`
186			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
187			`inbound_done_cnt : in std_logic;`
188			`inbound_drop_cnt : in std_logic;`
189			`outbound_done_cnt : in std_logic;`
190			`outbound_drop_cnt : in std_logic;`
191			`reset : in STD_LOGIC := '0';`
192			`search_done_cnt : in std_logic;`
193			`search_drop_cnt : in std_logic);`
194			`end component esoc_port_processor_control;`
195
196			`component esoc_fifo_256x16`
197			`port(`
198			`aclr : in STD_LOGIC := '0';`
199			`data : in STD_LOGIC_VECTOR(15 downto 0);`
200			`rdclk : in STD_LOGIC;`
201			`rdreq : in STD_LOGIC;`
202			`wrclk : in STD_LOGIC;`
203			`wrreq : in STD_LOGIC;`
204			`q : out STD_LOGIC_VECTOR(15 downto 0);`
205			`rdempty : out STD_LOGIC;`
206			`rdusedw : out STD_LOGIC_VECTOR(7 downto 0);`
207			`wrfull : out STD_LOGIC;`
208			`wrusedw : out STD_LOGIC_VECTOR(7 downto 0));`
209			`end component esoc_fifo_256x16;`
210
211			`component esoc_ram_4kx1`
212			`port(`
213			`address_a : in STD_LOGIC_VECTOR(11 downto 0);`
214			`address_b : in STD_LOGIC_VECTOR(11 downto 0);`
215			`clock_a : in STD_LOGIC := '1';`
216			`clock_b : in STD_LOGIC;`
217			`data_a : in STD_LOGIC_VECTOR(0 downto 0);`
218			`data_b : in STD_LOGIC_VECTOR(0 downto 0);`
219			`wren_a : in STD_LOGIC := '0';`
220			`wren_b : in STD_LOGIC := '0';`
221			`q_a : out STD_LOGIC_VECTOR(0 downto 0);`
222			`q_b : out STD_LOGIC_VECTOR(0 downto 0);`
223			`rden_a : in STD_LOGIC := '1';`
224			`rden_b : in STD_LOGIC := '1');`
225			`end component esoc_ram_4kx1;`
226
227			`begin`
228			`--Search Engine Control`
229			`--Inbound Control - port to switch core`
230			`--Outbound Control - port to switch core`
231			`--Search Result FIFO`
232			`--VLAN Member Table`
233			`--Port Processor Control`
234			`--VLAN Member Table`
235			`u0: esoc_port_processor_search`
236			`generic map(`
237			`esoc_port_nr => esoc_port_nr)`
238			`port map(`
239			`clk_search => clk_search,`
240			`inbound_header => inbound_header,`
241			`inbound_header_empty => inbound_header_empty,`
242			`inbound_header_read => inbound_header_read,`
243			`inbound_vlan_member => q_a,`
244			`reset => reset,`
245			`search_data => search_data,`
246			`search_done_cnt => search_done_cnt,`
247			`search_drop_cnt => search_drop_cnt,`
248			`search_eof => search_eof,`
249			`search_gnt_wr => search_gnt_wr,`
250			`search_key => search_key,`
251			`search_req => search_req,`
252			`search_result => search_result,`
253			`search_result_av => search_result_av,`
254			`search_sof => search_sof,`
255			`search_write => Net_2);`
256
257			`u1: esoc_port_processor_inbound`
258			`generic map(`
259			`esoc_port_nr => esoc_port_nr)`
260			`port map(`
261			`clk_data => clk_data,`
262			`data => data,`
263			`data_eof => data_eof,`
264			`data_gnt_wr => data_gnt_wr,`
265			`data_port_sel => data_port_sel,`
266			`data_req => data_req,`
267			`data_sof => data_sof,`
268			`inbound_data => inbound_data,`
269			`inbound_data_full => inbound_data_full,`
270			`inbound_data_read => inbound_data_read,`
271			`inbound_done_cnt => inbound_done_cnt,`
272			`inbound_drop_cnt => inbound_drop_cnt,`
273			`inbound_info => inbound_info,`
274			`inbound_info_empty => inbound_info_empty,`
275			`inbound_info_read => inbound_info_read,`
276			`reset => reset,`
277			`search_data => Net_1,`
278			`search_empty => rdempty,`
279			`search_read => Net_0);`
280
281			`u2: esoc_port_processor_outbound`
282			`generic map(`
283			`esoc_port_nr => esoc_port_nr)`
284			`port map(`
285			`clk_data => clk_data,`
286			`data => data,`
287			`data_eof => data_eof,`
288			`data_gnt_rd => data_gnt_rd,`
289			`data_port_sel => data_port_sel,`
290			`data_sof => data_sof,`
291			`outbound_data => outbound_data,`
292			`outbound_data_full => outbound_data_full,`
293			`outbound_data_write => outbound_data_write,`
294			`outbound_done_cnt => outbound_done_cnt,`
295			`outbound_drop_cnt => outbound_drop_cnt,`
296			`outbound_info => outbound_info,`
297			`outbound_info_write => outbound_info_write,`
298			`outbound_vlan_id => outbound_vlan_id,`
299			`outbound_vlan_member => u4_q_b,`
300			`reset => reset);`
301
302			`u3: esoc_port_processor_control`
303			`generic map(`
304			`esoc_port_nr => esoc_port_nr)`
305			`port map(`
306			`clk_control => clk_control,`
307			`clk_data => clk_data,`
308			`clk_search => clk_search,`
309			`ctrl_address => ctrl_address,`
310			`ctrl_rd => ctrl_rd,`
311			`ctrl_rddata => ctrl_rddata,`
312			`ctrl_vlan_id => ctrl_vlan_id,`
313			`ctrl_vlan_id_member_in => q_b,`
314			`ctrl_vlan_id_member_out => ctrl_vlan_id_member,`
315			`ctrl_vlan_id_wr => ctrl_vlan_id_wr,`
316			`ctrl_wait => ctrl_wait,`
317			`ctrl_wr => ctrl_wr,`
318			`ctrl_wrdata => ctrl_wrdata,`
319			`inbound_done_cnt => inbound_done_cnt,`
320			`inbound_drop_cnt => inbound_drop_cnt,`
321			`outbound_done_cnt => outbound_done_cnt,`
322			`outbound_drop_cnt => outbound_drop_cnt,`
323			`reset => reset,`
324			`search_done_cnt => search_done_cnt,`
325			`search_drop_cnt => search_drop_cnt);`
326
327			`u5: esoc_fifo_256x16`
328			`port map(`
329			`aclr => reset,`
330			`data => search_data,`
331			`rdclk => clk_data,`
332			`rdreq => Net_0,`
333			`wrclk => clk_search,`
334			`wrreq => Net_2,`
335			`q => Net_1,`
336			`rdempty => rdempty,`
337			`rdusedw => open,`
338			`wrfull => open,`
339			`wrusedw => open);`
340
341			`u6: esoc_ram_4kx1`
342			`port map(`
343			`address_a => inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan),`
344			`address_b => ctrl_vlan_id,`
345			`clock_a => clk_search,`
346			`clock_b => clk_control,`
347			`data_a => (others => '0'),`
348			`data_b => ctrl_vlan_id_member,`
349			`wren_a => '0',`
350			`wren_b => ctrl_vlan_id_wr,`
351			`q_a => q_a,`
352			`q_b => q_b,`
353			`rden_a => '1',`
354			`rden_b => '1');`
355
356			`u4: esoc_ram_4kx1`
357			`port map(`
358			`address_a => ctrl_vlan_id,`
359			`address_b => outbound_vlan_id,`
360			`clock_a => clk_control,`
361			`clock_b => clk_data,`
362			`data_a => ctrl_vlan_id_member,`
363			`data_b => (others => '0'),`
364			`wren_a => ctrl_vlan_id_wr,`
365			`wren_b => '0',`
366			`q_a => open,`
367			`q_b => u4_q_b,`
368			`rden_a => '1',`
369			`rden_b => '1');`
370
371			`end architecture structure ; -- of esoc_port_processor`
372