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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_storage.vhd] - Blame information for rev 46

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1 42 lmaarsen
--------------------------------------------------------------------------------
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----                                                                        ----
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---- Ethernet Switch on Configurable Logic IP Core                          ----
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----                                                                        ----
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---- This file is part of the ESoCL project                                 ----
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---- http://www.opencores.org/cores/esoc/                                   ----
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----                                                                        ----
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---- Description: see design description ESoCL_dd_71022001.pdf              ----
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----                                                                        ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
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----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
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----                                                                        ----
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---- Author(s): L.Maarsen                                                   ----
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---- Bert Maarsen, lmaarsen@opencores.org                                   ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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----                                                                        ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
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----                                                                        ----
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---- This source file may be used and distributed without                   ----
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---- restriction provided that this copyright statement is not              ----
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---- removed from the file and that any derivative work contains            ----
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---- the original copyright notice and the associated disclaimer.           ----
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----                                                                        ----
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---- This source file is free software; you can redistribute it             ----
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---- and/or modify it under the terms of the GNU Lesser General             ----
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---- Public License as published by the Free Software Foundation;           ----
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---- either version 2.1 of the License, or (at your option) any             ----
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---- later version.                                                         ----
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----                                                                        ----
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---- This source is distributed in the hope that it will be                 ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
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---- PURPOSE. See the GNU Lesser General Public License for more            ----
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---- details.                                                               ----
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----                                                                        ----
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---- You should have received a copy of the GNU Lesser General              ----
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---- Public License along with this source; if not, download it             ----
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---- from http://www.opencores.org/lgpl.shtml                               ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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-- Object        : Entity work.esoc_port_storage
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-- Last modified : Mon Apr 14 12:49:43 2014.
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--------------------------------------------------------------------------------
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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entity esoc_port_storage is
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  port(
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    clk_control               : in     std_logic;
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    clk_data                  : in     std_logic;
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    clk_search                : in     std_logic;
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    inbound_port_data         : in     std_logic_vector(31 downto 0);
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    inbound_port_data_full    : out    std_logic;
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    inbound_port_data_write   : in     std_logic;
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    inbound_port_header       : in     std_logic_vector(111 downto 0);
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    inbound_port_header_write : in     std_logic;
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    inbound_port_info         : in     std_logic_vector(31 downto 0);
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    inbound_port_info_write   : in     std_logic;
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    inbound_proc_data         : out    std_logic_vector(63 downto 0);
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    inbound_proc_data_full    : out    std_logic;
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    inbound_proc_data_read    : in     std_logic;
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    inbound_proc_header       : out    std_logic_vector(111 downto 0);
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    inbound_proc_header_empty : out    std_logic;
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    inbound_proc_header_read  : in     std_logic;
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    inbound_proc_info         : out    std_logic_vector(31 downto 0);
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    inbound_proc_info_empty   : out    std_logic;
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    inbound_proc_info_read    : in     std_logic;
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    outbound_port_data        : out    std_logic_vector(31 downto 0);
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    outbound_port_data_read   : in     std_logic;
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    outbound_port_info        : out    std_logic_vector(15 downto 0);
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    outbound_port_info_empty  : out    std_logic;
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    outbound_port_info_read   : in     std_logic;
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    outbound_proc_data        : in     std_logic_vector(63 downto 0);
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    outbound_proc_data_full   : out    std_logic;
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    outbound_proc_data_write  : in     std_logic;
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    outbound_proc_info        : in     std_logic_vector(15 downto 0);
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    outbound_proc_info_write  : in     std_logic;
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    reset                     : in     std_logic);
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end entity esoc_port_storage;
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--------------------------------------------------------------------------------
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-- Object        : Architecture work.esoc_port_storage.structure
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-- Last modified : Mon Apr 14 12:49:43 2014.
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--------------------------------------------------------------------------------
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architecture structure of esoc_port_storage is
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  signal inbound_wrusedw : STD_LOGIC_VECTOR(10 downto 0);
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  signal inbound_rdusedw : STD_LOGIC_VECTOR(9 downto 0);
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  component esoc_fifo_256x32
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    port(
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      aclr    : in     STD_LOGIC := '0';
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      data    : in     STD_LOGIC_VECTOR(31 downto 0);
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      rdclk   : in     STD_LOGIC;
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      rdreq   : in     STD_LOGIC;
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      wrclk   : in     STD_LOGIC;
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      wrreq   : in     STD_LOGIC;
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      q       : out    STD_LOGIC_VECTOR(31 downto 0);
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      rdempty : out    STD_LOGIC;
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      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);
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      wrfull  : out    STD_LOGIC;
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      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));
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  end component esoc_fifo_256x32;
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  component esoc_fifo_256x112
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    port(
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      aclr    : in     STD_LOGIC := '0';
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      data    : in     STD_LOGIC_VECTOR(111 downto 0);
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      rdclk   : in     STD_LOGIC;
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      rdreq   : in     STD_LOGIC;
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      wrclk   : in     STD_LOGIC;
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      wrreq   : in     STD_LOGIC;
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      q       : out    STD_LOGIC_VECTOR(111 downto 0);
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      rdempty : out    STD_LOGIC;
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      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);
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      wrfull  : out    STD_LOGIC;
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      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));
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  end component esoc_fifo_256x112;
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  component esoc_fifo_256x16
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    port(
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      aclr    : in     STD_LOGIC := '0';
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      data    : in     STD_LOGIC_VECTOR(15 downto 0);
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      rdclk   : in     STD_LOGIC;
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      rdreq   : in     STD_LOGIC;
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      wrclk   : in     STD_LOGIC;
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      wrreq   : in     STD_LOGIC;
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      q       : out    STD_LOGIC_VECTOR(15 downto 0);
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      rdempty : out    STD_LOGIC;
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      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);
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      wrfull  : out    STD_LOGIC;
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      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));
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  end component esoc_fifo_256x16;
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  component esoc_fifo_2kx32x64
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    port(
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      aclr    : in     STD_LOGIC := '0';
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      data    : in     STD_LOGIC_VECTOR(31 downto 0);
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      rdclk   : in     STD_LOGIC;
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      rdreq   : in     STD_LOGIC;
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      wrclk   : in     STD_LOGIC;
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      wrreq   : in     STD_LOGIC;
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      q       : out    STD_LOGIC_VECTOR(63 downto 0);
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      rdempty : out    STD_LOGIC;
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      rdusedw : out    STD_LOGIC_VECTOR(9 downto 0);
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      wrfull  : out    STD_LOGIC;
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      wrusedw : out    STD_LOGIC_VECTOR(10 downto 0));
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  end component esoc_fifo_2kx32x64;
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  component esoc_fifo_2kx64x32
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    port(
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      aclr    : in     STD_LOGIC := '0';
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      data    : in     STD_LOGIC_VECTOR(63 downto 0);
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      rdclk   : in     STD_LOGIC;
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      rdreq   : in     STD_LOGIC;
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      wrclk   : in     STD_LOGIC;
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      wrreq   : in     STD_LOGIC;
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      q       : out    STD_LOGIC_VECTOR(31 downto 0);
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      rdempty : out    STD_LOGIC;
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      rdusedw : out    STD_LOGIC_VECTOR(10 downto 0);
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      wrfull  : out    STD_LOGIC;
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      wrusedw : out    STD_LOGIC_VECTOR(9 downto 0));
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  end component esoc_fifo_2kx64x32;
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begin
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  --Inbound FIFO's
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  --- Data Fifo
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  --- Info Fifo
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  --- Header Fifo
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  --Outbound FIFO's
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  --- Data Fifo
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  --- Info Fifo
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  u1: esoc_fifo_256x32
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    port map(
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      aclr    => reset,
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      data    => inbound_port_info,
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      rdclk   => clk_data,
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      rdreq   => inbound_proc_info_read,
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      wrclk   => clk_control,
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      wrreq   => inbound_port_info_write,
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      q       => inbound_proc_info,
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      rdempty => inbound_proc_info_empty,
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      rdusedw => open,
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      wrfull  => open,
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      wrusedw => open);
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  u4: esoc_fifo_256x112
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    port map(
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      aclr    => reset,
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      data    => inbound_port_header,
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      rdclk   => clk_search,
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      rdreq   => inbound_proc_header_read,
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      wrclk   => clk_control,
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      wrreq   => inbound_port_header_write,
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      q       => inbound_proc_header,
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      rdempty => inbound_proc_header_empty,
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      rdusedw => open,
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      wrfull  => open,
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      wrusedw => open);
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  u5: esoc_fifo_256x16
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    port map(
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      aclr    => reset,
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      data    => outbound_proc_info,
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      rdclk   => clk_control,
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      rdreq   => outbound_port_info_read,
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      wrclk   => clk_data,
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      wrreq   => outbound_proc_info_write,
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      q       => outbound_port_info,
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      rdempty => outbound_port_info_empty,
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      rdusedw => open,
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      wrfull  => open,
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      wrusedw => open);
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  u6: esoc_fifo_2kx32x64
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    port map(
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      aclr    => reset,
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      data    => inbound_port_data,
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      rdclk   => clk_data,
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      rdreq   => inbound_proc_data_read,
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      wrclk   => clk_control,
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      wrreq   => inbound_port_data_write,
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      q       => inbound_proc_data,
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      rdempty => open,
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      rdusedw => inbound_rdusedw,
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      wrfull  => open,
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      wrusedw => inbound_wrusedw);
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  u0: esoc_fifo_2kx64x32
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    port map(
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      aclr    => reset,
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      data    => outbound_proc_data,
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      rdclk   => clk_control,
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      rdreq   => outbound_port_data_read,
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      wrclk   => clk_data,
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      wrreq   => outbound_proc_data_write,
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      q       => outbound_port_data,
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      rdempty => open,
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      rdusedw => open,
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      wrfull  => outbound_proc_data_full,
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      wrusedw => open);
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  -- FIFO Behaviour:                  ST to Write FIFO latency is 1 clock cycle, take this into account 
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  --                                  WRUSEDW latency is 1 clock cycle, take this into account 
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  --                                  WRUSEDW becomes 2047 -> 0 when FIFO is completely full, take this into account 
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  --                                  WRUSEDW must end on an even number of words due to 32/64 conversion, take this into account
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  --                                  Conclusion: set Almost Full threshold offset on 3
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  --
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  --                                  Ready Latency @ ST Interface is 2
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  --
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  --                                  Required Almost Full threshold:  1 + 1 + 1 + 1 + 2 = 6
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  --
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  inbound_port_data_full <= '1' when (2**inbound_wrusedw'length - to_integer(unsigned(inbound_wrusedw))) <= 6 else '0';
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  --
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  inbound_proc_data_full <= '1' when to_integer(unsigned(inbound_rdusedw)) = ((2**inbound_rdusedw'length)-1) else '0';
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end architecture structure ; -- of esoc_port_storage
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