Subversion Repositories esoc

--------------------------------------------------------------------------------

----                                                                        ----

---- Ethernet Switch on Configurable Logic IP Core                          ----

----                                                                        ----

---- This file is part of the ESoCL project                                 ----

---- http://www.opencores.org/cores/esoc/                                   ----

----                                                                        ----

---- Description: see design description ESoCL_dd_71022001.pdf              ----

----                                                                        ----

---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----

----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----

----                                                                        ----

---- Author(s): L.Maarsen                                                   ----

---- Bert Maarsen, lmaarsen@opencores.org                                   ----

----                                                                        ----

--------------------------------------------------------------------------------

----                                                                        ----

---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----

----                                                                        ----

---- This source file may be used and distributed without                   ----

---- restriction provided that this copyright statement is not              ----

---- removed from the file and that any derivative work contains            ----

---- the original copyright notice and the associated disclaimer.           ----

----                                                                        ----

---- This source file is free software; you can redistribute it             ----

---- and/or modify it under the terms of the GNU Lesser General             ----

---- Public License as published by the Free Software Foundation;           ----

---- either version 2.1 of the License, or (at your option) any             ----

---- later version.                                                         ----

----                                                                        ----

---- This source is distributed in the hope that it will be                 ----

---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----

---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----

---- PURPOSE. See the GNU Lesser General Public License for more            ----

---- details.                                                               ----

----                                                                        ----

---- You should have received a copy of the GNU Lesser General              ----

---- Public License along with this source; if not, download it             ----

---- from http://www.opencores.org/lgpl.shtml                               ----

----                                                                        ----

--------------------------------------------------------------------------------

-- Object        : Entity work.esoc_port_storage

-- Last modified : Mon Apr 14 12:49:43 2014.

--------------------------------------------------------------------------------

library ieee, std, work;

use ieee.std_logic_1164.all;

use std.textio.all;

use ieee.numeric_std.all;

use work.package_esoc_configuration.all;

entity esoc_port_storage is

  port(

    clk_control               : in     std_logic;

    clk_data                  : in     std_logic;

    clk_search                : in     std_logic;

    inbound_port_data         : in     std_logic_vector(31 downto 0);

    inbound_port_data_full    : out    std_logic;

    inbound_port_data_write   : in     std_logic;

    inbound_port_header       : in     std_logic_vector(111 downto 0);

    inbound_port_header_write : in     std_logic;

    inbound_port_info         : in     std_logic_vector(31 downto 0);

    inbound_port_info_write   : in     std_logic;

    inbound_proc_data         : out    std_logic_vector(63 downto 0);

    inbound_proc_data_full    : out    std_logic;

    inbound_proc_data_read    : in     std_logic;

    inbound_proc_header       : out    std_logic_vector(111 downto 0);

    inbound_proc_header_empty : out    std_logic;

    inbound_proc_header_read  : in     std_logic;

    inbound_proc_info         : out    std_logic_vector(31 downto 0);

    inbound_proc_info_empty   : out    std_logic;

    inbound_proc_info_read    : in     std_logic;

    outbound_port_data        : out    std_logic_vector(31 downto 0);

    outbound_port_data_read   : in     std_logic;

    outbound_port_info        : out    std_logic_vector(15 downto 0);

    outbound_port_info_empty  : out    std_logic;

    outbound_port_info_read   : in     std_logic;

    outbound_proc_data        : in     std_logic_vector(63 downto 0);

    outbound_proc_data_full   : out    std_logic;

    outbound_proc_data_write  : in     std_logic;

    outbound_proc_info        : in     std_logic_vector(15 downto 0);

    outbound_proc_info_write  : in     std_logic;

    reset                     : in     std_logic);

end entity esoc_port_storage;

--------------------------------------------------------------------------------

-- Object        : Architecture work.esoc_port_storage.structure

-- Last modified : Mon Apr 14 12:49:43 2014.

--------------------------------------------------------------------------------

architecture structure of esoc_port_storage is

  signal inbound_wrusedw : STD_LOGIC_VECTOR(10 downto 0);

  signal inbound_rdusedw : STD_LOGIC_VECTOR(9 downto 0);

  component esoc_fifo_256x32

    port(

      aclr    : in     STD_LOGIC := '0';

      data    : in     STD_LOGIC_VECTOR(31 downto 0);

      rdclk   : in     STD_LOGIC;

      rdreq   : in     STD_LOGIC;

      wrclk   : in     STD_LOGIC;

      wrreq   : in     STD_LOGIC;

      q       : out    STD_LOGIC_VECTOR(31 downto 0);

      rdempty : out    STD_LOGIC;

      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);

      wrfull  : out    STD_LOGIC;

      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));

  end component esoc_fifo_256x32;

  component esoc_fifo_256x112

    port(

      aclr    : in     STD_LOGIC := '0';

      data    : in     STD_LOGIC_VECTOR(111 downto 0);

      rdclk   : in     STD_LOGIC;

      rdreq   : in     STD_LOGIC;

      wrclk   : in     STD_LOGIC;

      wrreq   : in     STD_LOGIC;

      q       : out    STD_LOGIC_VECTOR(111 downto 0);

      rdempty : out    STD_LOGIC;

      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);

      wrfull  : out    STD_LOGIC;

      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));

  end component esoc_fifo_256x112;

  component esoc_fifo_256x16

    port(

      aclr    : in     STD_LOGIC := '0';

      data    : in     STD_LOGIC_VECTOR(15 downto 0);

      rdclk   : in     STD_LOGIC;

      rdreq   : in     STD_LOGIC;

      wrclk   : in     STD_LOGIC;

      wrreq   : in     STD_LOGIC;

      q       : out    STD_LOGIC_VECTOR(15 downto 0);

      rdempty : out    STD_LOGIC;

      rdusedw : out    STD_LOGIC_VECTOR(7 downto 0);

      wrfull  : out    STD_LOGIC;

      wrusedw : out    STD_LOGIC_VECTOR(7 downto 0));

  end component esoc_fifo_256x16;

  component esoc_fifo_2kx32x64

    port(

      aclr    : in     STD_LOGIC := '0';

      data    : in     STD_LOGIC_VECTOR(31 downto 0);

      rdclk   : in     STD_LOGIC;

      rdreq   : in     STD_LOGIC;

      wrclk   : in     STD_LOGIC;

      wrreq   : in     STD_LOGIC;

      q       : out    STD_LOGIC_VECTOR(63 downto 0);

      rdempty : out    STD_LOGIC;

      rdusedw : out    STD_LOGIC_VECTOR(9 downto 0);

      wrfull  : out    STD_LOGIC;

      wrusedw : out    STD_LOGIC_VECTOR(10 downto 0));

  end component esoc_fifo_2kx32x64;

  component esoc_fifo_2kx64x32

    port(

      aclr    : in     STD_LOGIC := '0';

      data    : in     STD_LOGIC_VECTOR(63 downto 0);

      rdclk   : in     STD_LOGIC;

      rdreq   : in     STD_LOGIC;

      wrclk   : in     STD_LOGIC;

      wrreq   : in     STD_LOGIC;

      q       : out    STD_LOGIC_VECTOR(31 downto 0);

      rdempty : out    STD_LOGIC;

      rdusedw : out    STD_LOGIC_VECTOR(10 downto 0);

      wrfull  : out    STD_LOGIC;

      wrusedw : out    STD_LOGIC_VECTOR(9 downto 0));

  end component esoc_fifo_2kx64x32;

begin

  --Inbound FIFO's

  --- Data Fifo

  --- Info Fifo

  --- Header Fifo

  --Outbound FIFO's

  --- Data Fifo

  --- Info Fifo

  u1: esoc_fifo_256x32

    port map(

      aclr    => reset,

      data    => inbound_port_info,

      rdclk   => clk_data,

      rdreq   => inbound_proc_info_read,

      wrclk   => clk_control,

      wrreq   => inbound_port_info_write,

      q       => inbound_proc_info,

      rdempty => inbound_proc_info_empty,

      rdusedw => open,

      wrfull  => open,

      wrusedw => open);

  u4: esoc_fifo_256x112

    port map(

      aclr    => reset,

      data    => inbound_port_header,

      rdclk   => clk_search,

      rdreq   => inbound_proc_header_read,

      wrclk   => clk_control,

      wrreq   => inbound_port_header_write,

      q       => inbound_proc_header,

      rdempty => inbound_proc_header_empty,

      rdusedw => open,

      wrfull  => open,

      wrusedw => open);

  u5: esoc_fifo_256x16

    port map(

      aclr    => reset,

      data    => outbound_proc_info,

      rdclk   => clk_control,

      rdreq   => outbound_port_info_read,

      wrclk   => clk_data,

      wrreq   => outbound_proc_info_write,

      q       => outbound_port_info,

      rdempty => outbound_port_info_empty,

      rdusedw => open,

      wrfull  => open,

      wrusedw => open);

  u6: esoc_fifo_2kx32x64

    port map(

      aclr    => reset,

      data    => inbound_port_data,

      rdclk   => clk_data,

      rdreq   => inbound_proc_data_read,

      wrclk   => clk_control,

      wrreq   => inbound_port_data_write,

      q       => inbound_proc_data,

      rdempty => open,

      rdusedw => inbound_rdusedw,

      wrfull  => open,

      wrusedw => inbound_wrusedw);

  u0: esoc_fifo_2kx64x32

    port map(

      aclr    => reset,

      data    => outbound_proc_data,

      rdclk   => clk_control,

      rdreq   => outbound_port_data_read,

      wrclk   => clk_data,

      wrreq   => outbound_proc_data_write,

      q       => outbound_port_data,

      rdempty => open,

      rdusedw => open,

      wrfull  => outbound_proc_data_full,

      wrusedw => open);

  -- FIFO Behaviour:                  ST to Write FIFO latency is 1 clock cycle, take this into account 

  --                                  WRUSEDW latency is 1 clock cycle, take this into account 

  --                                  WRUSEDW becomes 2047 -> 0 when FIFO is completely full, take this into account 

  --                                  WRUSEDW must end on an even number of words due to 32/64 conversion, take this into account

  --                                  Conclusion: set Almost Full threshold offset on 3

  --

  --                                  Ready Latency @ ST Interface is 2

  --

  --                                  Required Almost Full threshold:  1 + 1 + 1 + 1 + 2 = 6

  --

  inbound_port_data_full <= '1' when (2**inbound_wrusedw'length - to_integer(unsigned(inbound_wrusedw))) <= 6 else '0';

  --

  inbound_proc_data_full <= '1' when to_integer(unsigned(inbound_rdusedw)) = ((2**inbound_rdusedw'length)-1) else '0';

end architecture structure ; -- of esoc_port_storage